openpower.mdwn

   1 # Evaluation
   2
   3 EULA released! looks good.
   4
   5 Links
   6
   7 * https://forums.raptorcs.com/
   8 * http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev
   9 * http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo
  10 * http://bugs.libre-riscv.org/show_bug.cgi?id=179
  11 * https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0
  12 * https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b
  13
  14 Summary
  15
  16 * FP32 is converted to FP64. Requires SimpleV to be active.
  17 * FP16 needed
  18 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  19 * FCVT between 16/32/64 needed
  20 * c++11 atomics not very efficient
  21 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  22 * needs escape sequencing (ISAMUX/NS)
  23
  24 # SimpleV
  25
  26 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
  27 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  28 register files to "a sequence of elements".  The **one** instruction
  29 (an unmodified **scalar** instruction) is interpreted as a *hardware
  30 for-loop* that issues **multiple** internal instructions with
  31 sequentially-incrementing register numbers.
  32
  33 Thus it is completely unnecessary to add any vector opcodes - at all -
  34 saving hugely on both hardware and compiler development time when
  35 the concept is dropped on top of a pre-existing ISA.
  36
  37 # atomics
  38
  39 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  40
  41 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  42
  43 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  44
  45 # FP16
  46
  47 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  48
  49 Usually done with a fmt field, 2 bit, last one is FP128
  50
  51 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  52
  53 # Escape Sequencing
  54
  55 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
  56 from OpenPower Foundation.
  57
  58 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
  59 (including for and by OpenPower Foundation)
  60
  61 ## Branches in namespaces
  62
  63 Branches are fine as it is up to the compiler to decide whether to let the
  64 ISAMUX/NS/escape-sequence countdown run out.
  65
  66 This is all a software / compiler / ABI issue.
  67
  68 ## Function calls in namespaces
  69
  70 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
  71
  72 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
  73
  74 All of this is a software issue (compiler / ABI).
  75
  76 # Compressed, 48, 64, VBLOCK
  77
  78 TODO investigate Power VLE (Freescale doc Ref 314-68105)
  79
  80 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
  81 entire row, 2 bits instead of 3.  greatly simplifies decoder.
  82
  83 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
  84 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
  85 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
  86 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
  87
  88 # Compressed 16
  89
  90 Further "escape-sequencing".
  91
  92 Only 11 bits available. Idea: have "pages" where one instruction selects
  93 the page number. It also specifies for how long that page is activated
  94 (terminated on a branch)
  95
  96 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
  97
  98 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
  99
 100 Store activation length in a CSR.
 101
 102 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 103
 104 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 105
 106 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 107
 108 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 109
 110 # RISCV userspace
 111
 112 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 113
 114 the exception entry point:
 115 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
 116
 117 the rest of the context switch code is in a different file:
 118 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589