openpower.mdwn

   1 # OpenPOWER
   2 In the late 1980s [[!wikipedia IBM]] developed a POWER family of processors.
   3 This evolved to a specification known as the Power ISA. In 2019 IBM made the Power ISA [[!wikipedia Open_source]] to be looked after by the existing [[!wikipedia OpenPOWER_Foundation]]. Here is a longer history of [[!wikipedia IBM_POWER_microprocessors]].
   4
   5 Libre-soc is basing its [[Simple-V Vectorisation|sv]] CPU extensions on OpenPOWER because it wants to be able to specify a machine that can be completely trusted.
   6
   7 # Evaluation
   8
   9 EULA released! looks good.
  10
  11 Links
  12
  13 * OpenPOWER Membership
  14   <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
  15 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
  16 * [[openpower/isatables]]
  17 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
  18 * [[openpower/gem5]]
  19 * [[openpower/sv]]
  20 * [[openpower/simd_vsx]]
  21 * [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
  22 * [[openpower/pearpc]]
  23 * [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
  24 * [[3d_gpu/architecture/decoder]]
  25 * <https://forums.raptorcs.com/>
  26 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  27 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  28 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  29 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  30 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  31
  32 PowerPC Unit Tests
  33
  34 * <https://github.com/lioncash/DolphinPPCTests>
  35 * <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
  36
  37 Summary
  38
  39 * FP32 is converted to FP64. Requires SimpleV to be active.
  40 * FP16 needed
  41 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  42 * FCVT between 16/32/64 needed
  43 * c++11 atomics not very efficient
  44 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  45 * needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
  46
  47 # What we are *NOT* doing:
  48
  49 * A processor that is fundamentally incompatible (noncompliant) with Power.
  50  (**escape-sequencing requires and guarantees compatibility**).
  51 * Opcode 4 Signal Processing (SPE)
  52 * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
  53 * Avoidable legacy opcodes
  54
  55 # SimpleV
  56
  57 see [[openpower/sv]].
  58 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  59 register files to "a sequence of elements".  The **one** instruction
  60 (an unmodified **scalar** instruction) is interpreted as a *hardware
  61 for-loop* that issues **multiple** internal instructions with
  62 sequentially-incrementing register numbers.
  63
  64 Thus it is completely unnecessary to add any vector opcodes - at all -
  65 saving hugely on both hardware and compiler development time when
  66 the concept is dropped on top of a pre-existing ISA.
  67
  68 ## Condition Registers
  69
  70 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  71
  72 ## Carry
  73
  74 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Most sensible location to use is the CRs
  75
  76 # Integer Overflow / Saturate
  77
  78 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  79
  80 # atomics
  81
  82 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  83
  84 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  85
  86 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  87
  88 # FP16
  89
  90 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  91
  92 Usually done with a fmt field, 2 bit, last one is FP128
  93
  94 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  95
  96 # Escape Sequencing
  97
  98 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
  99 from OpenPower Foundation.
 100
 101 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
 102 (including for and by OpenPower Foundation)
 103
 104 ## Branches in namespaces
 105
 106 Branches are fine as it is up to the compiler to decide whether to let the
 107 ISAMUX/NS/escape-sequence countdown run out.
 108
 109 This is all a software / compiler / ABI issue.
 110
 111 ## Function calls in namespaces
 112
 113 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
 114
 115 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
 116
 117 All of this is a software issue (compiler / ABI).
 118
 119 # Compressed, 48, 64, VBLOCK
 120
 121 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 122
 123 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 124 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 125
 126 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 127 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 128 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 129 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 130
 131 Note that this requires BE instruction encoding (separate from
 132 data BE/LE encoding).  BE encoding always places the major opcode in
 133 the first 2 bytes of the raw (uninterpreted) sequential instruction
 134 byte stream.
 135
 136 Thus in BE-instruction-mode, the first 2 bytes may be analysed to
 137 detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
 138 64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
 139
 140 It is not possible to distinguish LE-encoded 32-bit instructions
 141 from LE-encoded 16-bit instructions because in LE-encoded 32-bit
 142 instructions, the opcode falls into:
 143
 144 * bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
 145   byte stream for a 32-bit instruction
 146 * bytes 0 and 1 for a 16-bit Compressed instruction
 147 * bytes 4 and 5 for a 48-bit SVP P48
 148 * bytes 6 and 7 for a 64-bit SVP P64
 149
 150 Clearly this is an impossible situation, therefore BE is the only
 151 option.  Note: *this is completely separate from BE/LE for data*
 152
 153 # Compressed 16
 154
 155 Further "escape-sequencing".
 156
 157 Only 11 bits available. Idea: have "pages" where one instruction selects
 158 the page number. It also specifies for how long that page is activated
 159 (terminated on a branch)
 160
 161 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 162
 163 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 164
 165 Store activation length in a CSR.
 166
 167 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 168
 169 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 170
 171 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 172
 173 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 174
 175 # RISCV userspace
 176
 177 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 178
 179 the exception entry point:
 180 <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
 181
 182 the rest of the context switch code is in a different file:
 183 <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>