4 * Copyright (c) 1998-2017 Stephen Williams (steve@icarus.com)
5 * Copyright CERN 2012-2013 / Stephen Williams (steve@icarus.com)
7 * This source code is free software; you can redistribute it
8 * and/or modify it in source code form under the terms of the GNU
9 * General Public License as published by the Free Software
10 * Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
25 # include "parse_misc.h"
26 # include "compiler.h"
28 # include "Statement.h"
36 extern void lex_end_table();
38 static list<pform_range_t>* param_active_range = 0;
39 static bool param_active_signed = false;
40 static ivl_variable_type_t param_active_type = IVL_VT_LOGIC;
42 /* Port declaration lists use this structure for context. */
44 NetNet::Type port_net_type;
45 NetNet::PortType port_type;
46 data_type_t* data_type;
47 } port_declaration_context = {NetNet::NONE, NetNet::NOT_A_PORT, 0};
49 /* Modport port declaration lists use this structure for context. */
50 enum modport_port_type_t { MP_NONE, MP_SIMPLE, MP_TF, MP_CLOCKING };
52 modport_port_type_t type;
54 NetNet::PortType direction;
57 } last_modport_port = { MP_NONE, {NetNet::NOT_A_PORT}};
59 /* The task and function rules need to briefly hold the pointer to the
60 task/function that is currently in progress. */
61 static PTask* current_task = 0;
62 static PFunction* current_function = 0;
63 static stack<PBlock*> current_block_stack;
65 /* The variable declaration rules need to know if a lifetime has been
67 static LexicalScope::lifetime_t var_lifetime;
69 static pform_name_t* pform_create_this(void)
71 name_component_t name (perm_string::literal("@"));
72 pform_name_t*res = new pform_name_t;
77 static pform_name_t* pform_create_super(void)
79 name_component_t name (perm_string::literal("#"));
80 pform_name_t*res = new pform_name_t;
85 /* This is used to keep track of the extra arguments after the notifier
86 * in the $setuphold and $recrem timing checks. This allows us to print
87 * a warning message that the delayed signals will not be created. We
88 * need to do this since not driving these signals creates real
89 * simulation issues. */
90 static unsigned args_after_notifier;
92 /* The rules sometimes push attributes into a global context where
93 sub-rules may grab them. This makes parser rules a little easier to
94 write in some cases. */
95 static list<named_pexpr_t>*attributes_in_context = 0;
97 /* Later version of bison (including 1.35) will not compile in stack
98 extension if the output is compiled with C++ and either the YYSTYPE
99 or YYLTYPE are provided by the source code. However, I can get the
100 old behavior back by defining these symbols. */
101 # define YYSTYPE_IS_TRIVIAL 1
102 # define YYLTYPE_IS_TRIVIAL 1
104 /* Recent version of bison expect that the user supply a
105 YYLLOC_DEFAULT macro that makes up a yylloc value from existing
106 values. I need to supply an explicit version to account for the
107 text field, that otherwise won't be copied.
109 The YYLLOC_DEFAULT blends the file range for the tokens of Rhs
110 rule, which has N tokens.
112 # define YYLLOC_DEFAULT(Current, Rhs, N) do { \
114 (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \
115 (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \
116 (Current).last_line = YYRHSLOC (Rhs, N).last_line; \
117 (Current).last_column = YYRHSLOC (Rhs, N).last_column; \
118 (Current).text = YYRHSLOC (Rhs, 1).text; \
120 (Current).first_line = YYRHSLOC (Rhs, 0).last_line; \
121 (Current).first_column = YYRHSLOC (Rhs, 0).last_column; \
122 (Current).last_line = YYRHSLOC (Rhs, 0).last_line; \
123 (Current).last_column = YYRHSLOC (Rhs, 0).last_column; \
124 (Current).text = YYRHSLOC (Rhs, 0).text; \
129 * These are some common strength pairs that are used as defaults when
130 * the user is not otherwise specific.
132 static const struct str_pair_t pull_strength = { IVL_DR_PULL, IVL_DR_PULL };
133 static const struct str_pair_t str_strength = { IVL_DR_STRONG, IVL_DR_STRONG };
135 static list<pform_port_t>* make_port_list(char*id, list<pform_range_t>*udims, PExpr*expr)
137 list<pform_port_t>*tmp = new list<pform_port_t>;
138 tmp->push_back(pform_port_t(lex_strings.make(id), udims, expr));
142 static list<pform_port_t>* make_port_list(list<pform_port_t>*tmp,
143 char*id, list<pform_range_t>*udims, PExpr*expr)
145 tmp->push_back(pform_port_t(lex_strings.make(id), udims, expr));
150 list<pform_range_t>* make_range_from_width(uint64_t wid)
153 range.first = new PENumber(new verinum(wid-1, integer_width));
154 range.second = new PENumber(new verinum((uint64_t)0, integer_width));
156 list<pform_range_t>*rlist = new list<pform_range_t>;
157 rlist->push_back(range);
161 static list<perm_string>* list_from_identifier(char*id)
163 list<perm_string>*tmp = new list<perm_string>;
164 tmp->push_back(lex_strings.make(id));
169 static list<perm_string>* list_from_identifier(list<perm_string>*tmp, char*id)
171 tmp->push_back(lex_strings.make(id));
176 list<pform_range_t>* copy_range(list<pform_range_t>* orig)
178 list<pform_range_t>*copy = 0;
181 copy = new list<pform_range_t> (*orig);
186 template <class T> void append(vector<T>&out, const vector<T>&in)
188 for (size_t idx = 0 ; idx < in.size() ; idx += 1)
189 out.push_back(in[idx]);
193 * Look at the list and pull null pointers off the end.
195 static void strip_tail_items(list<PExpr*>*lst)
197 while (! lst->empty()) {
198 if (lst->back() != 0)
205 * This is a shorthand for making a PECallFunction that takes a single
206 * arg. This is used by some of the code that detects built-ins.
208 static PECallFunction*make_call_function(perm_string tn, PExpr*arg)
210 vector<PExpr*> parms(1);
212 PECallFunction*tmp = new PECallFunction(tn, parms);
216 static PECallFunction*make_call_function(perm_string tn, PExpr*arg1, PExpr*arg2)
218 vector<PExpr*> parms(2);
221 PECallFunction*tmp = new PECallFunction(tn, parms);
225 static list<named_pexpr_t>* make_named_numbers(perm_string name, long first, long last, PExpr*val =0)
227 list<named_pexpr_t>*lst = new list<named_pexpr_t>;
229 // We are counting up.
231 for (long idx = first ; idx <= last ; idx += 1) {
233 buf << name.str() << idx << ends;
234 tmp.name = lex_strings.make(buf.str());
239 // We are counting down.
241 for (long idx = first ; idx >= last ; idx -= 1) {
243 buf << name.str() << idx << ends;
244 tmp.name = lex_strings.make(buf.str());
253 static list<named_pexpr_t>* make_named_number(perm_string name, PExpr*val =0)
255 list<named_pexpr_t>*lst = new list<named_pexpr_t>;
263 static long check_enum_seq_value(const YYLTYPE&loc, verinum *arg, bool zero_ok)
266 // We can never have an undefined value in an enumeration name
267 // declaration sequence.
268 if (! arg->is_defined()) {
269 yyerror(loc, "error: undefined value used in enum name sequence.");
270 // We can never have a negative value in an enumeration name
271 // declaration sequence.
272 } else if (arg->is_negative()) {
273 yyerror(loc, "error: negative value used in enum name sequence.");
275 value = arg->as_ulong();
276 // We cannot have a zero enumeration name declaration count.
277 if (! zero_ok && (value == 0)) {
278 yyerror(loc, "error: zero count used in enum name sequence.");
285 static void current_task_set_statement(const YYLTYPE&loc, vector<Statement*>*s)
288 /* if the statement list is null, then the parser
289 detected the case that there are no statements in the
290 task. If this is SystemVerilog, handle it as an
292 if (!gn_system_verilog()) {
293 yyerror(loc, "error: Support for empty tasks requires SystemVerilog.");
295 PBlock*tmp = new PBlock(PBlock::BL_SEQ);
297 current_task->set_statement(tmp);
302 /* An empty vector represents one or more null statements. Handle
303 this as a simple null statement. */
307 /* A vector of 1 is handled as a simple statement. */
308 if (s->size() == 1) {
309 current_task->set_statement((*s)[0]);
313 if (!gn_system_verilog()) {
314 yyerror(loc, "error: Task body with multiple statements requires SystemVerilog.");
317 PBlock*tmp = new PBlock(PBlock::BL_SEQ);
319 tmp->set_statement(*s);
320 current_task->set_statement(tmp);
323 static void current_function_set_statement(const YYLTYPE&loc, vector<Statement*>*s)
326 /* if the statement list is null, then the parser
327 detected the case that there are no statements in the
328 task. If this is SystemVerilog, handle it as an
330 if (!gn_system_verilog()) {
331 yyerror(loc, "error: Support for empty functions requires SystemVerilog.");
333 PBlock*tmp = new PBlock(PBlock::BL_SEQ);
335 current_function->set_statement(tmp);
340 /* An empty vector represents one or more null statements. Handle
341 this as a simple null statement. */
345 /* A vector of 1 is handled as a simple statement. */
346 if (s->size() == 1) {
347 current_function->set_statement((*s)[0]);
351 if (!gn_system_verilog()) {
352 yyerror(loc, "error: Function body with multiple statements requires SystemVerilog.");
355 PBlock*tmp = new PBlock(PBlock::BL_SEQ);
357 tmp->set_statement(*s);
358 current_function->set_statement(tmp);
369 /* text items are C strings allocated by the lexor using
370 strdup. They can be put into lists with the texts type. */
372 list<perm_string>*perm_strings;
374 list<pform_port_t>*port_list;
376 vector<pform_tf_port_t>* tf_ports;
378 pform_name_t*pform_name;
380 ivl_discipline_t discipline;
384 list<string>*strings;
386 struct str_pair_t drive;
389 svector<PCase::Item*>*citems;
392 svector<lgate>*gates;
394 Module::port_t *mport;
395 LexicalScope::range_t* value_range;
396 vector<Module::port_t*>*mports;
398 named_number_t* named_number;
399 list<named_number_t>* named_numbers;
401 named_pexpr_t*named_pexpr;
402 list<named_pexpr_t>*named_pexprs;
403 struct parmvalue_t*parmvalue;
404 list<pform_range_t>*ranges;
409 svector<PEEvent*>*event_expr;
411 NetNet::Type nettype;
412 PGBuiltin::Type gatetype;
413 NetNet::PortType porttype;
414 ivl_variable_type_t vartype;
415 PBlock::BL_TYPE join_keyword;
418 vector<PWire*>*wires;
420 PEventStatement*event_statement;
422 vector<Statement*>*statement_list;
424 net_decl_assign_t*net_decl_assign;
425 enum_type_t*enum_type;
427 decl_assignment_t*decl_assignment;
428 list<decl_assignment_t*>*decl_assignments;
430 struct_member_t*struct_member;
431 list<struct_member_t*>*struct_members;
432 struct_type_t*struct_type;
434 data_type_t*data_type;
435 class_type_t*class_type;
436 real_type_t::type_t real_type;
437 property_qualifier_t property_qualifier;
448 } class_declaration_extends;
455 list<index_component_t> *dimensions;
457 LexicalScope::lifetime_t lifetime;
460 %token <text> IDENTIFIER SYSTEM_IDENTIFIER STRING TIME_LITERAL
461 %token <type_identifier> TYPE_IDENTIFIER
462 %token <package> PACKAGE_IDENTIFIER
463 %token <discipline> DISCIPLINE_IDENTIFIER
464 %token <text> PATHPULSE_IDENTIFIER
465 %token <number> BASED_NUMBER DEC_NUMBER UNBASED_NUMBER
466 %token <realtime> REALTIME
467 %token K_PLUS_EQ K_MINUS_EQ K_INCR K_DECR
468 %token K_LE K_GE K_EG K_EQ K_NE K_CEQ K_CNE K_WEQ K_WNE K_LP K_LS K_RS K_RSS K_SG
469 /* K_CONTRIBUTE is <+, the contribution assign. */
471 %token K_PO_POS K_PO_NEG K_POW
472 %token K_PSTAR K_STARP K_DOTSTAR
473 %token K_LOR K_LAND K_NAND K_NOR K_NXOR K_TRIGGER
475 %token K_edge_descriptor
477 /* The base tokens from 1364-1995. */
478 %token K_always K_and K_assign K_begin K_buf K_bufif0 K_bufif1 K_case
479 %token K_casex K_casez K_cmos K_deassign K_default K_defparam K_disable
480 %token K_edge K_else K_end K_endcase K_endfunction K_endmodule
481 %token K_endprimitive K_endspecify K_endtable K_endtask K_event K_for
482 %token K_force K_forever K_fork K_function K_highz0 K_highz1 K_if
483 %token K_ifnone K_initial K_inout K_input K_integer K_join K_large
484 %token K_macromodule K_medium K_module K_nand K_negedge K_nmos K_nor
485 %token K_not K_notif0 K_notif1 K_or K_output K_parameter K_pmos K_posedge
486 %token K_primitive K_pull0 K_pull1 K_pulldown K_pullup K_rcmos K_real
487 %token K_realtime K_reg K_release K_repeat K_rnmos K_rpmos K_rtran
488 %token K_rtranif0 K_rtranif1 K_scalared K_small K_specify K_specparam
489 %token K_strong0 K_strong1 K_supply0 K_supply1 K_table K_task K_time
490 %token K_tran K_tranif0 K_tranif1 K_tri K_tri0 K_tri1 K_triand K_trior
491 %token K_trireg K_vectored K_wait K_wand K_weak0 K_weak1 K_while K_wire
492 %token K_wor K_xnor K_xor
494 %token K_Shold K_Snochange K_Speriod K_Srecovery K_Ssetup K_Ssetuphold
495 %token K_Sskew K_Swidth
497 /* Icarus specific tokens. */
498 %token KK_attribute K_bool K_logic
500 /* The new tokens from 1364-2001. */
501 %token K_automatic K_endgenerate K_generate K_genvar K_localparam
502 %token K_noshowcancelled K_pulsestyle_onevent K_pulsestyle_ondetect
503 %token K_showcancelled K_signed K_unsigned
505 %token K_Sfullskew K_Srecrem K_Sremoval K_Stimeskew
507 /* The 1364-2001 configuration tokens. */
508 %token K_cell K_config K_design K_endconfig K_incdir K_include K_instance
509 %token K_liblist K_library K_use
511 /* The new tokens from 1364-2005. */
512 %token K_wone K_uwire
514 /* The new tokens from 1800-2005. */
515 %token K_alias K_always_comb K_always_ff K_always_latch K_assert
516 %token K_assume K_before K_bind K_bins K_binsof K_bit K_break K_byte
517 %token K_chandle K_class K_clocking K_const K_constraint K_context
518 %token K_continue K_cover K_covergroup K_coverpoint K_cross K_dist K_do
519 %token K_endclass K_endclocking K_endgroup K_endinterface K_endpackage
520 %token K_endprogram K_endproperty K_endsequence K_enum K_expect K_export
521 %token K_extends K_extern K_final K_first_match K_foreach K_forkjoin
522 %token K_iff K_ignore_bins K_illegal_bins K_import K_inside K_int
523 /* Icarus already has defined "logic" above! */
524 %token K_interface K_intersect K_join_any K_join_none K_local
525 %token K_longint K_matches K_modport K_new K_null K_package K_packed
526 %token K_priority K_program K_property K_protected K_pure K_rand K_randc
527 %token K_randcase K_randsequence K_ref K_return K_sequence K_shortint
528 %token K_shortreal K_solve K_static K_string K_struct K_super
529 %token K_tagged K_this K_throughout K_timeprecision K_timeunit K_type
530 %token K_typedef K_union K_unique K_var K_virtual K_void K_wait_order
531 %token K_wildcard K_with K_within
533 /* The new tokens from 1800-2009. */
534 %token K_accept_on K_checker K_endchecker K_eventually K_global K_implies
535 %token K_let K_nexttime K_reject_on K_restrict K_s_always K_s_eventually
536 %token K_s_nexttime K_s_until K_s_until_with K_strong K_sync_accept_on
537 %token K_sync_reject_on K_unique0 K_until K_until_with K_untyped K_weak
539 /* The new tokens from 1800-2012. */
540 %token K_implements K_interconnect K_nettype K_soft
542 /* The new tokens for Verilog-AMS 2.3. */
543 %token K_above K_abs K_absdelay K_abstol K_access K_acos K_acosh
544 /* 1800-2005 has defined "assert" above! */
545 %token K_ac_stim K_aliasparam K_analog K_analysis K_asin K_asinh
546 %token K_atan K_atan2 K_atanh K_branch K_ceil K_connect K_connectmodule
547 %token K_connectrules K_continuous K_cos K_cosh K_ddt K_ddt_nature K_ddx
548 %token K_discipline K_discrete K_domain K_driver_update K_endconnectrules
549 %token K_enddiscipline K_endnature K_endparamset K_exclude K_exp
550 %token K_final_step K_flicker_noise K_floor K_flow K_from K_ground
551 %token K_hypot K_idt K_idtmod K_idt_nature K_inf K_initial_step
552 %token K_laplace_nd K_laplace_np K_laplace_zd K_laplace_zp
553 %token K_last_crossing K_limexp K_ln K_log K_max K_merged K_min K_nature
554 %token K_net_resolution K_noise_table K_paramset K_potential K_pow
555 /* 1800-2005 has defined "string" above! */
556 %token K_resolveto K_sin K_sinh K_slew K_split K_sqrt K_tan K_tanh
557 %token K_timer K_transition K_units K_white_noise K_wreal
558 %token K_zi_nd K_zi_np K_zi_zd K_zi_zp
560 %type <flag> from_exclude block_item_decls_opt
561 %type <number> number pos_neg_number
562 %type <flag> signing unsigned_signed_opt signed_unsigned_opt
563 %type <flag> import_export
564 %type <flag> K_packed_opt K_reg_opt K_static_opt K_virtual_opt
565 %type <flag> udp_reg_opt edge_operator
566 %type <drive> drive_strength drive_strength_opt dr_strength0 dr_strength1
567 %type <letter> udp_input_sym udp_output_sym
568 %type <text> udp_input_list udp_sequ_entry udp_comb_entry
569 %type <perm_strings> udp_input_declaration_list
570 %type <strings> udp_entry_list udp_comb_entry_list udp_sequ_entry_list
571 %type <strings> udp_body
572 %type <perm_strings> udp_port_list
573 %type <wires> udp_port_decl udp_port_decls
574 %type <statement> udp_initial udp_init_opt
575 %type <expr> udp_initial_expr_opt
577 %type <text> register_variable net_variable event_variable endlabel_opt class_declaration_endlabel_opt
578 %type <perm_strings> register_variable_list net_variable_list event_variable_list
579 %type <perm_strings> list_of_identifiers loop_variables
580 %type <port_list> list_of_port_identifiers list_of_variable_port_identifiers
582 %type <net_decl_assign> net_decl_assign net_decl_assigns
584 %type <mport> port port_opt port_reference port_reference_list
585 %type <mport> port_declaration
586 %type <mports> list_of_ports module_port_list_opt list_of_port_declarations module_attribute_foreign
587 %type <value_range> parameter_value_range parameter_value_ranges
588 %type <value_range> parameter_value_ranges_opt
589 %type <expr> tf_port_item_expr_opt value_range_expression
591 %type <named_pexprs> enum_name_list enum_name
592 %type <enum_type> enum_data_type
594 %type <tf_ports> function_item function_item_list function_item_list_opt
595 %type <tf_ports> task_item task_item_list task_item_list_opt
596 %type <tf_ports> tf_port_declaration tf_port_item tf_port_item_list tf_port_list tf_port_list_opt
598 %type <named_pexpr> modport_simple_port port_name parameter_value_byname
599 %type <named_pexprs> port_name_list parameter_value_byname_list
601 %type <named_pexpr> attribute
602 %type <named_pexprs> attribute_list attribute_instance_list attribute_list_opt
604 %type <citem> case_item
605 %type <citems> case_items
607 %type <gate> gate_instance
608 %type <gates> gate_instance_list
610 %type <pform_name> hierarchy_identifier implicit_class_handle
611 %type <expr> assignment_pattern expression expr_mintypmax
612 %type <expr> expr_primary_or_typename expr_primary
613 %type <expr> class_new dynamic_array_new
614 %type <expr> inc_or_dec_expression inside_expression lpvalue
615 %type <expr> branch_probe_expression streaming_concatenation
616 %type <expr> delay_value delay_value_simple
617 %type <exprs> delay1 delay3 delay3_opt delay_value_list
618 %type <exprs> expression_list_with_nuls expression_list_proper
619 %type <exprs> cont_assign cont_assign_list
621 %type <decl_assignment> variable_decl_assignment
622 %type <decl_assignments> list_of_variable_decl_assignments
624 %type <data_type> data_type data_type_or_implicit data_type_or_implicit_or_void
625 %type <data_type> simple_type_or_string
626 %type <class_type> class_identifier
627 %type <struct_member> struct_union_member
628 %type <struct_members> struct_union_member_list
629 %type <struct_type> struct_data_type
631 %type <class_declaration_extends> class_declaration_extends_opt
633 %type <property_qualifier> class_item_qualifier property_qualifier
634 %type <property_qualifier> class_item_qualifier_list property_qualifier_list
635 %type <property_qualifier> class_item_qualifier_opt property_qualifier_opt
636 %type <property_qualifier> random_qualifier
638 %type <ranges> variable_dimension
639 %type <ranges> dimensions_opt dimensions
641 %type <nettype> net_type net_type_opt
642 %type <gatetype> gatetype switchtype
643 %type <porttype> port_direction port_direction_opt
644 %type <vartype> bit_logic bit_logic_opt
645 %type <vartype> integer_vector_type
646 %type <parmvalue> parameter_value_opt
648 %type <event_expr> event_expression_list
649 %type <event_expr> event_expression
650 %type <event_statement> event_control
651 %type <statement> statement statement_item statement_or_null
652 %type <statement> compressed_statement
653 %type <statement> loop_statement for_step jump_statement
654 %type <statement> procedural_assertion_statement
655 %type <statement_list> statement_or_null_list statement_or_null_list_opt
657 %type <statement> analog_statement
659 %type <join_keyword> join_keyword
661 %type <letter> spec_polarity
662 %type <perm_strings> specify_path_identifiers
664 %type <specpath> specify_simple_path specify_simple_path_decl
665 %type <specpath> specify_edge_path specify_edge_path_decl
667 %type <real_type> non_integer_type
668 %type <int_val> atom2_type
669 %type <int_val> module_start module_end
671 %type <lifetime> lifetime lifetime_opt
674 %right K_PLUS_EQ K_MINUS_EQ K_MUL_EQ K_DIV_EQ K_MOD_EQ K_AND_EQ K_OR_EQ
675 %right K_XOR_EQ K_LS_EQ K_RS_EQ K_RSS_EQ
676 %right '?' ':' K_inside
680 %left '^' K_NXOR K_NOR
682 %left K_EQ K_NE K_CEQ K_CNE K_WEQ K_WNE
683 %left K_GE K_LE '<' '>'
684 %left K_LS K_RS K_RSS
691 /* to resolve dangling else ambiguity. */
692 %nonassoc less_than_K_else
695 /* to resolve exclude (... ambiguity */
699 /* to resolve timeunits declaration/redeclaration ambiguity */
700 %nonassoc no_timeunits_declaration
701 %nonassoc one_timeunits_declaration
702 %nonassoc K_timeunit K_timeprecision
707 /* IEEE1800-2005: A.1.2 */
708 /* source_text ::= [ timeunits_declaration ] { description } */
710 : timeunits_declaration_opt
711 { pform_set_scope_timescale(yyloc); }
716 assertion_item /* IEEE1800-2012: A.6.10 */
717 : concurrent_assertion_item
720 assignment_pattern /* IEEE1800-2005: A.6.7.1 */
721 : K_LP expression_list_proper '}'
722 { PEAssignPattern*tmp = new PEAssignPattern(*$2);
728 { PEAssignPattern*tmp = new PEAssignPattern;
734 /* Some rules have a ... [ block_identifier ':' ] ... part. This
735 implements it in a LALR way. */
736 block_identifier_opt /* */
741 class_declaration /* IEEE1800-2005: A.1.2 */
742 : K_virtual_opt K_class lifetime_opt class_identifier class_declaration_extends_opt ';'
743 { pform_start_class_declaration(@2, $4, $5.type, $5.exprs, $3); }
744 class_items_opt K_endclass
745 { // Process a class.
746 pform_end_class_declaration(@9);
748 class_declaration_endlabel_opt
749 { // Wrap up the class.
750 if ($11 && $4 && $4->name != $11) {
751 yyerror(@11, "error: Class end label doesn't match class name.");
757 class_constraint /* IEEE1800-2005: A.1.8 */
758 : constraint_prototype
759 | constraint_declaration
764 { // Create a synthetic typedef for the class name so that the
765 // lexor detects the name as a type.
766 perm_string name = lex_strings.make($1);
767 class_type_t*tmp = new class_type_t(name);
769 pform_set_typedef(name, tmp, NULL);
774 { class_type_t*tmp = dynamic_cast<class_type_t*>($1.type);
776 yyerror(@1, "Type name \"%s\"is not a predeclared class name.", $1.text);
783 /* The endlabel after a class declaration is a little tricky because
784 the class name is detected by the lexor as a TYPE_IDENTIFIER if it
785 does indeed match a name. */
786 class_declaration_endlabel_opt
787 : ':' TYPE_IDENTIFIER
788 { class_type_t*tmp = dynamic_cast<class_type_t*> ($2.type);
790 yyerror(@2, "error: class declaration endlabel \"%s\" is not a class name\n", $2.text);
793 $$ = strdupnew(tmp->name.str());
803 /* This rule implements [ extends class_type ] in the
804 class_declaration. It is not a rule of its own in the LRM.
806 Note that for this to be correct, the identifier after the
807 extends keyword must be a class name. Therefore, match
808 TYPE_IDENTIFIER instead of IDENTIFIER, and this rule will return
811 class_declaration_extends_opt /* IEEE1800-2005: A.1.2 */
812 : K_extends TYPE_IDENTIFIER
817 | K_extends TYPE_IDENTIFIER '(' expression_list_with_nuls ')'
823 { $$.type = 0; $$.exprs = 0; }
826 /* The class_items_opt and class_items rules together implement the
827 rule snippet { class_item } (zero or more class_item) of the
828 class_declaration. */
829 class_items_opt /* IEEE1800-2005: A.1.2 */
834 class_items /* IEEE1800-2005: A.1.2 */
835 : class_items class_item
839 class_item /* IEEE1800-2005: A.1.8 */
841 /* IEEE1800 A.1.8: class_constructor_declaration */
842 : method_qualifier_opt K_function K_new
843 { assert(current_function==0);
844 current_function = pform_push_constructor_scope(@3);
846 '(' tf_port_list_opt ')' ';'
847 function_item_list_opt
848 statement_or_null_list_opt
849 K_endfunction endnew_opt
850 { current_function->set_ports($6);
851 pform_set_constructor_return(current_function);
852 pform_set_this_class(@3, current_function);
853 current_function_set_statement(@3, $10);
855 current_function = 0;
858 /* Class properties... */
860 | property_qualifier_opt data_type list_of_variable_decl_assignments ';'
861 { pform_class_property(@2, $1, $2, $3); }
863 | K_const class_item_qualifier_opt data_type list_of_variable_decl_assignments ';'
864 { pform_class_property(@1, $2 | property_qualifier_t::make_const(), $3, $4); }
866 /* Class methods... */
868 | method_qualifier_opt task_declaration
869 { /* The task_declaration rule puts this into the class */ }
871 | method_qualifier_opt function_declaration
872 { /* The function_declaration rule puts this into the class */ }
874 /* External class method definitions... */
876 | K_extern method_qualifier_opt K_function K_new ';'
877 { yyerror(@1, "sorry: External constructors are not yet supported."); }
878 | K_extern method_qualifier_opt K_function K_new '(' tf_port_list_opt ')' ';'
879 { yyerror(@1, "sorry: External constructors are not yet supported."); }
880 | K_extern method_qualifier_opt K_function data_type_or_implicit_or_void
882 { yyerror(@1, "sorry: External methods are not yet supported.");
885 | K_extern method_qualifier_opt K_function data_type_or_implicit_or_void
886 IDENTIFIER '(' tf_port_list_opt ')' ';'
887 { yyerror(@1, "sorry: External methods are not yet supported.");
890 | K_extern method_qualifier_opt K_task IDENTIFIER ';'
891 { yyerror(@1, "sorry: External methods are not yet supported.");
894 | K_extern method_qualifier_opt K_task IDENTIFIER '(' tf_port_list_opt ')' ';'
895 { yyerror(@1, "sorry: External methods are not yet supported.");
899 /* Class constraints... */
903 /* Here are some error matching rules to help recover from various
904 syntax errors within a class declaration. */
906 | property_qualifier_opt data_type error ';'
907 { yyerror(@3, "error: Errors in variable names after data type.");
911 | property_qualifier_opt IDENTIFIER error ';'
912 { yyerror(@3, "error: %s doesn't name a type.", $2);
916 | method_qualifier_opt K_function K_new error K_endfunction endnew_opt
917 { yyerror(@1, "error: I give up on this class constructor declaration.");
922 { yyerror(@2, "error: invalid class item.");
928 class_item_qualifier /* IEEE1800-2005 A.1.8 */
929 : K_static { $$ = property_qualifier_t::make_static(); }
930 | K_protected { $$ = property_qualifier_t::make_protected(); }
931 | K_local { $$ = property_qualifier_t::make_local(); }
934 class_item_qualifier_list
935 : class_item_qualifier_list class_item_qualifier { $$ = $1 | $2; }
936 | class_item_qualifier { $$ = $1; }
939 class_item_qualifier_opt
940 : class_item_qualifier_list { $$ = $1; }
941 | { $$ = property_qualifier_t::make_none(); }
944 class_new /* IEEE1800-2005 A.2.4 */
945 : K_new '(' expression_list_with_nuls ')'
946 { list<PExpr*>*expr_list = $3;
947 strip_tail_items(expr_list);
948 PENewClass*tmp = new PENewClass(*expr_list);
953 | K_new hierarchy_identifier
954 { PEIdent*tmpi = new PEIdent(*$2);
956 PENewCopy*tmp = new PENewCopy(tmpi);
962 { PENewClass*tmp = new PENewClass;
968 /* The concurrent_assertion_item pulls together the
969 concurrent_assertion_statement and checker_instantiation rules. */
971 concurrent_assertion_item /* IEEE1800-2012 A.2.10 */
972 : block_identifier_opt K_assert K_property '(' property_spec ')' statement_or_null
974 if (gn_assertions_flag) {
975 yyerror(@2, "sorry: concurrent_assertion_item not supported."
976 " Try -gno-assertion to turn this message off.");
979 | block_identifier_opt K_assert K_property '(' error ')' statement_or_null
981 yyerror(@2, "error: Error in property_spec of concurrent assertion item.");
985 constraint_block_item /* IEEE1800-2005 A.1.9 */
986 : constraint_expression
989 constraint_block_item_list
990 : constraint_block_item_list constraint_block_item
991 | constraint_block_item
994 constraint_block_item_list_opt
996 | constraint_block_item_list
999 constraint_declaration /* IEEE1800-2005: A.1.9 */
1000 : K_static_opt K_constraint IDENTIFIER '{' constraint_block_item_list_opt '}'
1001 { yyerror(@2, "sorry: Constraint declarations not supported."); }
1003 /* Error handling rules... */
1005 | K_static_opt K_constraint IDENTIFIER '{' error '}'
1006 { yyerror(@4, "error: Errors in the constraint block item list."); }
1009 constraint_expression /* IEEE1800-2005 A.1.9 */
1011 | expression K_dist '{' '}' ';'
1012 | expression K_TRIGGER constraint_set
1013 | K_if '(' expression ')' constraint_set %prec less_than_K_else
1014 | K_if '(' expression ')' constraint_set K_else constraint_set
1015 | K_foreach '(' IDENTIFIER '[' loop_variables ']' ')' constraint_set
1018 constraint_expression_list /* */
1019 : constraint_expression_list constraint_expression
1020 | constraint_expression
1023 constraint_prototype /* IEEE1800-2005: A.1.9 */
1024 : K_static_opt K_constraint IDENTIFIER ';'
1025 { yyerror(@2, "sorry: Constraint prototypes not supported."); }
1028 constraint_set /* IEEE1800-2005 A.1.9 */
1029 : constraint_expression
1030 | '{' constraint_expression_list '}'
1033 data_declaration /* IEEE1800-2005: A.2.1.3 */
1034 : attribute_list_opt data_type_or_implicit list_of_variable_decl_assignments ';'
1035 { data_type_t*data_type = $2;
1036 if (data_type == 0) {
1037 data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
1038 FILE_NAME(data_type, @2);
1040 pform_makewire(@2, 0, str_strength, $3, NetNet::IMPLICIT_REG, data_type);
1044 data_type /* IEEE1800-2005: A.2.2.1 */
1045 : integer_vector_type unsigned_signed_opt dimensions_opt
1046 { ivl_variable_type_t use_vtype = $1;
1047 bool reg_flag = false;
1048 if (use_vtype == IVL_VT_NO_TYPE) {
1049 use_vtype = IVL_VT_LOGIC;
1052 vector_type_t*tmp = new vector_type_t(use_vtype, $2, $3);
1053 tmp->reg_flag = reg_flag;
1058 { real_type_t*tmp = new real_type_t($1);
1063 { if (!$1->packed_flag) {
1064 yyerror(@1, "sorry: Unpacked structs not supported.");
1070 | atom2_type signed_unsigned_opt
1071 { atom2_type_t*tmp = new atom2_type_t($1, $2);
1075 | K_integer signed_unsigned_opt
1076 { list<pform_range_t>*pd = make_range_from_width(integer_width);
1077 vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, $2, pd);
1078 tmp->reg_flag = true;
1079 tmp->integer_flag = true;
1083 { list<pform_range_t>*pd = make_range_from_width(64);
1084 vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, pd);
1085 tmp->reg_flag = !gn_system_verilog();
1088 | TYPE_IDENTIFIER dimensions_opt
1090 parray_type_t*tmp = new parray_type_t($1.type, $2);
1093 } else $$ = $1.type;
1096 | PACKAGE_IDENTIFIER K_SCOPE_RES
1097 { lex_in_package_scope($1); }
1099 { lex_in_package_scope(0);
1104 { string_type_t*tmp = new string_type_t;
1110 /* The data_type_or_implicit rule is a little more complex then the
1111 rule documented in the IEEE format syntax in order to allow for
1112 signaling the special case that the data_type is completely
1113 absent. The context may need that information to decide to resort
1116 data_type_or_implicit /* IEEE1800-2005: A.2.2.1 */
1119 | signing dimensions_opt
1120 { vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, $1, $2);
1121 tmp->implicit_flag = true;
1126 { vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, $1);
1127 tmp->implicit_flag = true;
1136 data_type_or_implicit_or_void
1137 : data_type_or_implicit
1140 { void_type_t*tmp = new void_type_t;
1146 /* NOTE: The "module" rule of the description combines the
1147 module_declaration, program_declaration, and interface_declaration
1148 rules from the standard description. */
1150 description /* IEEE1800-2005: A.1.2 */
1153 | config_declaration
1154 | nature_declaration
1155 | package_declaration
1156 | discipline_declaration
1158 | KK_attribute '(' IDENTIFIER ',' STRING ',' STRING ')'
1159 { perm_string tmp3 = lex_strings.make($3);
1160 pform_set_type_attrib(tmp3, $5, $7);
1168 | description_list description
1172 /* This implements the [ : IDENTIFIER ] part of the constructor
1173 rule documented in IEEE1800-2005: A.1.8 */
1174 endnew_opt : ':' K_new | ;
1176 /* The dynamic_array_new rule is kinda like an expression, but it is
1177 treated differently by rules that use this "expression". Watch out! */
1179 dynamic_array_new /* IEEE1800-2005: A.2.4 */
1180 : K_new '[' expression ']'
1181 { $$ = new PENewArray($3, 0);
1184 | K_new '[' expression ']' '(' expression ')'
1185 { $$ = new PENewArray($3, $6);
1190 for_step /* IEEE1800-2005: A.6.8 */
1191 : lpvalue '=' expression
1192 { PAssign*tmp = new PAssign($1,$3);
1196 | inc_or_dec_expression
1197 { $$ = pform_compressed_assign_from_inc_dec(@1, $1); }
1198 | compressed_statement
1203 /* The function declaration rule matches the function declaration
1204 header, then pushes the function scope. This causes the
1205 definitions in the func_body to take on the scope of the function
1206 instead of the module. */
1207 function_declaration /* IEEE1800-2005: A.2.6 */
1208 : K_function lifetime_opt data_type_or_implicit_or_void IDENTIFIER ';'
1209 { assert(current_function == 0);
1210 current_function = pform_push_function_scope(@1, $4, $2);
1212 function_item_list statement_or_null_list_opt
1214 { current_function->set_ports($7);
1215 current_function->set_return($3);
1216 current_function_set_statement($8? @8 : @4, $8);
1217 pform_set_this_class(@4, current_function);
1219 current_function = 0;
1222 { // Last step: check any closing name.
1224 if (strcmp($4,$11) != 0) {
1225 yyerror(@11, "error: End label doesn't match "
1228 if (! gn_system_verilog()) {
1229 yyerror(@11, "error: Function end labels require "
1237 | K_function lifetime_opt data_type_or_implicit_or_void IDENTIFIER
1238 { assert(current_function == 0);
1239 current_function = pform_push_function_scope(@1, $4, $2);
1241 '(' tf_port_list_opt ')' ';'
1242 block_item_decls_opt
1243 statement_or_null_list_opt
1245 { current_function->set_ports($7);
1246 current_function->set_return($3);
1247 current_function_set_statement($11? @11 : @4, $11);
1248 pform_set_this_class(@4, current_function);
1250 current_function = 0;
1251 if ($7==0 && !gn_system_verilog()) {
1252 yyerror(@4, "error: Empty parenthesis syntax requires SystemVerilog.");
1256 { // Last step: check any closing name.
1258 if (strcmp($4,$14) != 0) {
1259 yyerror(@14, "error: End label doesn't match "
1262 if (! gn_system_verilog()) {
1263 yyerror(@14, "error: Function end labels require "
1271 /* Detect and recover from some errors. */
1273 | K_function lifetime_opt data_type_or_implicit_or_void IDENTIFIER error K_endfunction
1275 if (current_function) {
1277 current_function = 0;
1279 assert(current_function == 0);
1280 yyerror(@1, "error: Syntax error defining function.");
1284 { // Last step: check any closing name.
1286 if (strcmp($4,$8) != 0) {
1287 yyerror(@8, "error: End label doesn't match function name");
1289 if (! gn_system_verilog()) {
1290 yyerror(@8, "error: Function end labels require "
1300 import_export /* IEEE1800-2012: A.2.9 */
1301 : K_import { $$ = true; }
1302 | K_export { $$ = false; }
1305 implicit_class_handle /* IEEE1800-2005: A.8.4 */
1306 : K_this { $$ = pform_create_this(); }
1307 | K_super { $$ = pform_create_super(); }
1310 /* SystemVerilog adds support for the increment/decrement
1311 expressions, which look like a++, --a, etc. These are primaries
1312 but are in their own rules because they can also be
1313 statements. Note that the operator can only take l-value
1316 inc_or_dec_expression /* IEEE1800-2005: A.4.3 */
1317 : K_INCR lpvalue %prec UNARY_PREC
1318 { PEUnary*tmp = new PEUnary('I', $2);
1322 | lpvalue K_INCR %prec UNARY_PREC
1323 { PEUnary*tmp = new PEUnary('i', $1);
1327 | K_DECR lpvalue %prec UNARY_PREC
1328 { PEUnary*tmp = new PEUnary('D', $2);
1332 | lpvalue K_DECR %prec UNARY_PREC
1333 { PEUnary*tmp = new PEUnary('d', $1);
1339 inside_expression /* IEEE1800-2005 A.8.3 */
1340 : expression K_inside '{' open_range_list '}'
1341 { yyerror(@2, "sorry: \"inside\" expressions not supported yet.");
1346 integer_vector_type /* IEEE1800-2005: A.2.2.1 */
1347 : K_reg { $$ = IVL_VT_NO_TYPE; } /* Usually a synonym for logic. */
1348 | K_bit { $$ = IVL_VT_BOOL; }
1349 | K_logic { $$ = IVL_VT_LOGIC; }
1350 | K_bool { $$ = IVL_VT_BOOL; } /* Icarus Verilog xtypes extension */
1353 join_keyword /* IEEE1800-2005: A.6.3 */
1355 { $$ = PBlock::BL_PAR; }
1357 { $$ = PBlock::BL_JOIN_NONE; }
1359 { $$ = PBlock::BL_JOIN_ANY; }
1362 jump_statement /* IEEE1800-2005: A.6.5 */
1364 { yyerror(@1, "sorry: break statements not supported.");
1368 { PReturn*tmp = new PReturn(0);
1372 | K_return expression ';'
1373 { PReturn*tmp = new PReturn($2);
1379 lifetime /* IEEE1800-2005: A.2.1.3 */
1380 : K_automatic { $$ = LexicalScope::AUTOMATIC; }
1381 | K_static { $$ = LexicalScope::STATIC; }
1384 lifetime_opt /* IEEE1800-2005: A.2.1.3 */
1385 : lifetime { $$ = $1; }
1386 | { $$ = LexicalScope::INHERITED; }
1389 /* Loop statements are kinds of statements. */
1391 loop_statement /* IEEE1800-2005: A.6.8 */
1392 : K_for '(' lpvalue '=' expression ';' expression ';' for_step ')'
1394 { PForStatement*tmp = new PForStatement($3, $5, $7, $9, $11);
1399 // Handle for_variable_declaration syntax by wrapping the for(...)
1400 // statement in a synthetic named block. We can name the block
1401 // after the variable that we are creating, that identifier is
1402 // safe in the controlling scope.
1403 | K_for '(' data_type IDENTIFIER '=' expression ';' expression ';' for_step ')'
1404 { static unsigned for_counter = 0;
1405 char for_block_name [64];
1406 snprintf(for_block_name, sizeof for_block_name, "$ivl_for_loop%u", for_counter);
1408 PBlock*tmp = pform_push_block_scope(for_block_name, PBlock::BL_SEQ);
1410 current_block_stack.push(tmp);
1412 list<decl_assignment_t*>assign_list;
1413 decl_assignment_t*tmp_assign = new decl_assignment_t;
1414 tmp_assign->name = lex_strings.make($4);
1415 assign_list.push_back(tmp_assign);
1416 pform_makewire(@4, 0, str_strength, &assign_list, NetNet::REG, $3);
1419 { pform_name_t tmp_hident;
1420 tmp_hident.push_back(name_component_t(lex_strings.make($4)));
1422 PEIdent*tmp_ident = pform_new_ident(tmp_hident);
1423 FILE_NAME(tmp_ident, @4);
1425 PForStatement*tmp_for = new PForStatement(tmp_ident, $6, $8, $10, $13);
1426 FILE_NAME(tmp_for, @1);
1429 vector<Statement*>tmp_for_list (1);
1430 tmp_for_list[0] = tmp_for;
1431 PBlock*tmp_blk = current_block_stack.top();
1432 current_block_stack.pop();
1433 tmp_blk->set_statement(tmp_for_list);
1438 | K_forever statement_or_null
1439 { PForever*tmp = new PForever($2);
1444 | K_repeat '(' expression ')' statement_or_null
1445 { PRepeat*tmp = new PRepeat($3, $5);
1450 | K_while '(' expression ')' statement_or_null
1451 { PWhile*tmp = new PWhile($3, $5);
1456 | K_do statement_or_null K_while '(' expression ')' ';'
1457 { PDoWhile*tmp = new PDoWhile($5, $2);
1462 // When matching a foreach loop, implicitly create a named block
1463 // to hold the definitions for the index variables.
1464 | K_foreach '(' IDENTIFIER '[' loop_variables ']' ')'
1465 { static unsigned foreach_counter = 0;
1466 char for_block_name[64];
1467 snprintf(for_block_name, sizeof for_block_name, "$ivl_foreach%u", foreach_counter);
1468 foreach_counter += 1;
1470 PBlock*tmp = pform_push_block_scope(for_block_name, PBlock::BL_SEQ);
1472 current_block_stack.push(tmp);
1474 pform_make_foreach_declarations(@1, $5);
1477 { PForeach*tmp_for = pform_make_foreach(@1, $3, $5, $9);
1480 vector<Statement*>tmp_for_list(1);
1481 tmp_for_list[0] = tmp_for;
1482 PBlock*tmp_blk = current_block_stack.top();
1483 current_block_stack.pop();
1484 tmp_blk->set_statement(tmp_for_list);
1488 /* Error forms for loop statements. */
1490 | K_for '(' lpvalue '=' expression ';' expression ';' error ')'
1493 yyerror(@1, "error: Error in for loop step assignment.");
1496 | K_for '(' lpvalue '=' expression ';' error ';' for_step ')'
1499 yyerror(@1, "error: Error in for loop condition expression.");
1502 | K_for '(' error ')' statement_or_null
1504 yyerror(@1, "error: Incomprehensible for loop.");
1507 | K_while '(' error ')' statement_or_null
1509 yyerror(@1, "error: Error in while loop condition.");
1512 | K_do statement_or_null K_while '(' error ')' ';'
1514 yyerror(@1, "error: Error in do/while loop condition.");
1517 | K_foreach '(' IDENTIFIER '[' error ']' ')' statement_or_null
1519 yyerror(@4, "error: Errors in foreach loop variables list.");
1524 /* TODO: Replace register_variable_list with list_of_variable_decl_assignments. */
1525 list_of_variable_decl_assignments /* IEEE1800-2005 A.2.3 */
1526 : variable_decl_assignment
1527 { list<decl_assignment_t*>*tmp = new list<decl_assignment_t*>;
1531 | list_of_variable_decl_assignments ',' variable_decl_assignment
1532 { list<decl_assignment_t*>*tmp = $1;
1538 variable_decl_assignment /* IEEE1800-2005 A.2.3 */
1539 : IDENTIFIER dimensions_opt
1540 { decl_assignment_t*tmp = new decl_assignment_t;
1541 tmp->name = lex_strings.make($1);
1549 | IDENTIFIER '=' expression
1550 { decl_assignment_t*tmp = new decl_assignment_t;
1551 tmp->name = lex_strings.make($1);
1552 tmp->expr .reset($3);
1556 | IDENTIFIER '=' K_new '(' ')'
1557 { decl_assignment_t*tmp = new decl_assignment_t;
1558 tmp->name = lex_strings.make($1);
1559 PENewClass*expr = new PENewClass;
1560 FILE_NAME(expr, @3);
1561 tmp->expr .reset(expr);
1568 loop_variables /* IEEE1800-2005: A.6.8 */
1569 : loop_variables ',' IDENTIFIER
1570 { list<perm_string>*tmp = $1;
1571 tmp->push_back(lex_strings.make($3));
1576 { list<perm_string>*tmp = new list<perm_string>;
1577 tmp->push_back(lex_strings.make($1));
1583 method_qualifier /* IEEE1800-2005: A.1.8 */
1585 | class_item_qualifier
1588 method_qualifier_opt
1593 modport_declaration /* IEEE1800-2012: A.2.9 */
1595 { if (!pform_in_interface())
1596 yyerror(@1, "error: modport declarations are only allowed "
1599 modport_item_list ';'
1604 | modport_item_list ',' modport_item
1609 { pform_start_modport_item(@1, $1); }
1610 '(' modport_ports_list ')'
1611 { pform_end_modport_item(@1); }
1614 /* The modport_ports_list is a LALR(2) grammar. When the parser sees a
1615 ',' it needs to look ahead to the next token to decide whether it is
1616 a continuation of the preceding modport_ports_declaration, or the
1617 start of a new modport_ports_declaration. bison only supports LALR(1),
1618 so we have to handcraft a mini parser for this part of the syntax.
1619 last_modport_port holds the state for this mini parser.*/
1622 : modport_ports_declaration
1623 | modport_ports_list ',' modport_ports_declaration
1624 | modport_ports_list ',' modport_simple_port
1625 { if (last_modport_port.type == MP_SIMPLE) {
1626 pform_add_modport_port(@3, last_modport_port.direction,
1627 $3->name, $3->parm);
1629 yyerror(@3, "error: modport expression not allowed here.");
1633 | modport_ports_list ',' modport_tf_port
1634 { if (last_modport_port.type != MP_TF)
1635 yyerror(@3, "error: task/function declaration not allowed here.");
1637 | modport_ports_list ',' IDENTIFIER
1638 { if (last_modport_port.type == MP_SIMPLE) {
1639 pform_add_modport_port(@3, last_modport_port.direction,
1640 lex_strings.make($3), 0);
1641 } else if (last_modport_port.type != MP_TF) {
1642 yyerror(@3, "error: list of identifiers not allowed here.");
1646 | modport_ports_list ','
1647 { yyerror(@2, "error: NULL port declarations are not allowed"); }
1650 modport_ports_declaration
1651 : attribute_list_opt port_direction IDENTIFIER
1652 { last_modport_port.type = MP_SIMPLE;
1653 last_modport_port.direction = $2;
1654 pform_add_modport_port(@3, $2, lex_strings.make($3), 0);
1658 | attribute_list_opt port_direction modport_simple_port
1659 { last_modport_port.type = MP_SIMPLE;
1660 last_modport_port.direction = $2;
1661 pform_add_modport_port(@3, $2, $3->name, $3->parm);
1665 | attribute_list_opt import_export IDENTIFIER
1666 { last_modport_port.type = MP_TF;
1667 last_modport_port.is_import = $2;
1668 yyerror(@3, "sorry: modport task/function ports are not yet supported.");
1672 | attribute_list_opt import_export modport_tf_port
1673 { last_modport_port.type = MP_TF;
1674 last_modport_port.is_import = $2;
1675 yyerror(@3, "sorry: modport task/function ports are not yet supported.");
1678 | attribute_list_opt K_clocking IDENTIFIER
1679 { last_modport_port.type = MP_CLOCKING;
1680 last_modport_port.direction = NetNet::NOT_A_PORT;
1681 yyerror(@3, "sorry: modport clocking declaration is not yet supported.");
1688 : '.' IDENTIFIER '(' expression ')'
1689 { named_pexpr_t*tmp = new named_pexpr_t;
1690 tmp->name = lex_strings.make($2);
1699 | K_task IDENTIFIER '(' tf_port_list_opt ')'
1700 | K_function data_type_or_implicit_or_void IDENTIFIER
1701 | K_function data_type_or_implicit_or_void IDENTIFIER '(' tf_port_list_opt ')'
1704 non_integer_type /* IEEE1800-2005: A.2.2.1 */
1705 : K_real { $$ = real_type_t::REAL; }
1706 | K_realtime { $$ = real_type_t::REAL; }
1707 | K_shortreal { $$ = real_type_t::SHORTREAL; }
1710 number : BASED_NUMBER
1711 { $$ = $1; based_size = 0;}
1713 { $$ = $1; based_size = 0;}
1714 | DEC_NUMBER BASED_NUMBER
1715 { $$ = pform_verinum_with_size($1,$2, @2.text, @2.first_line);
1718 { $$ = $1; based_size = 0;}
1719 | DEC_NUMBER UNBASED_NUMBER
1720 { yyerror(@1, "error: Unbased SystemVerilog literal cannot have "
1722 $$ = $1; based_size = 0;}
1725 open_range_list /* IEEE1800-2005 A.2.11 */
1726 : open_range_list ',' value_range
1730 package_declaration /* IEEE1800-2005 A.1.2 */
1731 : K_package lifetime_opt IDENTIFIER ';'
1732 { pform_start_package_declaration(@1, $3, $2); }
1733 timeunits_declaration_opt
1734 { pform_set_scope_timescale(@1); }
1735 package_item_list_opt
1736 K_endpackage endlabel_opt
1737 { pform_end_package_declaration(@1);
1738 // If an end label is present make sure it match the package name.
1740 if (strcmp($3,$10) != 0) {
1741 yyerror(@10, "error: End label doesn't match package name");
1749 module_package_import_list_opt
1751 | package_import_list
1755 : package_import_declaration
1756 | package_import_list package_import_declaration
1759 package_import_declaration /* IEEE1800-2005 A.2.1.3 */
1760 : K_import package_import_item_list ';'
1765 : PACKAGE_IDENTIFIER K_SCOPE_RES IDENTIFIER
1766 { pform_package_import(@2, $1, $3);
1769 | PACKAGE_IDENTIFIER K_SCOPE_RES '*'
1770 { pform_package_import(@2, $1, 0);
1774 package_import_item_list
1775 : package_import_item_list',' package_import_item
1776 | package_import_item
1779 package_item /* IEEE1800-2005 A.1.10 */
1780 : timeunits_declaration
1781 | K_parameter param_type parameter_assign_list ';'
1782 | K_localparam param_type localparam_assign_list ';'
1784 | function_declaration
1791 : package_item_list package_item
1795 package_item_list_opt : package_item_list | ;
1797 port_direction /* IEEE1800-2005 A.1.3 */
1798 : K_input { $$ = NetNet::PINPUT; }
1799 | K_output { $$ = NetNet::POUTPUT; }
1800 | K_inout { $$ = NetNet::PINOUT; }
1802 { $$ = NetNet::PREF;
1803 if (!gn_system_verilog()) {
1804 yyerror(@1, "error: Reference ports (ref) require SystemVerilog.");
1805 $$ = NetNet::PINPUT;
1810 /* port_direction_opt is used in places where the port direction is
1811 optional. The default direction is selected by the context,
1812 which needs to notice the PIMPLICIT direction. */
1815 : port_direction { $$ = $1; }
1816 | { $$ = NetNet::PIMPLICIT; }
1819 property_expr /* IEEE1800-2012 A.2.10 */
1823 procedural_assertion_statement /* IEEE1800-2012 A.6.10 */
1824 : K_assert '(' expression ')' statement %prec less_than_K_else
1825 { yyerror(@1, "sorry: Simple immediate assertion statements not implemented.");
1828 | K_assert '(' expression ')' K_else statement
1829 { yyerror(@1, "sorry: Simple immediate assertion statements not implemented.");
1832 | K_assert '(' expression ')' statement K_else statement
1833 { yyerror(@1, "sorry: Simple immediate assertion statements not implemented.");
1838 /* The property_qualifier rule is as literally described in the LRM,
1839 but the use is usually as { property_qualifier }, which is
1840 implemented by the property_qualifier_opt rule below. */
1842 property_qualifier /* IEEE1800-2005 A.1.8 */
1843 : class_item_qualifier
1847 property_qualifier_opt /* IEEE1800-2005 A.1.8: ... { property_qualifier } */
1848 : property_qualifier_list { $$ = $1; }
1849 | { $$ = property_qualifier_t::make_none(); }
1852 property_qualifier_list /* IEEE1800-2005 A.1.8 */
1853 : property_qualifier_list property_qualifier { $$ = $1 | $2; }
1854 | property_qualifier { $$ = $1; }
1857 /* The property_spec rule uses some helper rules to implement this
1859 [ clocking_event ] [ disable iff ( expression_or_dist ) ] property_expr
1860 This does it is a YACC friendly way. */
1862 property_spec /* IEEE1800-2012 A.2.10 */
1863 : clocking_event_opt property_spec_disable_iff_opt property_expr
1866 property_spec_disable_iff_opt /* */
1867 : K_disable K_iff '(' expression ')'
1871 random_qualifier /* IEEE1800-2005 A.1.8 */
1872 : K_rand { $$ = property_qualifier_t::make_rand(); }
1873 | K_randc { $$ = property_qualifier_t::make_randc(); }
1876 /* real and realtime are exactly the same so save some code
1877 * with a common matching rule. */
1883 signing /* IEEE1800-2005: A.2.2.1 */
1884 : K_signed { $$ = true; }
1885 | K_unsigned { $$ = false; }
1888 simple_type_or_string /* IEEE1800-2005: A.2.2.1 */
1889 : integer_vector_type
1890 { ivl_variable_type_t use_vtype = $1;
1891 bool reg_flag = false;
1892 if (use_vtype == IVL_VT_NO_TYPE) {
1893 use_vtype = IVL_VT_LOGIC;
1896 vector_type_t*tmp = new vector_type_t(use_vtype, false, 0);
1897 tmp->reg_flag = reg_flag;
1902 { real_type_t*tmp = new real_type_t($1);
1907 { atom2_type_t*tmp = new atom2_type_t($1, true);
1912 { list<pform_range_t>*pd = make_range_from_width(integer_width);
1913 vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, true, pd);
1914 tmp->reg_flag = true;
1915 tmp->integer_flag = true;
1919 { list<pform_range_t>*pd = make_range_from_width(64);
1920 vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, pd);
1921 tmp->reg_flag = !gn_system_verilog();
1928 | PACKAGE_IDENTIFIER K_SCOPE_RES
1929 { lex_in_package_scope($1); }
1931 { lex_in_package_scope(0);
1936 { string_type_t*tmp = new string_type_t;
1942 statement /* IEEE1800-2005: A.6.4 */
1943 : attribute_list_opt statement_item
1944 { pform_bind_attributes($2->attributes, $1);
1949 /* Many places where statements are allowed can actually take a
1950 statement or a null statement marked with a naked semi-colon. */
1952 statement_or_null /* IEEE1800-2005: A.6.4 */
1955 | attribute_list_opt ';'
1963 stream_expression_list
1964 : stream_expression_list ',' stream_expression
1973 streaming_concatenation /* IEEE1800-2005: A.8.1 */
1974 : '{' stream_operator '{' stream_expression_list '}' '}'
1975 { /* streaming concatenation is a SystemVerilog thing. */
1976 if (gn_system_verilog()) {
1977 yyerror(@2, "sorry: Streaming concatenation not supported.");
1980 yyerror(@2, "error: Streaming concatenation requires SystemVerilog");
1986 /* The task declaration rule matches the task declaration
1987 header, then pushes the function scope. This causes the
1988 definitions in the task_body to take on the scope of the task
1989 instead of the module. */
1991 task_declaration /* IEEE1800-2005: A.2.7 */
1993 : K_task lifetime_opt IDENTIFIER ';'
1994 { assert(current_task == 0);
1995 current_task = pform_push_task_scope(@1, $3, $2);
1998 statement_or_null_list_opt
2000 { current_task->set_ports($6);
2001 current_task_set_statement(@3, $7);
2002 pform_set_this_class(@3, current_task);
2005 if ($7 && $7->size() > 1 && !gn_system_verilog()) {
2006 yyerror(@7, "error: Task body with multiple statements requires SystemVerilog.");
2011 { // Last step: check any closing name. This is done late so
2012 // that the parser can look ahead to detect the present
2013 // endlabel_opt but still have the pform_endmodule() called
2014 // early enough that the lexor can know we are outside the
2017 if (strcmp($3,$10) != 0) {
2018 yyerror(@10, "error: End label doesn't match task name");
2020 if (! gn_system_verilog()) {
2021 yyerror(@10, "error: Task end labels require "
2029 | K_task lifetime_opt IDENTIFIER '('
2030 { assert(current_task == 0);
2031 current_task = pform_push_task_scope(@1, $3, $2);
2033 tf_port_list ')' ';'
2034 block_item_decls_opt
2035 statement_or_null_list_opt
2037 { current_task->set_ports($6);
2038 current_task_set_statement(@3, $10);
2039 pform_set_this_class(@3, current_task);
2042 if ($10) delete $10;
2045 { // Last step: check any closing name. This is done late so
2046 // that the parser can look ahead to detect the present
2047 // endlabel_opt but still have the pform_endmodule() called
2048 // early enough that the lexor can know we are outside the
2051 if (strcmp($3,$13) != 0) {
2052 yyerror(@13, "error: End label doesn't match task name");
2054 if (! gn_system_verilog()) {
2055 yyerror(@13, "error: Task end labels require "
2063 | K_task lifetime_opt IDENTIFIER '(' ')' ';'
2064 { assert(current_task == 0);
2065 current_task = pform_push_task_scope(@1, $3, $2);
2067 block_item_decls_opt
2068 statement_or_null_list
2070 { current_task->set_ports(0);
2071 current_task_set_statement(@3, $9);
2072 pform_set_this_class(@3, current_task);
2073 if (! current_task->method_of()) {
2074 cerr << @3 << ": warning: task definition for \"" << $3
2075 << "\" has an empty port declaration list!" << endl;
2079 if ($9->size() > 1 && !gn_system_verilog()) {
2080 yyerror(@9, "error: Task body with multiple statements requires SystemVerilog.");
2085 { // Last step: check any closing name. This is done late so
2086 // that the parser can look ahead to detect the present
2087 // endlabel_opt but still have the pform_endmodule() called
2088 // early enough that the lexor can know we are outside the
2091 if (strcmp($3,$12) != 0) {
2092 yyerror(@12, "error: End label doesn't match task name");
2094 if (! gn_system_verilog()) {
2095 yyerror(@12, "error: Task end labels require "
2103 | K_task lifetime_opt IDENTIFIER error K_endtask
2111 { // Last step: check any closing name. This is done late so
2112 // that the parser can look ahead to detect the present
2113 // endlabel_opt but still have the pform_endmodule() called
2114 // early enough that the lexor can know we are outside the
2117 if (strcmp($3,$7) != 0) {
2118 yyerror(@7, "error: End label doesn't match task name");
2120 if (! gn_system_verilog()) {
2121 yyerror(@7, "error: Task end labels require "
2132 tf_port_declaration /* IEEE1800-2005: A.2.7 */
2133 : port_direction K_reg_opt unsigned_signed_opt dimensions_opt list_of_identifiers ';'
2134 { vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1,
2141 /* When the port is an integer, infer a signed vector of the integer
2142 shape. Generate a range ([31:0]) to make it work. */
2144 | port_direction K_integer list_of_identifiers ';'
2145 { list<pform_range_t>*range_stub = make_range_from_width(integer_width);
2146 vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, true,
2147 range_stub, $3, true);
2151 /* Ports can be time with a width of [63:0] (unsigned). */
2153 | port_direction K_time list_of_identifiers ';'
2154 { list<pform_range_t>*range_stub = make_range_from_width(64);
2155 vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, false,
2160 /* Ports can be real or realtime. */
2162 | port_direction real_or_realtime list_of_identifiers ';'
2163 { vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_REAL, true,
2169 /* Ports can be string. */
2171 | port_direction K_string list_of_identifiers ';'
2172 { vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_STRING, true,
2180 /* These rules for tf_port_item are slightly expanded from the
2181 strict rules in the LRM to help with LALR parsing.
2183 NOTE: Some of these rules should be folded into the "data_type"
2184 variant which uses the data_type rule to match data type
2185 declarations. That some rules do not use the data_type production
2186 is a consequence of legacy. */
2188 tf_port_item /* IEEE1800-2005: A.2.7 */
2190 : port_direction_opt data_type_or_implicit IDENTIFIER dimensions_opt tf_port_item_expr_opt
2191 { vector<pform_tf_port_t>*tmp;
2192 NetNet::PortType use_port_type = $1;
2193 if ((use_port_type == NetNet::PIMPLICIT) && (gn_system_verilog() || ($2 == 0)))
2194 use_port_type = port_declaration_context.port_type;
2195 perm_string name = lex_strings.make($3);
2196 list<perm_string>* ilist = list_from_identifier($3);
2198 if (use_port_type == NetNet::PIMPLICIT) {
2199 yyerror(@1, "error: missing task/function port direction.");
2200 use_port_type = NetNet::PINPUT; // for error recovery
2202 if (($2 == 0) && ($1==NetNet::PIMPLICIT)) {
2203 // Detect special case this is an undecorated
2204 // identifier and we need to get the declaration from
2207 yyerror(@4, "internal error: How can there be an unpacked range here?\n");
2209 tmp = pform_make_task_ports(@3, use_port_type,
2210 port_declaration_context.data_type,
2214 // Otherwise, the decorations for this identifier
2215 // indicate the type. Save the type for any right
2216 // context that may come later.
2217 port_declaration_context.port_type = use_port_type;
2219 $2 = new vector_type_t(IVL_VT_LOGIC, false, 0);
2222 port_declaration_context.data_type = $2;
2223 tmp = pform_make_task_ports(@3, use_port_type, $2, ilist);
2226 pform_set_reg_idx(name, $4);
2231 assert(tmp->size()==1);
2232 tmp->front().defe = $5;
2236 /* Rules to match error cases... */
2238 | port_direction_opt data_type_or_implicit IDENTIFIER error
2239 { yyerror(@3, "error: Error in task/function port item after port name %s.", $3);
2245 /* This rule matches the [ = <expression> ] part of the tf_port_item rules. */
2247 tf_port_item_expr_opt
2249 { if (! gn_system_verilog()) {
2250 yyerror(@1, "error: Task/function default arguments require "
2258 tf_port_list /* IEEE1800-2005: A.2.7 */
2259 : { port_declaration_context.port_type = gn_system_verilog() ? NetNet::PINPUT : NetNet::PIMPLICIT;
2260 port_declaration_context.data_type = 0;
2267 : tf_port_item_list ',' tf_port_item
2268 { vector<pform_tf_port_t>*tmp;
2270 size_t s1 = $1->size();
2272 tmp->resize(tmp->size()+$3->size());
2273 for (size_t idx = 0 ; idx < $3->size() ; idx += 1)
2274 tmp->at(s1+idx) = $3->at(idx);
2287 /* Rules to handle some errors in tf_port_list items. */
2289 | error ',' tf_port_item
2290 { yyerror(@2, "error: Syntax error in task/function port declaration.");
2293 | tf_port_item_list ','
2294 { yyerror(@2, "error: NULL port declarations are not allowed.");
2297 | tf_port_item_list ';'
2298 { yyerror(@2, "error: ';' is an invalid port declaration separator.");
2303 timeunits_declaration /* IEEE1800-2005: A.1.2 */
2304 : K_timeunit TIME_LITERAL ';'
2305 { pform_set_timeunit($2, allow_timeunit_decl); }
2306 | K_timeunit TIME_LITERAL '/' TIME_LITERAL ';'
2307 { bool initial_decl = allow_timeunit_decl && allow_timeprec_decl;
2308 pform_set_timeunit($2, initial_decl);
2309 pform_set_timeprec($4, initial_decl);
2311 | K_timeprecision TIME_LITERAL ';'
2312 { pform_set_timeprec($2, allow_timeprec_decl); }
2315 /* Allow zero, one, or two declarations. The second declaration might
2316 be a repeat declaration, but the pform functions take care of that. */
2317 timeunits_declaration_opt
2318 : /* empty */ %prec no_timeunits_declaration
2319 | timeunits_declaration %prec one_timeunits_declaration
2320 | timeunits_declaration timeunits_declaration
2323 value_range /* IEEE1800-2005: A.8.3 */
2326 | '[' expression ':' expression ']'
2330 variable_dimension /* IEEE1800-2005: A.2.5 */
2331 : '[' expression ':' expression ']'
2332 { list<pform_range_t> *tmp = new list<pform_range_t>;
2333 pform_range_t index ($2,$4);
2334 tmp->push_back(index);
2337 | '[' expression ']'
2338 { // SystemVerilog canonical range
2339 if (!gn_system_verilog()) {
2341 cerr << @2 << ": warning: Use of SystemVerilog [size] dimension. "
2342 << "Use at least -g2005-sv to remove this warning." << endl;
2344 list<pform_range_t> *tmp = new list<pform_range_t>;
2345 pform_range_t index;
2346 index.first = new PENumber(new verinum((uint64_t)0, integer_width));
2347 index.second = new PEBinary('-', $2, new PENumber(new verinum((uint64_t)1, integer_width)));
2348 tmp->push_back(index);
2352 { list<pform_range_t> *tmp = new list<pform_range_t>;
2353 pform_range_t index (0,0);
2354 tmp->push_back(index);
2358 { // SystemVerilog queue
2359 list<pform_range_t> *tmp = new list<pform_range_t>;
2360 pform_range_t index (new PENull,0);
2361 if (!gn_system_verilog()) {
2362 yyerror("error: Queue declarations require SystemVerilog.");
2364 tmp->push_back(index);
2371 { if (!gn_system_verilog()) {
2372 yyerror(@1, "error: overriding the default variable lifetime "
2373 "requires SystemVerilog.");
2374 } else if ($1 != pform_peek_scope()->default_lifetime) {
2375 yyerror(@1, "sorry: overriding the default variable lifetime "
2376 "is not yet supported.");
2382 /* Verilog-2001 supports attribute lists, which can be attached to a
2383 variety of different objects. The syntax inside the (* *) is a
2384 comma separated list of names or names with assigned values. */
2386 : attribute_instance_list
2392 attribute_instance_list
2393 : K_PSTAR K_STARP { $$ = 0; }
2394 | K_PSTAR attribute_list K_STARP { $$ = $2; }
2395 | attribute_instance_list K_PSTAR K_STARP { $$ = $1; }
2396 | attribute_instance_list K_PSTAR attribute_list K_STARP
2397 { list<named_pexpr_t>*tmp = $1;
2399 tmp->splice(tmp->end(), *$3);
2407 : attribute_list ',' attribute
2408 { list<named_pexpr_t>*tmp = $1;
2409 tmp->push_back(*$3);
2414 { list<named_pexpr_t>*tmp = new list<named_pexpr_t>;
2415 tmp->push_back(*$1);
2424 { named_pexpr_t*tmp = new named_pexpr_t;
2425 tmp->name = lex_strings.make($1);
2430 | IDENTIFIER '=' expression
2432 named_pexpr_t*tmp2 = new named_pexpr_t;
2433 tmp2->name = lex_strings.make($1);
2441 /* The block_item_decl is used in function definitions, task
2442 definitions, module definitions and named blocks. Wherever a new
2443 scope is entered, the source may declare new registers and
2444 integers. This rule matches those declarations. The containing
2445 rule has presumably set up the scope. */
2449 /* variable declarations. Note that data_type can be 0 if we are
2450 recovering from an error. */
2452 : data_type register_variable_list ';'
2453 { if ($1) pform_set_data_type(@1, $1, $2, NetNet::REG, attributes_in_context);
2456 | variable_lifetime data_type register_variable_list ';'
2457 { if ($2) pform_set_data_type(@2, $2, $3, NetNet::REG, attributes_in_context);
2458 var_lifetime = LexicalScope::INHERITED;
2461 | K_reg data_type register_variable_list ';'
2462 { if ($2) pform_set_data_type(@2, $2, $3, NetNet::REG, attributes_in_context);
2465 | variable_lifetime K_reg data_type register_variable_list ';'
2466 { if ($3) pform_set_data_type(@3, $3, $4, NetNet::REG, attributes_in_context);
2467 var_lifetime = LexicalScope::INHERITED;
2470 | K_event event_variable_list ';'
2471 { if ($2) pform_make_events($2, @1.text, @1.first_line);
2474 | K_parameter param_type parameter_assign_list ';'
2475 | K_localparam param_type localparam_assign_list ';'
2477 /* Blocks can have type declarations. */
2481 /* Recover from errors that happen within variable lists. Use the
2482 trailing semi-colon to resync the parser. */
2484 | K_integer error ';'
2485 { yyerror(@1, "error: syntax error in integer variable list.");
2490 { yyerror(@1, "error: syntax error in time variable list.");
2494 | K_parameter error ';'
2495 { yyerror(@1, "error: syntax error in parameter list.");
2498 | K_localparam error ';'
2499 { yyerror(@1, "error: syntax error localparam list.");
2506 | block_item_decls block_item_decl
2509 block_item_decls_opt
2510 : block_item_decls { $$ = true; }
2514 /* Type declarations are parsed here. The rule actions call pform
2515 functions that add the declaration to the current lexical scope. */
2517 : K_typedef data_type IDENTIFIER dimensions_opt ';'
2518 { perm_string name = lex_strings.make($3);
2519 pform_set_typedef(name, $2, $4);
2523 /* If the IDENTIFIER already is a typedef, it is possible for this
2524 code to override the definition, but only if the typedef is
2525 inherited from a different scope. */
2526 | K_typedef data_type TYPE_IDENTIFIER ';'
2527 { perm_string name = lex_strings.make($3.text);
2528 if (pform_test_type_identifier_local(name)) {
2529 yyerror(@3, "error: Typedef identifier \"%s\" is already a type name.", $3.text);
2532 pform_set_typedef(name, $2, NULL);
2537 /* These are forward declarations... */
2539 | K_typedef K_class IDENTIFIER ';'
2540 { // Create a synthetic typedef for the class name so that the
2541 // lexor detects the name as a type.
2542 perm_string name = lex_strings.make($3);
2543 class_type_t*tmp = new class_type_t(name);
2545 pform_set_typedef(name, tmp, NULL);
2548 | K_typedef K_enum IDENTIFIER ';'
2549 { yyerror(@1, "sorry: Enum forward declarations not supported yet."); }
2550 | K_typedef K_struct IDENTIFIER ';'
2551 { yyerror(@1, "sorry: Struct forward declarations not supported yet."); }
2552 | K_typedef K_union IDENTIFIER ';'
2553 { yyerror(@1, "sorry: Union forward declarations not supported yet."); }
2554 | K_typedef IDENTIFIER ';'
2555 { // Create a synthetic typedef for the class name so that the
2556 // lexor detects the name as a type.
2557 perm_string name = lex_strings.make($2);
2558 class_type_t*tmp = new class_type_t(name);
2560 pform_set_typedef(name, tmp, NULL);
2564 | K_typedef error ';'
2565 { yyerror(@2, "error: Syntax error in typedef clause.");
2571 /* The structure for an enumeration data type is the keyword "enum",
2572 followed by the enumeration values in curly braces. Also allow
2573 for an optional base type. The default base type is "int", but it
2574 can be any of the integral or vector types. */
2577 : K_enum '{' enum_name_list '}'
2578 { enum_type_t*enum_type = new enum_type_t;
2579 FILE_NAME(enum_type, @1);
2580 enum_type->names .reset($3);
2581 enum_type->base_type = IVL_VT_BOOL;
2582 enum_type->signed_flag = true;
2583 enum_type->integer_flag = false;
2584 enum_type->range.reset(make_range_from_width(32));
2587 | K_enum atom2_type signed_unsigned_opt '{' enum_name_list '}'
2588 { enum_type_t*enum_type = new enum_type_t;
2589 FILE_NAME(enum_type, @1);
2590 enum_type->names .reset($5);
2591 enum_type->base_type = IVL_VT_BOOL;
2592 enum_type->signed_flag = $3;
2593 enum_type->integer_flag = false;
2594 enum_type->range.reset(make_range_from_width($2));
2597 | K_enum K_integer signed_unsigned_opt '{' enum_name_list '}'
2598 { enum_type_t*enum_type = new enum_type_t;
2599 FILE_NAME(enum_type, @1);
2600 enum_type->names .reset($5);
2601 enum_type->base_type = IVL_VT_LOGIC;
2602 enum_type->signed_flag = $3;
2603 enum_type->integer_flag = true;
2604 enum_type->range.reset(make_range_from_width(integer_width));
2607 | K_enum K_logic unsigned_signed_opt dimensions_opt '{' enum_name_list '}'
2608 { enum_type_t*enum_type = new enum_type_t;
2609 FILE_NAME(enum_type, @1);
2610 enum_type->names .reset($6);
2611 enum_type->base_type = IVL_VT_LOGIC;
2612 enum_type->signed_flag = $3;
2613 enum_type->integer_flag = false;
2614 enum_type->range.reset($4 ? $4 : make_range_from_width(1));
2617 | K_enum K_reg unsigned_signed_opt dimensions_opt '{' enum_name_list '}'
2618 { enum_type_t*enum_type = new enum_type_t;
2619 FILE_NAME(enum_type, @1);
2620 enum_type->names .reset($6);
2621 enum_type->base_type = IVL_VT_LOGIC;
2622 enum_type->signed_flag = $3;
2623 enum_type->integer_flag = false;
2624 enum_type->range.reset($4 ? $4 : make_range_from_width(1));
2627 | K_enum K_bit unsigned_signed_opt dimensions_opt '{' enum_name_list '}'
2628 { enum_type_t*enum_type = new enum_type_t;
2629 FILE_NAME(enum_type, @1);
2630 enum_type->names .reset($6);
2631 enum_type->base_type = IVL_VT_BOOL;
2632 enum_type->signed_flag = $3;
2633 enum_type->integer_flag = false;
2634 enum_type->range.reset($4 ? $4 : make_range_from_width(1));
2643 | enum_name_list ',' enum_name
2644 { list<named_pexpr_t>*lst = $1;
2645 lst->splice(lst->end(), *$3);
2656 { verinum tmp = -(*($2));
2664 { perm_string name = lex_strings.make($1);
2666 $$ = make_named_number(name);
2668 | IDENTIFIER '[' pos_neg_number ']'
2669 { perm_string name = lex_strings.make($1);
2670 long count = check_enum_seq_value(@1, $3, false);
2672 $$ = make_named_numbers(name, 0, count-1);
2675 | IDENTIFIER '[' pos_neg_number ':' pos_neg_number ']'
2676 { perm_string name = lex_strings.make($1);
2677 $$ = make_named_numbers(name, check_enum_seq_value(@1, $3, true),
2678 check_enum_seq_value(@1, $5, true));
2683 | IDENTIFIER '=' expression
2684 { perm_string name = lex_strings.make($1);
2686 $$ = make_named_number(name, $3);
2688 | IDENTIFIER '[' pos_neg_number ']' '=' expression
2689 { perm_string name = lex_strings.make($1);
2690 long count = check_enum_seq_value(@1, $3, false);
2691 $$ = make_named_numbers(name, 0, count-1, $6);
2695 | IDENTIFIER '[' pos_neg_number ':' pos_neg_number ']' '=' expression
2696 { perm_string name = lex_strings.make($1);
2697 $$ = make_named_numbers(name, check_enum_seq_value(@1, $3, true),
2698 check_enum_seq_value(@1, $5, true), $8);
2706 : K_struct K_packed_opt '{' struct_union_member_list '}'
2707 { struct_type_t*tmp = new struct_type_t;
2709 tmp->packed_flag = $2;
2710 tmp->union_flag = false;
2711 tmp->members .reset($4);
2714 | K_union K_packed_opt '{' struct_union_member_list '}'
2715 { struct_type_t*tmp = new struct_type_t;
2717 tmp->packed_flag = $2;
2718 tmp->union_flag = true;
2719 tmp->members .reset($4);
2722 | K_struct K_packed_opt '{' error '}'
2723 { yyerror(@3, "error: Errors in struct member list.");
2725 struct_type_t*tmp = new struct_type_t;
2727 tmp->packed_flag = $2;
2728 tmp->union_flag = false;
2731 | K_union K_packed_opt '{' error '}'
2732 { yyerror(@3, "error: Errors in union member list.");
2734 struct_type_t*tmp = new struct_type_t;
2736 tmp->packed_flag = $2;
2737 tmp->union_flag = true;
2742 /* This is an implementation of the rule snippet:
2743 struct_union_member { struct_union_member }
2744 that is used in the rule matching struct and union types
2745 in IEEE 1800-2012 A.2.2.1. */
2746 struct_union_member_list
2747 : struct_union_member_list struct_union_member
2748 { list<struct_member_t*>*tmp = $1;
2752 | struct_union_member
2753 { list<struct_member_t*>*tmp = new list<struct_member_t*>;
2759 struct_union_member /* IEEE 1800-2012 A.2.2.1 */
2760 : attribute_list_opt data_type list_of_variable_decl_assignments ';'
2761 { struct_member_t*tmp = new struct_member_t;
2763 tmp->type .reset($2);
2764 tmp->names .reset($3);
2768 { yyerror(@2, "Error in struct/union member.");
2775 : expression_list_proper ':' statement_or_null
2776 { PCase::Item*tmp = new PCase::Item;
2782 | K_default ':' statement_or_null
2783 { PCase::Item*tmp = new PCase::Item;
2787 | K_default statement_or_null
2788 { PCase::Item*tmp = new PCase::Item;
2792 | error ':' statement_or_null
2793 { yyerror(@2, "error: Incomprehensible case expression.");
2799 : case_items case_item
2800 { svector<PCase::Item*>*tmp;
2801 tmp = new svector<PCase::Item*>(*$1, $2);
2806 { svector<PCase::Item*>*tmp = new svector<PCase::Item*>(1);
2824 : hierarchy_identifier '=' expression
2825 { pform_set_defparam(*$1, $3);
2830 defparam_assign_list
2832 | dimensions defparam_assign
2833 { yyerror(@1, "error: defparam may not include a range.");
2836 | defparam_assign_list ',' defparam_assign
2840 : '#' delay_value_simple
2841 { list<PExpr*>*tmp = new list<PExpr*>;
2845 | '#' '(' delay_value ')'
2846 { list<PExpr*>*tmp = new list<PExpr*>;
2853 : '#' delay_value_simple
2854 { list<PExpr*>*tmp = new list<PExpr*>;
2858 | '#' '(' delay_value ')'
2859 { list<PExpr*>*tmp = new list<PExpr*>;
2863 | '#' '(' delay_value ',' delay_value ')'
2864 { list<PExpr*>*tmp = new list<PExpr*>;
2869 | '#' '(' delay_value ',' delay_value ',' delay_value ')'
2870 { list<PExpr*>*tmp = new list<PExpr*>;
2879 : delay3 { $$ = $1; }
2885 { list<PExpr*>*tmp = new list<PExpr*>;
2889 | delay_value_list ',' delay_value
2890 { list<PExpr*>*tmp = $1;
2901 | expression ':' expression ':' expression
2902 { $$ = pform_select_mtm_expr($1, $3, $5); }
2910 yyerror(@1, "internal error: delay.");
2913 $$ = new PENumber(tmp);
2919 { verireal*tmp = $1;
2921 yyerror(@1, "internal error: delay.");
2924 $$ = new PEFNumber(tmp);
2929 { PEIdent*tmp = new PEIdent(lex_strings.make($1));
2939 if ($1 == 0 || !get_time_unit($1, unit))
2940 yyerror(@1, "internal error: delay.");
2942 double p = pow(10.0,
2943 (double)(unit - pform_get_timeunit()));
2944 double time = atof($1) * p;
2946 verireal *v = new verireal(time);
2947 $$ = new PEFNumber(v);
2953 /* The discipline and nature declarations used to take no ';' after
2954 the identifier. The 2.3 LRM adds the ';', but since there are
2955 programs written to the 2.1 and 2.2 standard that don't, we
2956 choose to make the ';' optional in this context. */
2957 optional_semicolon : ';' | ;
2959 discipline_declaration
2960 : K_discipline IDENTIFIER optional_semicolon
2961 { pform_start_discipline($2); }
2962 discipline_items K_enddiscipline
2963 { pform_end_discipline(@1); delete[] $2; }
2967 : discipline_items discipline_item
2972 : K_domain K_discrete ';'
2973 { pform_discipline_domain(@1, IVL_DIS_DISCRETE); }
2974 | K_domain K_continuous ';'
2975 { pform_discipline_domain(@1, IVL_DIS_CONTINUOUS); }
2976 | K_potential IDENTIFIER ';'
2977 { pform_discipline_potential(@1, $2); delete[] $2; }
2978 | K_flow IDENTIFIER ';'
2979 { pform_discipline_flow(@1, $2); delete[] $2; }
2983 : K_nature IDENTIFIER optional_semicolon
2984 { pform_start_nature($2); }
2987 { pform_end_nature(@1); delete[] $2; }
2991 : nature_items nature_item
2996 : K_units '=' STRING ';'
2998 | K_abstol '=' expression ';'
2999 | K_access '=' IDENTIFIER ';'
3000 { pform_nature_access(@1, $3); delete[] $3; }
3001 | K_idt_nature '=' IDENTIFIER ';'
3003 | K_ddt_nature '=' IDENTIFIER ';'
3008 : K_config IDENTIFIER ';'
3009 K_design lib_cell_identifiers ';'
3010 list_of_config_rule_statements
3012 { cerr << @1 << ": sorry: config declarations are not supported and "
3013 "will be skipped." << endl;
3018 lib_cell_identifiers
3019 : /* The BNF implies this can be blank, but I'm not sure exactly what
3021 | lib_cell_identifiers lib_cell_id
3024 list_of_config_rule_statements
3025 : /* config rules are optional. */
3026 | list_of_config_rule_statements config_rule_statement
3029 config_rule_statement
3030 : K_default K_liblist list_of_libraries ';'
3031 | K_instance hierarchy_identifier K_liblist list_of_libraries ';'
3033 | K_instance hierarchy_identifier K_use lib_cell_id opt_config ';'
3035 | K_cell lib_cell_id K_liblist list_of_libraries ';'
3036 | K_cell lib_cell_id K_use lib_cell_id opt_config ';'
3040 : /* The use clause takes an optional :config. */
3047 | IDENTIFIER '.' IDENTIFIER
3048 { delete[] $1; delete[] $3; }
3052 : /* A NULL library means use the parents cell library. */
3053 | list_of_libraries IDENTIFIER
3058 : '(' dr_strength0 ',' dr_strength1 ')'
3059 { $$.str0 = $2.str0;
3062 | '(' dr_strength1 ',' dr_strength0 ')'
3063 { $$.str0 = $4.str0;
3066 | '(' dr_strength0 ',' K_highz1 ')'
3067 { $$.str0 = $2.str0;
3068 $$.str1 = IVL_DR_HiZ;
3070 | '(' dr_strength1 ',' K_highz0 ')'
3071 { $$.str0 = IVL_DR_HiZ;
3074 | '(' K_highz1 ',' dr_strength0 ')'
3075 { $$.str0 = $4.str0;
3076 $$.str1 = IVL_DR_HiZ;
3078 | '(' K_highz0 ',' dr_strength1 ')'
3079 { $$.str0 = IVL_DR_HiZ;
3085 : drive_strength { $$ = $1; }
3086 | { $$.str0 = IVL_DR_STRONG; $$.str1 = IVL_DR_STRONG; }
3090 : K_supply0 { $$.str0 = IVL_DR_SUPPLY; }
3091 | K_strong0 { $$.str0 = IVL_DR_STRONG; }
3092 | K_pull0 { $$.str0 = IVL_DR_PULL; }
3093 | K_weak0 { $$.str0 = IVL_DR_WEAK; }
3097 : K_supply1 { $$.str1 = IVL_DR_SUPPLY; }
3098 | K_strong1 { $$.str1 = IVL_DR_STRONG; }
3099 | K_pull1 { $$.str1 = IVL_DR_PULL; }
3100 | K_weak1 { $$.str1 = IVL_DR_WEAK; }
3103 clocking_event_opt /* */
3108 event_control /* A.K.A. clocking_event */
3109 : '@' hierarchy_identifier
3110 { PEIdent*tmpi = new PEIdent(*$2);
3111 PEEvent*tmpe = new PEEvent(PEEvent::ANYEDGE, tmpi);
3112 PEventStatement*tmps = new PEventStatement(tmpe);
3113 FILE_NAME(tmps, @1);
3117 | '@' '(' event_expression_list ')'
3118 { PEventStatement*tmp = new PEventStatement(*$3);
3124 { yyerror(@1, "error: Malformed event control expression.");
3129 event_expression_list
3132 | event_expression_list K_or event_expression
3133 { svector<PEEvent*>*tmp = new svector<PEEvent*>(*$1, *$3);
3138 | event_expression_list ',' event_expression
3139 { svector<PEEvent*>*tmp = new svector<PEEvent*>(*$1, *$3);
3147 : K_posedge expression
3148 { PEEvent*tmp = new PEEvent(PEEvent::POSEDGE, $2);
3150 svector<PEEvent*>*tl = new svector<PEEvent*>(1);
3154 | K_negedge expression
3155 { PEEvent*tmp = new PEEvent(PEEvent::NEGEDGE, $2);
3157 svector<PEEvent*>*tl = new svector<PEEvent*>(1);
3162 { PEEvent*tmp = new PEEvent(PEEvent::ANYEDGE, $1);
3164 svector<PEEvent*>*tl = new svector<PEEvent*>(1);
3170 /* A branch probe expression applies a probe function (potential or
3171 flow) to a branch. The branch may be implicit as a pair of nets
3172 or explicit as a named branch. Elaboration will check that the
3173 function name really is a nature attribute identifier. */
3174 branch_probe_expression
3175 : IDENTIFIER '(' IDENTIFIER ',' IDENTIFIER ')'
3176 { $$ = pform_make_branch_probe_expression(@1, $1, $3, $5); }
3177 | IDENTIFIER '(' IDENTIFIER ')'
3178 { $$ = pform_make_branch_probe_expression(@1, $1, $3); }
3182 : expr_primary_or_typename
3184 | inc_or_dec_expression
3188 | '+' attribute_list_opt expr_primary %prec UNARY_PREC
3190 | '-' attribute_list_opt expr_primary %prec UNARY_PREC
3191 { PEUnary*tmp = new PEUnary('-', $3);
3195 | '~' attribute_list_opt expr_primary %prec UNARY_PREC
3196 { PEUnary*tmp = new PEUnary('~', $3);
3200 | '&' attribute_list_opt expr_primary %prec UNARY_PREC
3201 { PEUnary*tmp = new PEUnary('&', $3);
3205 | '!' attribute_list_opt expr_primary %prec UNARY_PREC
3206 { PEUnary*tmp = new PEUnary('!', $3);
3210 | '|' attribute_list_opt expr_primary %prec UNARY_PREC
3211 { PEUnary*tmp = new PEUnary('|', $3);
3215 | '^' attribute_list_opt expr_primary %prec UNARY_PREC
3216 { PEUnary*tmp = new PEUnary('^', $3);
3220 | '~' '&' attribute_list_opt expr_primary %prec UNARY_PREC
3221 { yyerror(@1, "error: '~' '&' is not a valid expression. "
3222 "Please use operator '~&' instead.");
3225 | '~' '|' attribute_list_opt expr_primary %prec UNARY_PREC
3226 { yyerror(@1, "error: '~' '|' is not a valid expression. "
3227 "Please use operator '~|' instead.");
3230 | '~' '^' attribute_list_opt expr_primary %prec UNARY_PREC
3231 { yyerror(@1, "error: '~' '^' is not a valid expression. "
3232 "Please use operator '~^' instead.");
3235 | K_NAND attribute_list_opt expr_primary %prec UNARY_PREC
3236 { PEUnary*tmp = new PEUnary('A', $3);
3240 | K_NOR attribute_list_opt expr_primary %prec UNARY_PREC
3241 { PEUnary*tmp = new PEUnary('N', $3);
3245 | K_NXOR attribute_list_opt expr_primary %prec UNARY_PREC
3246 { PEUnary*tmp = new PEUnary('X', $3);
3250 | '!' error %prec UNARY_PREC
3251 { yyerror(@1, "error: Operand of unary ! "
3252 "is not a primary expression.");
3255 | '^' error %prec UNARY_PREC
3256 { yyerror(@1, "error: Operand of reduction ^ "
3257 "is not a primary expression.");
3260 | expression '^' attribute_list_opt expression
3261 { PEBinary*tmp = new PEBinary('^', $1, $4);
3265 | expression K_POW attribute_list_opt expression
3266 { PEBinary*tmp = new PEBPower('p', $1, $4);
3270 | expression '*' attribute_list_opt expression
3271 { PEBinary*tmp = new PEBinary('*', $1, $4);
3275 | expression '/' attribute_list_opt expression
3276 { PEBinary*tmp = new PEBinary('/', $1, $4);
3280 | expression '%' attribute_list_opt expression
3281 { PEBinary*tmp = new PEBinary('%', $1, $4);
3285 | expression '+' attribute_list_opt expression
3286 { PEBinary*tmp = new PEBinary('+', $1, $4);
3290 | expression '-' attribute_list_opt expression
3291 { PEBinary*tmp = new PEBinary('-', $1, $4);
3295 | expression '&' attribute_list_opt expression
3296 { PEBinary*tmp = new PEBinary('&', $1, $4);
3300 | expression '|' attribute_list_opt expression
3301 { PEBinary*tmp = new PEBinary('|', $1, $4);
3305 | expression K_NAND attribute_list_opt expression
3306 { PEBinary*tmp = new PEBinary('A', $1, $4);
3310 | expression K_NOR attribute_list_opt expression
3311 { PEBinary*tmp = new PEBinary('O', $1, $4);
3315 | expression K_NXOR attribute_list_opt expression
3316 { PEBinary*tmp = new PEBinary('X', $1, $4);
3320 | expression '<' attribute_list_opt expression
3321 { PEBinary*tmp = new PEBComp('<', $1, $4);
3325 | expression '>' attribute_list_opt expression
3326 { PEBinary*tmp = new PEBComp('>', $1, $4);
3330 | expression K_LS attribute_list_opt expression
3331 { PEBinary*tmp = new PEBShift('l', $1, $4);
3335 | expression K_RS attribute_list_opt expression
3336 { PEBinary*tmp = new PEBShift('r', $1, $4);
3340 | expression K_RSS attribute_list_opt expression
3341 { PEBinary*tmp = new PEBShift('R', $1, $4);
3345 | expression K_EQ attribute_list_opt expression
3346 { PEBinary*tmp = new PEBComp('e', $1, $4);
3350 | expression K_CEQ attribute_list_opt expression
3351 { PEBinary*tmp = new PEBComp('E', $1, $4);
3355 | expression K_WEQ attribute_list_opt expression
3356 { PEBinary*tmp = new PEBComp('w', $1, $4);
3360 | expression K_LE attribute_list_opt expression
3361 { PEBinary*tmp = new PEBComp('L', $1, $4);
3365 | expression K_GE attribute_list_opt expression
3366 { PEBinary*tmp = new PEBComp('G', $1, $4);
3370 | expression K_NE attribute_list_opt expression
3371 { PEBinary*tmp = new PEBComp('n', $1, $4);
3375 | expression K_CNE attribute_list_opt expression
3376 { PEBinary*tmp = new PEBComp('N', $1, $4);
3380 | expression K_WNE attribute_list_opt expression
3381 { PEBinary*tmp = new PEBComp('W', $1, $4);
3385 | expression K_LOR attribute_list_opt expression
3386 { PEBinary*tmp = new PEBLogic('o', $1, $4);
3390 | expression K_LAND attribute_list_opt expression
3391 { PEBinary*tmp = new PEBLogic('a', $1, $4);
3395 | expression '?' attribute_list_opt expression ':' expression
3396 { PETernary*tmp = new PETernary($1, $4, $6);
3405 | expression ':' expression ':' expression
3406 { switch (min_typ_max_flag) {
3423 if (min_typ_max_warn > 0) {
3424 cerr << $$->get_fileline() << ": warning: choosing ";
3425 switch (min_typ_max_flag) {
3436 cerr << " expression." << endl;
3437 min_typ_max_warn -= 1;
3443 /* Many contexts take a comma separated list of expressions. Null
3444 expressions can happen anywhere in the list, so there are two
3445 extra rules in expression_list_with_nuls for parsing and
3446 installing those nulls.
3448 The expression_list_proper rules do not allow null items in the
3449 expression list, so can be used where nul expressions are not allowed. */
3451 expression_list_with_nuls
3452 : expression_list_with_nuls ',' expression
3453 { list<PExpr*>*tmp = $1;
3458 { list<PExpr*>*tmp = new list<PExpr*>;
3463 { list<PExpr*>*tmp = new list<PExpr*>;
3467 | expression_list_with_nuls ','
3468 { list<PExpr*>*tmp = $1;
3474 expression_list_proper
3475 : expression_list_proper ',' expression
3476 { list<PExpr*>*tmp = $1;
3481 { list<PExpr*>*tmp = new list<PExpr*>;
3487 expr_primary_or_typename
3490 /* There are a few special cases (notably $bits argument) where the
3491 expression may be a type name. Let the elaborator sort this out. */
3493 { PETypename*tmp = new PETypename($1.type);
3504 PENumber*tmp = new PENumber($1);
3509 { PEFNumber*tmp = new PEFNumber($1);
3514 { PEString*tmp = new PEString($1);
3523 if ($1 == 0 || !get_time_unit($1, unit))
3524 yyerror(@1, "internal error: delay.");
3526 double p = pow(10.0, (double)(unit - pform_get_timeunit()));
3527 double time = atof($1) * p;
3529 verireal *v = new verireal(time);
3530 $$ = new PEFNumber(v);
3535 { perm_string tn = lex_strings.make($1);
3536 PECallFunction*tmp = new PECallFunction(tn);
3542 /* The hierarchy_identifier rule matches simple identifiers as well as
3543 indexed arrays and part selects */
3545 | hierarchy_identifier
3546 { PEIdent*tmp = pform_new_ident(*$1);
3552 | PACKAGE_IDENTIFIER K_SCOPE_RES hierarchy_identifier
3553 { $$ = pform_package_ident(@2, $1, $3);
3557 /* An identifier followed by an expression list in parentheses is a
3558 function call. If a system identifier, then a system function
3559 call. It can also be a call to a class method (function). */
3561 | hierarchy_identifier '(' expression_list_with_nuls ')'
3562 { list<PExpr*>*expr_list = $3;
3563 strip_tail_items(expr_list);
3564 PECallFunction*tmp = pform_make_call_function(@1, *$1, *expr_list);
3568 | implicit_class_handle '.' hierarchy_identifier '(' expression_list_with_nuls ')'
3569 { pform_name_t*t_name = $1;
3570 while (! $3->empty()) {
3571 t_name->push_back($3->front());
3574 list<PExpr*>*expr_list = $5;
3575 strip_tail_items(expr_list);
3576 PECallFunction*tmp = pform_make_call_function(@1, *t_name, *expr_list);
3581 | SYSTEM_IDENTIFIER '(' expression_list_proper ')'
3582 { perm_string tn = lex_strings.make($1);
3583 PECallFunction*tmp = new PECallFunction(tn, *$3);
3588 | PACKAGE_IDENTIFIER K_SCOPE_RES IDENTIFIER '(' expression_list_proper ')'
3589 { perm_string use_name = lex_strings.make($3);
3590 PECallFunction*tmp = new PECallFunction($1, use_name, *$5);
3595 | SYSTEM_IDENTIFIER '(' ')'
3596 { perm_string tn = lex_strings.make($1);
3597 const vector<PExpr*>empty;
3598 PECallFunction*tmp = new PECallFunction(tn, empty);
3602 if (!gn_system_verilog()) {
3603 yyerror(@1, "error: Empty function argument list requires SystemVerilog.");
3607 | implicit_class_handle
3608 { PEIdent*tmp = new PEIdent(*$1);
3614 | implicit_class_handle '.' hierarchy_identifier
3615 { pform_name_t*t_name = $1;
3616 while (! $3->empty()) {
3617 t_name->push_back($3->front());
3620 PEIdent*tmp = new PEIdent(*t_name);
3627 /* Many of the VAMS built-in functions are available as builtin
3628 functions with $system_function equivalents. */
3630 | K_acos '(' expression ')'
3631 { perm_string tn = perm_string::literal("$acos");
3632 PECallFunction*tmp = make_call_function(tn, $3);
3637 | K_acosh '(' expression ')'
3638 { perm_string tn = perm_string::literal("$acosh");
3639 PECallFunction*tmp = make_call_function(tn, $3);
3644 | K_asin '(' expression ')'
3645 { perm_string tn = perm_string::literal("$asin");
3646 PECallFunction*tmp = make_call_function(tn, $3);
3651 | K_asinh '(' expression ')'
3652 { perm_string tn = perm_string::literal("$asinh");
3653 PECallFunction*tmp = make_call_function(tn, $3);
3658 | K_atan '(' expression ')'
3659 { perm_string tn = perm_string::literal("$atan");
3660 PECallFunction*tmp = make_call_function(tn, $3);
3665 | K_atanh '(' expression ')'
3666 { perm_string tn = perm_string::literal("$atanh");
3667 PECallFunction*tmp = make_call_function(tn, $3);
3672 | K_atan2 '(' expression ',' expression ')'
3673 { perm_string tn = perm_string::literal("$atan2");
3674 PECallFunction*tmp = make_call_function(tn, $3, $5);
3679 | K_ceil '(' expression ')'
3680 { perm_string tn = perm_string::literal("$ceil");
3681 PECallFunction*tmp = make_call_function(tn, $3);
3686 | K_cos '(' expression ')'
3687 { perm_string tn = perm_string::literal("$cos");
3688 PECallFunction*tmp = make_call_function(tn, $3);
3693 | K_cosh '(' expression ')'
3694 { perm_string tn = perm_string::literal("$cosh");
3695 PECallFunction*tmp = make_call_function(tn, $3);
3700 | K_exp '(' expression ')'
3701 { perm_string tn = perm_string::literal("$exp");
3702 PECallFunction*tmp = make_call_function(tn, $3);
3707 | K_floor '(' expression ')'
3708 { perm_string tn = perm_string::literal("$floor");
3709 PECallFunction*tmp = make_call_function(tn, $3);
3714 | K_hypot '(' expression ',' expression ')'
3715 { perm_string tn = perm_string::literal("$hypot");
3716 PECallFunction*tmp = make_call_function(tn, $3, $5);
3721 | K_ln '(' expression ')'
3722 { perm_string tn = perm_string::literal("$ln");
3723 PECallFunction*tmp = make_call_function(tn, $3);
3728 | K_log '(' expression ')'
3729 { perm_string tn = perm_string::literal("$log10");
3730 PECallFunction*tmp = make_call_function(tn, $3);
3735 | K_pow '(' expression ',' expression ')'
3736 { perm_string tn = perm_string::literal("$pow");
3737 PECallFunction*tmp = make_call_function(tn, $3, $5);
3742 | K_sin '(' expression ')'
3743 { perm_string tn = perm_string::literal("$sin");
3744 PECallFunction*tmp = make_call_function(tn, $3);
3749 | K_sinh '(' expression ')'
3750 { perm_string tn = perm_string::literal("$sinh");
3751 PECallFunction*tmp = make_call_function(tn, $3);
3756 | K_sqrt '(' expression ')'
3757 { perm_string tn = perm_string::literal("$sqrt");
3758 PECallFunction*tmp = make_call_function(tn, $3);
3763 | K_tan '(' expression ')'
3764 { perm_string tn = perm_string::literal("$tan");
3765 PECallFunction*tmp = make_call_function(tn, $3);
3770 | K_tanh '(' expression ')'
3771 { perm_string tn = perm_string::literal("$tanh");
3772 PECallFunction*tmp = make_call_function(tn, $3);
3777 /* These mathematical functions are conveniently expressed as unary
3778 and binary expressions. They behave much like unary/binary
3779 operators, even though they are parsed as functions. */
3781 | K_abs '(' expression ')'
3782 { PEUnary*tmp = new PEUnary('m', $3);
3787 | K_max '(' expression ',' expression ')'
3788 { PEBinary*tmp = new PEBinary('M', $3, $5);
3793 | K_min '(' expression ',' expression ')'
3794 { PEBinary*tmp = new PEBinary('m', $3, $5);
3799 /* Parenthesized expressions are primaries. */
3801 | '(' expr_mintypmax ')'
3804 /* Various kinds of concatenation expressions. */
3806 | '{' expression_list_proper '}'
3807 { PEConcat*tmp = new PEConcat(*$2);
3812 | '{' expression '{' expression_list_proper '}' '}'
3814 PEConcat*tmp = new PEConcat(*$4, rep);
3819 | '{' expression '{' expression_list_proper '}' error '}'
3821 PEConcat*tmp = new PEConcat(*$4, rep);
3825 yyerror(@5, "error: Syntax error between internal '}' "
3826 "and closing '}' of repeat concatenation.");
3831 { // This is the empty queue syntax.
3832 if (gn_system_verilog()) {
3833 list<PExpr*> empty_list;
3834 PEConcat*tmp = new PEConcat(empty_list);
3838 yyerror(@1, "error: Concatenations are not allowed to be empty.");
3843 /* Cast expressions are primaries */
3845 | expr_primary "'" '(' expression ')'
3847 if (gn_system_verilog()) {
3848 PECastSize*tmp = new PECastSize($1, base);
3852 yyerror(@1, "error: Size cast requires SystemVerilog.");
3857 | simple_type_or_string "'" '(' expression ')'
3859 if (gn_system_verilog()) {
3860 PECastType*tmp = new PECastType($1, base);
3864 yyerror(@1, "error: Type cast requires SystemVerilog.");
3869 /* Aggregate literals are primaries. */
3871 | assignment_pattern
3874 /* SystemVerilog supports streaming concatenation */
3875 | streaming_concatenation
3879 { PENull*tmp = new PENull;
3885 /* A function_item_list borrows the task_port_item run to match
3886 declarations of ports. We check later to make sure there are no
3887 output or inout ports actually used.
3889 The function_item is the same as tf_item_declaration. */
3890 function_item_list_opt
3891 : function_item_list { $$ = $1; }
3898 | function_item_list function_item
3901 vector<pform_tf_port_t>*tmp = $1;
3902 size_t s1 = tmp->size();
3903 tmp->resize(s1 + $2->size());
3904 for (size_t idx = 0 ; idx < $2->size() ; idx += 1)
3905 tmp->at(s1+idx) = $2->at(idx);
3917 : tf_port_declaration
3923 /* A gate_instance is a module instantiation or a built in part
3924 type. In any case, the gate has a set of connections to ports. */
3926 : IDENTIFIER '(' expression_list_with_nuls ')'
3927 { lgate*tmp = new lgate;
3930 tmp->file = @1.text;
3931 tmp->lineno = @1.first_line;
3936 | IDENTIFIER dimensions '(' expression_list_with_nuls ')'
3937 { lgate*tmp = new lgate;
3938 list<pform_range_t>*rng = $2;
3941 tmp->range = rng->front();
3943 assert(rng->empty());
3944 tmp->file = @1.text;
3945 tmp->lineno = @1.first_line;
3951 | '(' expression_list_with_nuls ')'
3952 { lgate*tmp = new lgate;
3955 tmp->file = @1.text;
3956 tmp->lineno = @1.first_line;
3960 /* Degenerate modules can have no ports. */
3962 | IDENTIFIER dimensions
3963 { lgate*tmp = new lgate;
3964 list<pform_range_t>*rng = $2;
3967 tmp->parms_by_name = 0;
3968 tmp->range = rng->front();
3970 assert(rng->empty());
3971 tmp->file = @1.text;
3972 tmp->lineno = @1.first_line;
3978 /* Modules can also take ports by port-name expressions. */
3980 | IDENTIFIER '(' port_name_list ')'
3981 { lgate*tmp = new lgate;
3984 tmp->parms_by_name = $3;
3985 tmp->file = @1.text;
3986 tmp->lineno = @1.first_line;
3991 | IDENTIFIER dimensions '(' port_name_list ')'
3992 { lgate*tmp = new lgate;
3993 list<pform_range_t>*rng = $2;
3996 tmp->parms_by_name = $4;
3997 tmp->range = rng->front();
3999 assert(rng->empty());
4000 tmp->file = @1.text;
4001 tmp->lineno = @1.first_line;
4007 | IDENTIFIER '(' error ')'
4008 { lgate*tmp = new lgate;
4011 tmp->parms_by_name = 0;
4012 tmp->file = @1.text;
4013 tmp->lineno = @1.first_line;
4014 yyerror(@2, "error: Syntax error in instance port "
4020 | IDENTIFIER dimensions '(' error ')'
4021 { lgate*tmp = new lgate;
4024 tmp->parms_by_name = 0;
4025 tmp->file = @1.text;
4026 tmp->lineno = @1.first_line;
4027 yyerror(@3, "error: Syntax error in instance port "
4035 : gate_instance_list ',' gate_instance
4036 { svector<lgate>*tmp1 = $1;
4038 svector<lgate>*out = new svector<lgate> (*tmp1, *tmp2);
4044 { svector<lgate>*tmp = new svector<lgate>(1);
4052 : K_and { $$ = PGBuiltin::AND; }
4053 | K_nand { $$ = PGBuiltin::NAND; }
4054 | K_or { $$ = PGBuiltin::OR; }
4055 | K_nor { $$ = PGBuiltin::NOR; }
4056 | K_xor { $$ = PGBuiltin::XOR; }
4057 | K_xnor { $$ = PGBuiltin::XNOR; }
4058 | K_buf { $$ = PGBuiltin::BUF; }
4059 | K_bufif0 { $$ = PGBuiltin::BUFIF0; }
4060 | K_bufif1 { $$ = PGBuiltin::BUFIF1; }
4061 | K_not { $$ = PGBuiltin::NOT; }
4062 | K_notif0 { $$ = PGBuiltin::NOTIF0; }
4063 | K_notif1 { $$ = PGBuiltin::NOTIF1; }
4067 : K_nmos { $$ = PGBuiltin::NMOS; }
4068 | K_rnmos { $$ = PGBuiltin::RNMOS; }
4069 | K_pmos { $$ = PGBuiltin::PMOS; }
4070 | K_rpmos { $$ = PGBuiltin::RPMOS; }
4071 | K_cmos { $$ = PGBuiltin::CMOS; }
4072 | K_rcmos { $$ = PGBuiltin::RCMOS; }
4073 | K_tran { $$ = PGBuiltin::TRAN; }
4074 | K_rtran { $$ = PGBuiltin::RTRAN; }
4075 | K_tranif0 { $$ = PGBuiltin::TRANIF0; }
4076 | K_tranif1 { $$ = PGBuiltin::TRANIF1; }
4077 | K_rtranif0 { $$ = PGBuiltin::RTRANIF0; }
4078 | K_rtranif1 { $$ = PGBuiltin::RTRANIF1; }
4082 /* A general identifier is a hierarchical name, with the right most
4083 name the base of the identifier. This rule builds up a
4084 hierarchical name from the left to the right, forming a list of
4087 hierarchy_identifier
4089 { $$ = new pform_name_t;
4090 $$->push_back(name_component_t(lex_strings.make($1)));
4093 | hierarchy_identifier '.' IDENTIFIER
4094 { pform_name_t * tmp = $1;
4095 tmp->push_back(name_component_t(lex_strings.make($3)));
4099 | hierarchy_identifier '[' expression ']'
4100 { pform_name_t * tmp = $1;
4101 name_component_t&tail = tmp->back();
4102 index_component_t itmp;
4103 itmp.sel = index_component_t::SEL_BIT;
4105 tail.index.push_back(itmp);
4108 | hierarchy_identifier '[' '$' ']'
4109 { pform_name_t * tmp = $1;
4110 name_component_t&tail = tmp->back();
4111 if (! gn_system_verilog()) {
4112 yyerror(@3, "error: Last element expression ($) "
4113 "requires SystemVerilog. Try enabling SystemVerilog.");
4115 index_component_t itmp;
4116 itmp.sel = index_component_t::SEL_BIT_LAST;
4119 tail.index.push_back(itmp);
4122 | hierarchy_identifier '[' expression ':' expression ']'
4123 { pform_name_t * tmp = $1;
4124 name_component_t&tail = tmp->back();
4125 index_component_t itmp;
4126 itmp.sel = index_component_t::SEL_PART;
4129 tail.index.push_back(itmp);
4132 | hierarchy_identifier '[' expression K_PO_POS expression ']'
4133 { pform_name_t * tmp = $1;
4134 name_component_t&tail = tmp->back();
4135 index_component_t itmp;
4136 itmp.sel = index_component_t::SEL_IDX_UP;
4139 tail.index.push_back(itmp);
4142 | hierarchy_identifier '[' expression K_PO_NEG expression ']'
4143 { pform_name_t * tmp = $1;
4144 name_component_t&tail = tmp->back();
4145 index_component_t itmp;
4146 itmp.sel = index_component_t::SEL_IDX_DO;
4149 tail.index.push_back(itmp);
4154 /* This is a list of identifiers. The result is a list of strings,
4155 each one of the identifiers in the list. These are simple,
4156 non-hierarchical names separated by ',' characters. */
4159 { $$ = list_from_identifier($1); }
4160 | list_of_identifiers ',' IDENTIFIER
4161 { $$ = list_from_identifier($1, $3); }
4164 list_of_port_identifiers
4165 : IDENTIFIER dimensions_opt
4166 { $$ = make_port_list($1, $2, 0); }
4167 | list_of_port_identifiers ',' IDENTIFIER dimensions_opt
4168 { $$ = make_port_list($1, $3, $4, 0); }
4171 list_of_variable_port_identifiers
4172 : IDENTIFIER dimensions_opt
4173 { $$ = make_port_list($1, $2, 0); }
4174 | IDENTIFIER dimensions_opt '=' expression
4175 { $$ = make_port_list($1, $2, $4); }
4176 | list_of_variable_port_identifiers ',' IDENTIFIER dimensions_opt
4177 { $$ = make_port_list($1, $3, $4, 0); }
4178 | list_of_variable_port_identifiers ',' IDENTIFIER dimensions_opt '=' expression
4179 { $$ = make_port_list($1, $3, $4, $6); }
4183 /* The list_of_ports and list_of_port_declarations rules are the
4184 port list formats for module ports. The list_of_ports_opt rule is
4185 only used by the module start rule.
4187 The first, the list_of_ports, is the 1364-1995 format, a list of
4188 port names, including .name() syntax.
4190 The list_of_port_declarations the 1364-2001 format, an in-line
4191 declaration of the ports.
4193 In both cases, the list_of_ports and list_of_port_declarations
4194 returns an array of Module::port_t* items that include the name
4195 of the port internally and externally. The actual creation of the
4196 nets/variables is done in the declaration, whether internal to
4197 the port list or in amongst the module items. */
4201 { vector<Module::port_t*>*tmp
4202 = new vector<Module::port_t*>(1);
4206 | list_of_ports ',' port_opt
4207 { vector<Module::port_t*>*tmp = $1;
4213 list_of_port_declarations
4215 { vector<Module::port_t*>*tmp
4216 = new vector<Module::port_t*>(1);
4220 | list_of_port_declarations ',' port_declaration
4221 { vector<Module::port_t*>*tmp = $1;
4225 | list_of_port_declarations ',' IDENTIFIER
4226 { Module::port_t*ptmp;
4227 perm_string name = lex_strings.make($3);
4228 ptmp = pform_module_port_reference(name, @3.text,
4230 vector<Module::port_t*>*tmp = $1;
4231 tmp->push_back(ptmp);
4233 /* Get the port declaration details, the port type
4234 and what not, from context data stored by the
4235 last port_declaration rule. */
4236 pform_module_define_port(@3, name,
4237 port_declaration_context.port_type,
4238 port_declaration_context.port_net_type,
4239 port_declaration_context.data_type, 0);
4243 | list_of_port_declarations ','
4245 yyerror(@2, "error: NULL port declarations are not "
4248 | list_of_port_declarations ';'
4250 yyerror(@2, "error: ';' is an invalid port declaration "
4256 : attribute_list_opt K_input net_type_opt data_type_or_implicit IDENTIFIER dimensions_opt
4257 { Module::port_t*ptmp;
4258 perm_string name = lex_strings.make($5);
4259 data_type_t*use_type = $4;
4260 if ($6) use_type = new uarray_type_t(use_type, $6);
4261 ptmp = pform_module_port_reference(name, @2.text, @2.first_line);
4262 pform_module_define_port(@2, name, NetNet::PINPUT, $3, use_type, $1);
4263 port_declaration_context.port_type = NetNet::PINPUT;
4264 port_declaration_context.port_net_type = $3;
4265 port_declaration_context.data_type = $4;
4269 | attribute_list_opt
4270 K_input K_wreal IDENTIFIER
4271 { Module::port_t*ptmp;
4272 perm_string name = lex_strings.make($4);
4273 ptmp = pform_module_port_reference(name, @2.text,
4275 real_type_t*real_type = new real_type_t(real_type_t::REAL);
4276 FILE_NAME(real_type, @3);
4277 pform_module_define_port(@2, name, NetNet::PINPUT,
4278 NetNet::WIRE, real_type, $1);
4279 port_declaration_context.port_type = NetNet::PINPUT;
4280 port_declaration_context.port_net_type = NetNet::WIRE;
4281 port_declaration_context.data_type = real_type;
4285 | attribute_list_opt K_inout net_type_opt data_type_or_implicit IDENTIFIER dimensions_opt
4286 { Module::port_t*ptmp;
4287 perm_string name = lex_strings.make($5);
4288 ptmp = pform_module_port_reference(name, @2.text, @2.first_line);
4289 pform_module_define_port(@2, name, NetNet::PINOUT, $3, $4, $1);
4290 port_declaration_context.port_type = NetNet::PINOUT;
4291 port_declaration_context.port_net_type = $3;
4292 port_declaration_context.data_type = $4;
4295 yyerror(@6, "sorry: Inout ports with unpacked dimensions not supported.");
4300 | attribute_list_opt
4301 K_inout K_wreal IDENTIFIER
4302 { Module::port_t*ptmp;
4303 perm_string name = lex_strings.make($4);
4304 ptmp = pform_module_port_reference(name, @2.text,
4306 real_type_t*real_type = new real_type_t(real_type_t::REAL);
4307 FILE_NAME(real_type, @3);
4308 pform_module_define_port(@2, name, NetNet::PINOUT,
4309 NetNet::WIRE, real_type, $1);
4310 port_declaration_context.port_type = NetNet::PINOUT;
4311 port_declaration_context.port_net_type = NetNet::WIRE;
4312 port_declaration_context.data_type = real_type;
4316 | attribute_list_opt K_output net_type_opt data_type_or_implicit IDENTIFIER dimensions_opt
4317 { Module::port_t*ptmp;
4318 perm_string name = lex_strings.make($5);
4319 data_type_t*use_dtype = $4;
4320 if ($6) use_dtype = new uarray_type_t(use_dtype, $6);
4321 NetNet::Type use_type = $3;
4322 if (use_type == NetNet::IMPLICIT) {
4323 if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($4)) {
4324 if (dtype->reg_flag)
4325 use_type = NetNet::REG;
4326 else if (dtype->implicit_flag)
4327 use_type = NetNet::IMPLICIT;
4329 use_type = NetNet::IMPLICIT_REG;
4331 // The SystemVerilog types that can show up as
4332 // output ports are implicitly (on the inside)
4333 // variables because "reg" is not valid syntax
4335 } else if (dynamic_cast<atom2_type_t*> ($4)) {
4336 use_type = NetNet::IMPLICIT_REG;
4337 } else if (dynamic_cast<struct_type_t*> ($4)) {
4338 use_type = NetNet::IMPLICIT_REG;
4339 } else if (enum_type_t*etype = dynamic_cast<enum_type_t*> ($4)) {
4340 if(etype->base_type == IVL_VT_LOGIC)
4341 use_type = NetNet::IMPLICIT_REG;
4344 ptmp = pform_module_port_reference(name, @2.text, @2.first_line);
4345 pform_module_define_port(@2, name, NetNet::POUTPUT, use_type, use_dtype, $1);
4346 port_declaration_context.port_type = NetNet::POUTPUT;
4347 port_declaration_context.port_net_type = use_type;
4348 port_declaration_context.data_type = $4;
4352 | attribute_list_opt
4353 K_output K_wreal IDENTIFIER
4354 { Module::port_t*ptmp;
4355 perm_string name = lex_strings.make($4);
4356 ptmp = pform_module_port_reference(name, @2.text,
4358 real_type_t*real_type = new real_type_t(real_type_t::REAL);
4359 FILE_NAME(real_type, @3);
4360 pform_module_define_port(@2, name, NetNet::POUTPUT,
4361 NetNet::WIRE, real_type, $1);
4362 port_declaration_context.port_type = NetNet::POUTPUT;
4363 port_declaration_context.port_net_type = NetNet::WIRE;
4364 port_declaration_context.data_type = real_type;
4368 | attribute_list_opt K_output net_type_opt data_type_or_implicit IDENTIFIER '=' expression
4369 { Module::port_t*ptmp;
4370 perm_string name = lex_strings.make($5);
4371 NetNet::Type use_type = $3;
4372 if (use_type == NetNet::IMPLICIT) {
4373 if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($4)) {
4374 if (dtype->reg_flag)
4375 use_type = NetNet::REG;
4377 use_type = NetNet::IMPLICIT_REG;
4379 use_type = NetNet::IMPLICIT_REG;
4382 ptmp = pform_module_port_reference(name, @2.text, @2.first_line);
4383 pform_module_define_port(@2, name, NetNet::POUTPUT, use_type, $4, $1);
4384 port_declaration_context.port_type = NetNet::PINOUT;
4385 port_declaration_context.port_net_type = use_type;
4386 port_declaration_context.data_type = $4;
4388 pform_make_var_init(@5, name, $7);
4398 : net_type { $$ = $1; }
4399 | { $$ = NetNet::IMPLICIT; }
4403 * The signed_opt rule will return "true" if K_signed is present,
4404 * for "false" otherwise. This rule corresponds to the declaration
4405 * defaults for reg/bit/logic.
4407 * The signed_unsigned_opt rule with match K_signed or K_unsigned
4408 * and return true or false as appropriate. The default is
4409 * "true". This corresponds to the declaration defaults for
4410 * byte/shortint/int/longint.
4413 : K_signed { $$ = true; }
4414 | K_unsigned { $$ = false; }
4419 : K_signed { $$ = true; }
4420 | K_unsigned { $$ = false; }
4425 * In some places we can take any of the 4 2-value atom-type
4426 * names. All the context needs to know if that type is its width.
4429 : K_byte { $$ = 8; }
4430 | K_shortint { $$ = 16; }
4431 | K_int { $$ = 32; }
4432 | K_longint { $$ = 64; }
4435 /* An lpvalue is the expression that can go on the left side of a
4436 procedural assignment. This rule handles only procedural
4437 assignments. It is more limited than the general expr_primary
4438 rule to reflect the rules for assignment l-values. */
4440 : hierarchy_identifier
4441 { PEIdent*tmp = pform_new_ident(*$1);
4447 | implicit_class_handle '.' hierarchy_identifier
4448 { pform_name_t*t_name = $1;
4449 while (!$3->empty()) {
4450 t_name->push_back($3->front());
4453 PEIdent*tmp = new PEIdent(*t_name);
4460 | '{' expression_list_proper '}'
4461 { PEConcat*tmp = new PEConcat(*$2);
4467 | streaming_concatenation
4468 { yyerror(@1, "sorry: streaming concatenation not supported in l-values.");
4474 /* Continuous assignments have a list of individual assignments. */
4477 : lpvalue '=' expression
4478 { list<PExpr*>*tmp = new list<PExpr*>;
4486 : cont_assign_list ',' cont_assign
4487 { list<PExpr*>*tmp = $1;
4488 tmp->splice(tmp->end(), *$3);
4496 /* This is the global structure of a module. A module is a start
4497 section, with optional ports, then an optional list of module
4498 items, and finally an end marker. */
4501 : attribute_list_opt module_start lifetime_opt IDENTIFIER
4502 { pform_startmodule(@2, $4, $2==K_program, $2==K_interface, $3, $1); }
4503 module_package_import_list_opt
4504 module_parameter_port_list_opt
4505 module_port_list_opt
4506 module_attribute_foreign ';'
4507 { pform_module_set_ports($8); }
4508 timeunits_declaration_opt
4509 { pform_set_scope_timescale(@2); }
4510 module_item_list_opt
4512 { Module::UCDriveType ucd;
4513 // The lexor detected `unconnected_drive directives and
4514 // marked what it found in the uc_drive variable. Use that
4515 // to generate a UCD flag for the module.
4519 ucd = Module::UCD_NONE;
4522 ucd = Module::UCD_PULL0;
4525 ucd = Module::UCD_PULL1;
4528 // Check that program/endprogram and module/endmodule
4533 yyerror(@15, "error: module not closed by endmodule.");
4536 yyerror(@15, "error: program not closed by endprogram.");
4539 yyerror(@15, "error: interface not closed by endinterface.");
4545 pform_endmodule($4, in_celldefine, ucd);
4548 { // Last step: check any closing name. This is done late so
4549 // that the parser can look ahead to detect the present
4550 // endlabel_opt but still have the pform_endmodule() called
4551 // early enough that the lexor can know we are outside the
4554 if (strcmp($4,$17) != 0) {
4557 yyerror(@17, "error: End label doesn't match "
4561 yyerror(@17, "error: End label doesn't match "
4565 yyerror(@17, "error: End label doesn't match "
4572 if (($2 == K_module) && (! gn_system_verilog())) {
4573 yyerror(@8, "error: Module end labels require "
4582 /* Modules start with a module/macromodule, program, or interface
4583 keyword, and end with a endmodule, endprogram, or endinterface
4584 keyword. The syntax for modules programs, and interfaces is
4585 almost identical, so let semantics sort out the differences. */
4587 : K_module { $$ = K_module; }
4588 | K_macromodule { $$ = K_module; }
4589 | K_program { $$ = K_program; }
4590 | K_interface { $$ = K_interface; }
4594 : K_endmodule { $$ = K_module; }
4595 | K_endprogram { $$ = K_program; }
4596 | K_endinterface { $$ = K_interface; }
4600 : ':' IDENTIFIER { $$ = $2; }
4604 module_attribute_foreign
4605 : K_PSTAR IDENTIFIER K_integer IDENTIFIER '=' STRING ';' K_STARP { $$ = 0; }
4609 module_port_list_opt
4610 : '(' list_of_ports ')' { $$ = $2; }
4611 | '(' list_of_port_declarations ')' { $$ = $2; }
4614 { yyerror(@2, "Errors in port declarations.");
4620 /* Module declarations include optional ANSI style module parameter
4621 ports. These are simply advance ways to declare parameters, so
4622 that the port declarations may use them. */
4623 module_parameter_port_list_opt
4625 | '#' '(' module_parameter_port_list ')'
4628 module_parameter_port_list
4629 : K_parameter param_type parameter_assign
4630 | module_parameter_port_list ',' parameter_assign
4631 | module_parameter_port_list ',' K_parameter param_type parameter_assign
4636 /* Modules can contain further sub-module definitions. */
4639 | attribute_list_opt net_type data_type_or_implicit delay3_opt net_variable_list ';'
4641 { data_type_t*data_type = $3;
4642 if (data_type == 0) {
4643 data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
4644 FILE_NAME(data_type, @2);
4646 pform_set_data_type(@2, data_type, $5, $2, $1);
4648 yyerror(@2, "sorry: net delays not supported.");
4654 | attribute_list_opt K_wreal delay3 net_variable_list ';'
4655 { real_type_t*tmpt = new real_type_t(real_type_t::REAL);
4656 pform_set_data_type(@2, tmpt, $4, NetNet::WIRE, $1);
4658 yyerror(@3, "sorry: net delays not supported.");
4664 | attribute_list_opt K_wreal net_variable_list ';'
4665 { real_type_t*tmpt = new real_type_t(real_type_t::REAL);
4666 pform_set_data_type(@2, tmpt, $3, NetNet::WIRE, $1);
4670 /* Very similar to the rule above, but this takes a list of
4671 net_decl_assigns, which are <name> = <expr> assignment
4674 | attribute_list_opt net_type data_type_or_implicit delay3_opt net_decl_assigns ';'
4675 { data_type_t*data_type = $3;
4676 if (data_type == 0) {
4677 data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
4678 FILE_NAME(data_type, @2);
4680 pform_makewire(@2, $4, str_strength, $5, $2, data_type);
4682 yywarn(@2, "Attributes are not supported on net declaration "
4683 "assignments and will be discarded.");
4688 /* This form doesn't have the range, but does have strengths. This
4689 gives strength to the assignment drivers. */
4691 | attribute_list_opt net_type data_type_or_implicit drive_strength net_decl_assigns ';'
4692 { data_type_t*data_type = $3;
4693 if (data_type == 0) {
4694 data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
4695 FILE_NAME(data_type, @2);
4697 pform_makewire(@2, 0, $4, $5, $2, data_type);
4699 yywarn(@2, "Attributes are not supported on net declaration "
4700 "assignments and will be discarded.");
4705 | attribute_list_opt K_wreal net_decl_assigns ';'
4706 { real_type_t*data_type = new real_type_t(real_type_t::REAL);
4707 pform_makewire(@2, 0, str_strength, $3, NetNet::WIRE, data_type);
4709 yywarn(@2, "Attributes are not supported on net declaration "
4710 "assignments and will be discarded.");
4715 | K_trireg charge_strength_opt dimensions_opt delay3_opt list_of_identifiers ';'
4716 { yyerror(@1, "sorry: trireg nets not supported.");
4722 /* The next two rules handle port declarations that include a net type, e.g.
4723 input wire signed [h:l] <list>;
4724 This creates the wire and sets the port type all at once. */
4726 | attribute_list_opt port_direction net_type data_type_or_implicit list_of_port_identifiers ';'
4727 { pform_module_define_port(@2, $5, $2, $3, $4, $1); }
4729 | attribute_list_opt port_direction K_wreal list_of_port_identifiers ';'
4730 { real_type_t*real_type = new real_type_t(real_type_t::REAL);
4731 pform_module_define_port(@2, $4, $2, NetNet::WIRE, real_type, $1);
4734 /* The next three rules handle port declarations that include a variable
4736 output reg signed [h:l] <list>;
4737 and also handle incomplete port declarations, e.g.
4738 input signed [h:l] <list>;
4740 | attribute_list_opt K_inout data_type_or_implicit list_of_port_identifiers ';'
4741 { NetNet::Type use_type = $3 ? NetNet::IMPLICIT : NetNet::NONE;
4742 if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($3)) {
4743 if (dtype->implicit_flag)
4744 use_type = NetNet::NONE;
4746 if (use_type == NetNet::NONE)
4747 pform_set_port_type(@2, $4, NetNet::PINOUT, $3, $1);
4749 pform_module_define_port(@2, $4, NetNet::PINOUT, use_type, $3, $1);
4752 | attribute_list_opt K_input data_type_or_implicit list_of_port_identifiers ';'
4753 { NetNet::Type use_type = $3 ? NetNet::IMPLICIT : NetNet::NONE;
4754 if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($3)) {
4755 if (dtype->implicit_flag)
4756 use_type = NetNet::NONE;
4758 if (use_type == NetNet::NONE)
4759 pform_set_port_type(@2, $4, NetNet::PINPUT, $3, $1);
4761 pform_module_define_port(@2, $4, NetNet::PINPUT, use_type, $3, $1);
4764 | attribute_list_opt K_output data_type_or_implicit list_of_variable_port_identifiers ';'
4765 { NetNet::Type use_type = $3 ? NetNet::IMPLICIT : NetNet::NONE;
4766 if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($3)) {
4767 if (dtype->implicit_flag)
4768 use_type = NetNet::NONE;
4769 else if (dtype->reg_flag)
4770 use_type = NetNet::REG;
4772 use_type = NetNet::IMPLICIT_REG;
4774 // The SystemVerilog types that can show up as
4775 // output ports are implicitly (on the inside)
4776 // variables because "reg" is not valid syntax
4778 } else if (dynamic_cast<atom2_type_t*> ($3)) {
4779 use_type = NetNet::IMPLICIT_REG;
4780 } else if (dynamic_cast<struct_type_t*> ($3)) {
4781 use_type = NetNet::IMPLICIT_REG;
4782 } else if (enum_type_t*etype = dynamic_cast<enum_type_t*> ($3)) {
4783 if(etype->base_type == IVL_VT_LOGIC)
4784 use_type = NetNet::IMPLICIT_REG;
4786 if (use_type == NetNet::NONE)
4787 pform_set_port_type(@2, $4, NetNet::POUTPUT, $3, $1);
4789 pform_module_define_port(@2, $4, NetNet::POUTPUT, use_type, $3, $1);
4792 | attribute_list_opt port_direction net_type data_type_or_implicit error ';'
4793 { yyerror(@2, "error: Invalid variable list in port declaration.");
4799 | attribute_list_opt K_inout data_type_or_implicit error ';'
4800 { yyerror(@2, "error: Invalid variable list in port declaration.");
4806 | attribute_list_opt K_input data_type_or_implicit error ';'
4807 { yyerror(@2, "error: Invalid variable list in port declaration.");
4813 | attribute_list_opt K_output data_type_or_implicit error ';'
4814 { yyerror(@2, "error: Invalid variable list in port declaration.");
4820 /* Maybe this is a discipline declaration? If so, then the lexor
4821 will see the discipline name as an identifier. We match it to the
4822 discipline or type name semantically. */
4823 | DISCIPLINE_IDENTIFIER list_of_identifiers ';'
4824 { pform_attach_discipline(@1, $1, $2); }
4826 /* block_item_decl rule is shared with task blocks and named
4827 begin/end. Careful to pass attributes to the block_item_decl. */
4829 | attribute_list_opt { attributes_in_context = $1; } block_item_decl
4830 { delete attributes_in_context;
4831 attributes_in_context = 0;
4837 { if (pform_in_interface())
4838 yyerror(@1, "error: Parameter overrides are not allowed "
4841 defparam_assign_list ';'
4843 /* Most gate types have an optional drive strength and optional
4844 two/three-value delay. These rules handle the different cases.
4845 We check that the actual number of delays is correct later. */
4847 | attribute_list_opt gatetype gate_instance_list ';'
4848 { pform_makegates(@2, $2, str_strength, 0, $3, $1); }
4850 | attribute_list_opt gatetype delay3 gate_instance_list ';'
4851 { pform_makegates(@2, $2, str_strength, $3, $4, $1); }
4853 | attribute_list_opt gatetype drive_strength gate_instance_list ';'
4854 { pform_makegates(@2, $2, $3, 0, $4, $1); }
4856 | attribute_list_opt gatetype drive_strength delay3 gate_instance_list ';'
4857 { pform_makegates(@2, $2, $3, $4, $5, $1); }
4859 /* The switch type gates do not support a strength. */
4860 | attribute_list_opt switchtype gate_instance_list ';'
4861 { pform_makegates(@2, $2, str_strength, 0, $3, $1); }
4863 | attribute_list_opt switchtype delay3 gate_instance_list ';'
4864 { pform_makegates(@2, $2, str_strength, $3, $4, $1); }
4866 /* Pullup and pulldown devices cannot have delays, and their
4867 strengths are limited. */
4869 | K_pullup gate_instance_list ';'
4870 { pform_makegates(@1, PGBuiltin::PULLUP, pull_strength, 0, $2, 0); }
4871 | K_pulldown gate_instance_list ';'
4872 { pform_makegates(@1, PGBuiltin::PULLDOWN, pull_strength, 0, $2, 0); }
4874 | K_pullup '(' dr_strength1 ')' gate_instance_list ';'
4875 { pform_makegates(@1, PGBuiltin::PULLUP, $3, 0, $5, 0); }
4877 | K_pullup '(' dr_strength1 ',' dr_strength0 ')' gate_instance_list ';'
4878 { pform_makegates(@1, PGBuiltin::PULLUP, $3, 0, $7, 0); }
4880 | K_pullup '(' dr_strength0 ',' dr_strength1 ')' gate_instance_list ';'
4881 { pform_makegates(@1, PGBuiltin::PULLUP, $5, 0, $7, 0); }
4883 | K_pulldown '(' dr_strength0 ')' gate_instance_list ';'
4884 { pform_makegates(@1, PGBuiltin::PULLDOWN, $3, 0, $5, 0); }
4886 | K_pulldown '(' dr_strength1 ',' dr_strength0 ')' gate_instance_list ';'
4887 { pform_makegates(@1, PGBuiltin::PULLDOWN, $5, 0, $7, 0); }
4889 | K_pulldown '(' dr_strength0 ',' dr_strength1 ')' gate_instance_list ';'
4890 { pform_makegates(@1, PGBuiltin::PULLDOWN, $3, 0, $7, 0); }
4892 /* This rule handles instantiations of modules and user defined
4893 primitives. These devices to not have delay lists or strengths,
4894 but then can have parameter lists. */
4896 | attribute_list_opt
4897 IDENTIFIER parameter_value_opt gate_instance_list ';'
4898 { perm_string tmp1 = lex_strings.make($2);
4899 pform_make_modgates(@2, tmp1, $3, $4, $1);
4903 | attribute_list_opt
4904 IDENTIFIER parameter_value_opt error ';'
4905 { yyerror(@2, "error: Invalid module instantiation");
4910 /* Continuous assignment can have an optional drive strength, then
4911 an optional delay3 that applies to all the assignments in the
4912 cont_assign_list. */
4914 | K_assign drive_strength_opt delay3_opt cont_assign_list ';'
4915 { pform_make_pgassign_list($4, $3, $2, @1.text, @1.first_line); }
4917 /* Always and initial items are behavioral processes. */
4919 | attribute_list_opt K_always statement_item
4920 { PProcess*tmp = pform_make_behavior(IVL_PR_ALWAYS, $3, $1);
4923 | attribute_list_opt K_always_comb statement_item
4924 { PProcess*tmp = pform_make_behavior(IVL_PR_ALWAYS_COMB, $3, $1);
4927 | attribute_list_opt K_always_ff statement_item
4928 { PProcess*tmp = pform_make_behavior(IVL_PR_ALWAYS_FF, $3, $1);
4931 | attribute_list_opt K_always_latch statement_item
4932 { PProcess*tmp = pform_make_behavior(IVL_PR_ALWAYS_LATCH, $3, $1);
4935 | attribute_list_opt K_initial statement_item
4936 { PProcess*tmp = pform_make_behavior(IVL_PR_INITIAL, $3, $1);
4939 | attribute_list_opt K_final statement_item
4940 { PProcess*tmp = pform_make_behavior(IVL_PR_FINAL, $3, $1);
4944 | attribute_list_opt K_analog analog_statement
4945 { pform_make_analog_behavior(@2, IVL_PR_ALWAYS, $3); }
4947 | attribute_list_opt assertion_item
4949 | timeunits_declaration
4955 | function_declaration
4957 /* A generate region can contain further module items. Actually, it
4958 is supposed to be limited to certain kinds of module items, but
4959 the semantic tests will check that for us. Do check that the
4960 generate/endgenerate regions do not nest. Generate schemes nest,
4961 but generate regions do not. */
4963 | K_generate generate_item_list_opt K_endgenerate
4964 { // Test for bad nesting. I understand it, but it is illegal.
4965 if (pform_parent_generate()) {
4966 cerr << @1 << ": error: Generate/endgenerate regions cannot nest." << endl;
4967 cerr << @1 << ": : Try removing optional generate/endgenerate keywords," << endl;
4968 cerr << @1 << ": : or move them to surround the parent generate scheme." << endl;
4973 | K_genvar list_of_identifiers ';'
4974 { pform_genvars(@1, $2); }
4976 | K_for '(' IDENTIFIER '=' expression ';'
4978 IDENTIFIER '=' expression ')'
4979 { pform_start_generate_for(@1, $3, $5, $7, $9, $11); }
4981 { pform_endgenerate(); }
4986 { pform_start_generate_else(@1); }
4988 { pform_endgenerate(); }
4991 generate_block_opt %prec less_than_K_else
4992 { pform_endgenerate(); }
4994 | K_case '(' expression ')'
4995 { pform_start_generate_case(@1, $3); }
4998 { pform_endgenerate(); }
5000 | modport_declaration
5002 | package_import_declaration
5004 /* 1364-2001 and later allow specparam declarations outside specify blocks. */
5006 | attribute_list_opt K_specparam
5007 { if (pform_in_interface())
5008 yyerror(@1, "error: specparam declarations are not allowed "
5013 /* specify blocks are parsed but ignored. */
5016 { if (pform_in_interface())
5017 yyerror(@1, "error: specify blocks are not allowed "
5020 specify_item_list_opt K_endspecify
5022 | K_specify error K_endspecify
5023 { yyerror(@1, "error: syntax error in specify block");
5027 /* These rules match various errors that the user can type into
5028 module items. These rules try to catch them at a point where a
5029 reasonable error message can be produced. */
5032 { yyerror(@2, "error: invalid module item.");
5036 | K_assign error '=' expression ';'
5037 { yyerror(@1, "error: syntax error in left side "
5038 "of continuous assignment.");
5042 | K_assign error ';'
5043 { yyerror(@1, "error: syntax error in "
5044 "continuous assignment");
5048 | K_function error K_endfunction endlabel_opt
5049 { yyerror(@1, "error: I give up on this "
5050 "function definition.");
5052 if (!gn_system_verilog()) {
5053 yyerror(@4, "error: Function end names require "
5061 /* These rules are for the Icarus Verilog specific $attribute
5062 extensions. Then catch the parameters of the $attribute keyword. */
5064 | KK_attribute '(' IDENTIFIER ',' STRING ',' STRING ')' ';'
5065 { perm_string tmp3 = lex_strings.make($3);
5066 perm_string tmp5 = lex_strings.make($5);
5067 pform_set_attrib(tmp3, tmp5, $7);
5071 | KK_attribute '(' error ')' ';'
5072 { yyerror(@1, "error: Malformed $attribute parameter list."); }
5077 : module_item_list module_item
5081 module_item_list_opt
5086 generate_if : K_if '(' expression ')' { pform_start_generate_if(@1, $3); } ;
5089 : generate_case_items generate_case_item
5090 | generate_case_item
5094 : expression_list_proper ':' { pform_generate_case_item(@1, $1); } generate_block_opt
5095 { pform_endgenerate(); }
5096 | K_default ':' { pform_generate_case_item(@1, 0); } generate_block_opt
5097 { pform_endgenerate(); }
5102 /* Handle some anachronistic syntax cases. */
5103 | K_begin generate_item_list_opt K_end
5104 { /* Detect and warn about anachronistic begin/end use */
5105 if (generation_flag > GN_VER2001 && warn_anachronisms) {
5107 cerr << @1 << ": warning: Anachronistic use of begin/end to surround generate schemes." << endl;
5110 | K_begin ':' IDENTIFIER {
5111 pform_start_generate_nblock(@1, $3);
5112 } generate_item_list_opt K_end
5113 { /* Detect and warn about anachronistic named begin/end use */
5114 if (generation_flag > GN_VER2001 && warn_anachronisms) {
5116 cerr << @1 << ": warning: Anachronistic use of named begin/end to surround generate schemes." << endl;
5118 pform_endgenerate();
5123 : generate_item_list generate_item
5127 generate_item_list_opt
5128 : generate_item_list
5132 /* A generate block is the thing within a generate scheme. It may be
5133 a single module item, an anonymous block of module items, or a
5134 named module item. In all cases, the meat is in the module items
5135 inside, and the processing is done by the module_item rules. We
5136 only need to take note here of the scope name, if any. */
5140 | K_begin generate_item_list_opt K_end
5141 | K_begin ':' IDENTIFIER generate_item_list_opt K_end endlabel_opt
5142 { pform_generate_block_name($3);
5144 if (strcmp($3,$6) != 0) {
5145 yyerror(@6, "error: End label doesn't match "
5148 if (! gn_system_verilog()) {
5149 yyerror(@6, "error: Begin end labels require "
5158 generate_block_opt : generate_block | ';' ;
5161 /* A net declaration assignment allows the programmer to combine the
5162 net declaration and the continuous assignment into a single
5165 Note that the continuous assignment statement is generated as a
5166 side effect, and all I pass up is the name of the l-value. */
5169 : IDENTIFIER '=' expression
5170 { net_decl_assign_t*tmp = new net_decl_assign_t;
5172 tmp->name = lex_strings.make($1);
5180 : net_decl_assigns ',' net_decl_assign
5181 { net_decl_assign_t*tmp = $1;
5182 $3->next = tmp->next;
5192 : K_logic { $$ = IVL_VT_LOGIC; }
5193 | K_bool { $$ = IVL_VT_BOOL; /* Icarus misc */}
5194 | K_bit { $$ = IVL_VT_BOOL; /* IEEE1800 / IEEE1364-2009 */}
5199 | { $$ = IVL_VT_NO_TYPE; }
5203 : K_wire { $$ = NetNet::WIRE; }
5204 | K_tri { $$ = NetNet::TRI; }
5205 | K_tri1 { $$ = NetNet::TRI1; }
5206 | K_supply0 { $$ = NetNet::SUPPLY0; }
5207 | K_wand { $$ = NetNet::WAND; }
5208 | K_triand { $$ = NetNet::TRIAND; }
5209 | K_tri0 { $$ = NetNet::TRI0; }
5210 | K_supply1 { $$ = NetNet::SUPPLY1; }
5211 | K_wor { $$ = NetNet::WOR; }
5212 | K_trior { $$ = NetNet::TRIOR; }
5213 | K_wone { $$ = NetNet::UNRESOLVED_WIRE;
5214 cerr << @1.text << ":" << @1.first_line << ": warning: "
5215 "'wone' is deprecated, please use 'uwire' "
5218 | K_uwire { $$ = NetNet::UNRESOLVED_WIRE; }
5222 : bit_logic_opt unsigned_signed_opt dimensions_opt
5223 { param_active_range = $3;
5224 param_active_signed = $2;
5225 if (($1 == IVL_VT_NO_TYPE) && ($3 != 0))
5226 param_active_type = IVL_VT_LOGIC;
5228 param_active_type = $1;
5231 { param_active_range = make_range_from_width(integer_width);
5232 param_active_signed = true;
5233 param_active_type = IVL_VT_LOGIC;
5236 { param_active_range = make_range_from_width(64);
5237 param_active_signed = false;
5238 param_active_type = IVL_VT_LOGIC;
5241 { param_active_range = 0;
5242 param_active_signed = true;
5243 param_active_type = IVL_VT_REAL;
5246 { param_active_range = make_range_from_width($1);
5247 param_active_signed = true;
5248 param_active_type = IVL_VT_BOOL;
5251 { pform_set_param_from_type(@1, $1.type, $1.text, param_active_range,
5252 param_active_signed, param_active_type);
5257 /* parameter and localparam assignment lists are broken into
5258 separate BNF so that I can call slightly different parameter
5259 handling code. localparams parse the same as parameters, they
5260 just behave differently when someone tries to override them. */
5262 parameter_assign_list
5264 | parameter_assign_list ',' parameter_assign
5267 localparam_assign_list
5269 | localparam_assign_list ',' localparam_assign
5273 : IDENTIFIER '=' expression parameter_value_ranges_opt
5275 pform_set_parameter(@1, lex_strings.make($1), param_active_type,
5276 param_active_signed, param_active_range, tmp, $4);
5282 : IDENTIFIER '=' expression
5284 pform_set_localparam(@1, lex_strings.make($1), param_active_type,
5285 param_active_signed, param_active_range, tmp);
5290 parameter_value_ranges_opt : parameter_value_ranges { $$ = $1; } | { $$ = 0; } ;
5292 parameter_value_ranges
5293 : parameter_value_ranges parameter_value_range
5294 { $$ = $2; $$->next = $1; }
5295 | parameter_value_range
5296 { $$ = $1; $$->next = 0; }
5299 parameter_value_range
5300 : from_exclude '[' value_range_expression ':' value_range_expression ']'
5301 { $$ = pform_parameter_value_range($1, false, $3, false, $5); }
5302 | from_exclude '[' value_range_expression ':' value_range_expression ')'
5303 { $$ = pform_parameter_value_range($1, false, $3, true, $5); }
5304 | from_exclude '(' value_range_expression ':' value_range_expression ']'
5305 { $$ = pform_parameter_value_range($1, true, $3, false, $5); }
5306 | from_exclude '(' value_range_expression ':' value_range_expression ')'
5307 { $$ = pform_parameter_value_range($1, true, $3, true, $5); }
5308 | K_exclude expression
5309 { $$ = pform_parameter_value_range(true, false, $2, false, $2); }
5312 value_range_expression
5313 : expression { $$ = $1; }
5315 | '+' K_inf { $$ = 0; }
5316 | '-' K_inf { $$ = 0; }
5319 from_exclude : K_from { $$ = false; } | K_exclude { $$ = true; } ;
5321 /* The parameters of a module instance can be overridden by writing
5322 a list of expressions in a syntax much like a delay list. (The
5323 difference being the list can have any length.) The pform that
5324 attaches the expression list to the module checks that the
5325 expressions are constant.
5327 Although the BNF in IEEE1364-1995 implies that parameter value
5328 lists must be in parentheses, in practice most compilers will
5329 accept simple expressions outside of parentheses if there is only
5330 one value, so I'll accept simple numbers here. This also catches
5331 the case of a UDP with a single delay value, so we need to accept
5332 real values as well as decimal ones.
5334 The parameter value by name syntax is OVI enhancement BTF-B06 as
5335 approved by WG1364 on 6/28/1998. */
5338 : '#' '(' expression_list_with_nuls ')'
5339 { struct parmvalue_t*tmp = new struct parmvalue_t;
5344 | '#' '(' parameter_value_byname_list ')'
5345 { struct parmvalue_t*tmp = new struct parmvalue_t;
5352 PENumber*tmp = new PENumber($2);
5355 struct parmvalue_t*lst = new struct parmvalue_t;
5356 lst->by_order = new list<PExpr*>;
5357 lst->by_order->push_back(tmp);
5364 PEFNumber*tmp = new PEFNumber($2);
5367 struct parmvalue_t*lst = new struct parmvalue_t;
5368 lst->by_order = new list<PExpr*>;
5369 lst->by_order->push_back(tmp);
5374 { yyerror(@1, "error: syntax error in parameter value "
5375 "assignment list.");
5382 parameter_value_byname
5383 : '.' IDENTIFIER '(' expression ')'
5384 { named_pexpr_t*tmp = new named_pexpr_t;
5385 tmp->name = lex_strings.make($2);
5390 | '.' IDENTIFIER '(' ')'
5391 { named_pexpr_t*tmp = new named_pexpr_t;
5392 tmp->name = lex_strings.make($2);
5399 parameter_value_byname_list
5400 : parameter_value_byname
5401 { list<named_pexpr_t>*tmp = new list<named_pexpr_t>;
5402 tmp->push_back(*$1);
5406 | parameter_value_byname_list ',' parameter_value_byname
5407 { list<named_pexpr_t>*tmp = $1;
5408 tmp->push_back(*$3);
5415 /* The port (of a module) is a fairly complex item. Each port is
5416 handled as a Module::port_t object. A simple port reference has a
5417 name and a PExpr object, but more complex constructs are possible
5418 where the name can be attached to a list of PWire objects.
5420 The port_reference returns a Module::port_t, and so does the
5421 port_reference_list. The port_reference_list may have built up a
5422 list of PWires in the port_t object, but it is still a single
5423 Module::port_t object.
5425 The port rule below takes the built up Module::port_t object and
5426 tweaks its name as needed. */
5432 /* This syntax attaches an external name to the port reference so
5433 that the caller can bind by name to non-trivial port
5434 references. The port_t object gets its PWire from the
5435 port_reference, but its name from the IDENTIFIER. */
5437 | '.' IDENTIFIER '(' port_reference ')'
5438 { Module::port_t*tmp = $4;
5439 tmp->name = lex_strings.make($2);
5444 /* A port can also be a concatenation of port references. In this
5445 case the port does not have a name available to the outside, only
5446 positional parameter passing is possible here. */
5448 | '{' port_reference_list '}'
5449 { Module::port_t*tmp = $2;
5450 tmp->name = perm_string();
5454 /* This attaches a name to a port reference concatenation list so
5455 that parameter passing be name is possible. */
5457 | '.' IDENTIFIER '(' '{' port_reference_list '}' ')'
5458 { Module::port_t*tmp = $5;
5459 tmp->name = lex_strings.make($2);
5470 /* The port_name rule is used with a module is being *instantiated*,
5471 and not when it is being declared. See the port rule if you are
5472 looking for the ports of a module declaration. */
5475 : '.' IDENTIFIER '(' expression ')'
5476 { named_pexpr_t*tmp = new named_pexpr_t;
5477 tmp->name = lex_strings.make($2);
5482 | '.' IDENTIFIER '(' error ')'
5483 { yyerror(@3, "error: invalid port connection expression.");
5484 named_pexpr_t*tmp = new named_pexpr_t;
5485 tmp->name = lex_strings.make($2);
5490 | '.' IDENTIFIER '(' ')'
5491 { named_pexpr_t*tmp = new named_pexpr_t;
5492 tmp->name = lex_strings.make($2);
5498 { named_pexpr_t*tmp = new named_pexpr_t;
5499 tmp->name = lex_strings.make($2);
5500 tmp->parm = new PEIdent(lex_strings.make($2), true);
5501 FILE_NAME(tmp->parm, @1);
5506 { named_pexpr_t*tmp = new named_pexpr_t;
5507 tmp->name = lex_strings.make("*");
5514 : port_name_list ',' port_name
5515 { list<named_pexpr_t>*tmp = $1;
5516 tmp->push_back(*$3);
5521 { list<named_pexpr_t>*tmp = new list<named_pexpr_t>;
5522 tmp->push_back(*$1);
5529 /* A port reference is an internal (to the module) name of the port,
5530 possibly with a part of bit select to attach it to specific bits
5531 of a signal fully declared inside the module.
5533 The parser creates a PEIdent for every port reference, even if the
5534 signal is bound to different ports. The elaboration figures out
5535 the mess that this creates. The port_reference (and the
5536 port_reference_list below) puts the port reference PEIdent into the
5537 port_t object to pass it up to the module declaration code. */
5542 { Module::port_t*ptmp;
5543 perm_string name = lex_strings.make($1);
5544 ptmp = pform_module_port_reference(name, @1.text, @1.first_line);
5549 | IDENTIFIER '[' expression ':' expression ']'
5550 { index_component_t itmp;
5551 itmp.sel = index_component_t::SEL_PART;
5555 name_component_t ntmp (lex_strings.make($1));
5556 ntmp.index.push_back(itmp);
5559 pname.push_back(ntmp);
5561 PEIdent*wtmp = new PEIdent(pname);
5562 FILE_NAME(wtmp, @1);
5564 Module::port_t*ptmp = new Module::port_t;
5565 ptmp->name = perm_string();
5566 ptmp->expr.push_back(wtmp);
5572 | IDENTIFIER '[' expression ']'
5573 { index_component_t itmp;
5574 itmp.sel = index_component_t::SEL_BIT;
5578 name_component_t ntmp (lex_strings.make($1));
5579 ntmp.index.push_back(itmp);
5582 pname.push_back(ntmp);
5584 PEIdent*tmp = new PEIdent(pname);
5587 Module::port_t*ptmp = new Module::port_t;
5588 ptmp->name = perm_string();
5589 ptmp->expr.push_back(tmp);
5594 | IDENTIFIER '[' error ']'
5595 { yyerror(@1, "error: invalid port bit select");
5596 Module::port_t*ptmp = new Module::port_t;
5597 PEIdent*wtmp = new PEIdent(lex_strings.make($1));
5598 FILE_NAME(wtmp, @1);
5599 ptmp->name = lex_strings.make($1);
5600 ptmp->expr.push_back(wtmp);
5610 | port_reference_list ',' port_reference
5611 { Module::port_t*tmp = $1;
5612 append(tmp->expr, $3->expr);
5618 /* The range is a list of variable dimensions. */
5621 | dimensions { $$ = $1; }
5625 : variable_dimension
5627 | dimensions variable_dimension
5628 { list<pform_range_t> *tmp = $1;
5630 tmp->splice(tmp->end(), *$2);
5637 /* The register_variable rule is matched only when I am parsing
5638 variables in a "reg" definition. I therefore know that I am
5639 creating registers and I do not need to let the containing rule
5640 handle it. The register variable list simply packs them together
5641 so that bit ranges can be assigned. */
5643 : IDENTIFIER dimensions_opt
5644 { perm_string name = lex_strings.make($1);
5645 pform_makewire(@1, name, NetNet::REG,
5646 NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
5647 pform_set_reg_idx(name, $2);
5650 | IDENTIFIER dimensions_opt '=' expression
5651 { if (pform_peek_scope()->var_init_needs_explicit_lifetime()
5652 && (var_lifetime == LexicalScope::INHERITED)) {
5653 cerr << @3 << ": warning: Static variable initialization requires "
5654 "explicit lifetime in this context." << endl;
5657 perm_string name = lex_strings.make($1);
5658 pform_makewire(@1, name, NetNet::REG,
5659 NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
5660 pform_set_reg_idx(name, $2);
5661 pform_make_var_init(@1, name, $4);
5666 register_variable_list
5668 { list<perm_string>*tmp = new list<perm_string>;
5669 tmp->push_back(lex_strings.make($1));
5673 | register_variable_list ',' register_variable
5674 { list<perm_string>*tmp = $1;
5675 tmp->push_back(lex_strings.make($3));
5682 : IDENTIFIER dimensions_opt
5683 { perm_string name = lex_strings.make($1);
5684 pform_makewire(@1, name, NetNet::IMPLICIT,
5685 NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
5686 pform_set_reg_idx(name, $2);
5693 { list<perm_string>*tmp = new list<perm_string>;
5694 tmp->push_back(lex_strings.make($1));
5698 | net_variable_list ',' net_variable
5699 { list<perm_string>*tmp = $1;
5700 tmp->push_back(lex_strings.make($3));
5707 : IDENTIFIER dimensions_opt
5709 yyerror(@2, "sorry: event arrays are not supported.");
5718 { $$ = list_from_identifier($1); }
5719 | event_variable_list ',' event_variable
5720 { $$ = list_from_identifier($1, $3); }
5724 : K_specparam specparam_decl ';'
5725 | specify_simple_path_decl ';'
5726 { pform_module_specify_path($1);
5728 | specify_edge_path_decl ';'
5729 { pform_module_specify_path($1);
5731 | K_if '(' expression ')' specify_simple_path_decl ';'
5732 { PSpecPath*tmp = $5;
5734 tmp->conditional = true;
5735 tmp->condition = $3;
5737 pform_module_specify_path(tmp);
5739 | K_if '(' expression ')' specify_edge_path_decl ';'
5740 { PSpecPath*tmp = $5;
5742 tmp->conditional = true;
5743 tmp->condition = $3;
5745 pform_module_specify_path(tmp);
5747 | K_ifnone specify_simple_path_decl ';'
5748 { PSpecPath*tmp = $2;
5750 tmp->conditional = true;
5753 pform_module_specify_path(tmp);
5755 | K_ifnone specify_edge_path_decl ';'
5756 { yyerror(@1, "Sorry: ifnone with an edge-sensitive path is "
5760 | K_Sfullskew '(' spec_reference_event ',' spec_reference_event
5761 ',' delay_value ',' delay_value spec_notifier_opt ')' ';'
5765 | K_Shold '(' spec_reference_event ',' spec_reference_event
5766 ',' delay_value spec_notifier_opt ')' ';'
5769 | K_Snochange '(' spec_reference_event ',' spec_reference_event
5770 ',' delay_value ',' delay_value spec_notifier_opt ')' ';'
5774 | K_Speriod '(' spec_reference_event ',' delay_value
5775 spec_notifier_opt ')' ';'
5778 | K_Srecovery '(' spec_reference_event ',' spec_reference_event
5779 ',' delay_value spec_notifier_opt ')' ';'
5782 | K_Srecrem '(' spec_reference_event ',' spec_reference_event
5783 ',' delay_value ',' delay_value spec_notifier_opt ')' ';'
5787 | K_Sremoval '(' spec_reference_event ',' spec_reference_event
5788 ',' delay_value spec_notifier_opt ')' ';'
5791 | K_Ssetup '(' spec_reference_event ',' spec_reference_event
5792 ',' delay_value spec_notifier_opt ')' ';'
5795 | K_Ssetuphold '(' spec_reference_event ',' spec_reference_event
5796 ',' delay_value ',' delay_value spec_notifier_opt ')' ';'
5800 | K_Sskew '(' spec_reference_event ',' spec_reference_event
5801 ',' delay_value spec_notifier_opt ')' ';'
5804 | K_Stimeskew '(' spec_reference_event ',' spec_reference_event
5805 ',' delay_value spec_notifier_opt ')' ';'
5808 | K_Swidth '(' spec_reference_event ',' delay_value ',' expression
5809 spec_notifier_opt ')' ';'
5813 | K_Swidth '(' spec_reference_event ',' delay_value ')' ';'
5816 | K_pulsestyle_onevent specify_path_identifiers ';'
5819 | K_pulsestyle_ondetect specify_path_identifiers ';'
5822 | K_showcancelled specify_path_identifiers ';'
5825 | K_noshowcancelled specify_path_identifiers ';'
5832 | specify_item_list specify_item
5835 specify_item_list_opt
5842 specify_edge_path_decl
5843 : specify_edge_path '=' '(' delay_value_list ')'
5844 { $$ = pform_assign_path_delay($1, $4); }
5845 | specify_edge_path '=' delay_value_simple
5846 { list<PExpr*>*tmp = new list<PExpr*>;
5848 $$ = pform_assign_path_delay($1, tmp);
5852 edge_operator : K_posedge { $$ = true; } | K_negedge { $$ = false; } ;
5855 : '(' specify_path_identifiers spec_polarity
5856 K_EG '(' specify_path_identifiers polarity_operator expression ')' ')'
5857 { int edge_flag = 0;
5858 $$ = pform_make_specify_edge_path(@1, edge_flag, $2, $3, false, $6, $8); }
5859 | '(' edge_operator specify_path_identifiers spec_polarity
5860 K_EG '(' specify_path_identifiers polarity_operator expression ')' ')'
5861 { int edge_flag = $2? 1 : -1;
5862 $$ = pform_make_specify_edge_path(@1, edge_flag, $3, $4, false, $7, $9);}
5863 | '(' specify_path_identifiers spec_polarity
5864 K_SG '(' specify_path_identifiers polarity_operator expression ')' ')'
5865 { int edge_flag = 0;
5866 $$ = pform_make_specify_edge_path(@1, edge_flag, $2, $3, true, $6, $8); }
5867 | '(' edge_operator specify_path_identifiers spec_polarity
5868 K_SG '(' specify_path_identifiers polarity_operator expression ')' ')'
5869 { int edge_flag = $2? 1 : -1;
5870 $$ = pform_make_specify_edge_path(@1, edge_flag, $3, $4, true, $7, $9); }
5879 specify_simple_path_decl
5880 : specify_simple_path '=' '(' delay_value_list ')'
5881 { $$ = pform_assign_path_delay($1, $4); }
5882 | specify_simple_path '=' delay_value_simple
5883 { list<PExpr*>*tmp = new list<PExpr*>;
5885 $$ = pform_assign_path_delay($1, tmp);
5887 | specify_simple_path '=' '(' error ')'
5888 { yyerror(@3, "Syntax error in delay value list.");
5895 : '(' specify_path_identifiers spec_polarity
5896 K_EG specify_path_identifiers ')'
5897 { $$ = pform_make_specify_path(@1, $2, $3, false, $5); }
5898 | '(' specify_path_identifiers spec_polarity
5899 K_SG specify_path_identifiers ')'
5900 { $$ = pform_make_specify_path(@1, $2, $3, true, $5); }
5902 { yyerror(@1, "Invalid simple path");
5907 specify_path_identifiers
5909 { list<perm_string>*tmp = new list<perm_string>;
5910 tmp->push_back(lex_strings.make($1));
5914 | IDENTIFIER '[' expr_primary ']'
5915 { if (gn_specify_blocks_flag) {
5916 yywarn(@4, "Bit selects are not currently supported "
5917 "in path declarations. The declaration "
5918 "will be applied to the whole vector.");
5920 list<perm_string>*tmp = new list<perm_string>;
5921 tmp->push_back(lex_strings.make($1));
5925 | IDENTIFIER '[' expr_primary polarity_operator expr_primary ']'
5926 { if (gn_specify_blocks_flag) {
5927 yywarn(@4, "Part selects are not currently supported "
5928 "in path declarations. The declaration "
5929 "will be applied to the whole vector.");
5931 list<perm_string>*tmp = new list<perm_string>;
5932 tmp->push_back(lex_strings.make($1));
5936 | specify_path_identifiers ',' IDENTIFIER
5937 { list<perm_string>*tmp = $1;
5938 tmp->push_back(lex_strings.make($3));
5942 | specify_path_identifiers ',' IDENTIFIER '[' expr_primary ']'
5943 { if (gn_specify_blocks_flag) {
5944 yywarn(@4, "Bit selects are not currently supported "
5945 "in path declarations. The declaration "
5946 "will be applied to the whole vector.");
5948 list<perm_string>*tmp = $1;
5949 tmp->push_back(lex_strings.make($3));
5953 | specify_path_identifiers ',' IDENTIFIER '[' expr_primary polarity_operator expr_primary ']'
5954 { if (gn_specify_blocks_flag) {
5955 yywarn(@4, "Part selects are not currently supported "
5956 "in path declarations. The declaration "
5957 "will be applied to the whole vector.");
5959 list<perm_string>*tmp = $1;
5960 tmp->push_back(lex_strings.make($3));
5967 : IDENTIFIER '=' expression
5969 pform_set_specparam(@1, lex_strings.make($1),
5970 param_active_range, tmp);
5973 | IDENTIFIER '=' expression ':' expression ':' expression
5975 switch (min_typ_max_flag) {
5992 if (min_typ_max_warn > 0) {
5993 cerr << tmp->get_fileline() << ": warning: choosing ";
5994 switch (min_typ_max_flag) {
6005 cerr << " expression." << endl;
6006 min_typ_max_warn -= 1;
6008 pform_set_specparam(@1, lex_strings.make($1),
6009 param_active_range, tmp);
6012 | PATHPULSE_IDENTIFIER '=' expression
6016 | PATHPULSE_IDENTIFIER '=' '(' expression ',' expression ')'
6025 | specparam_list ',' specparam
6031 { param_active_range = $1; }
6033 { param_active_range = 0; }
6042 spec_reference_event
6043 : K_posedge expression
6045 | K_negedge expression
6047 | K_posedge expr_primary K_TAND expression
6051 | K_negedge expr_primary K_TAND expression
6055 | K_edge '[' edge_descriptor_list ']' expr_primary
6057 | K_edge '[' edge_descriptor_list ']' expr_primary K_TAND expression
6061 | expr_primary K_TAND expression
6069 /* The edge_descriptor is detected by the lexor as the various
6070 2-letter edge sequences that are supported here. For now, we
6071 don't care what they are, because we do not yet support specify
6073 edge_descriptor_list
6074 : edge_descriptor_list ',' K_edge_descriptor
6086 { args_after_notifier = 0; }
6087 | ',' hierarchy_identifier
6088 { args_after_notifier = 0; delete $2; }
6090 { args_after_notifier += 1; }
6091 | spec_notifier ',' hierarchy_identifier
6092 { args_after_notifier += 1;
6093 if (args_after_notifier >= 3) {
6094 cerr << @3 << ": warning: timing checks are not supported "
6095 "and delayed signal \"" << *$3
6096 << "\" will not be driven." << endl;
6099 /* How do we match this path? */
6101 { args_after_notifier = 0; delete[]$1; }
6105 statement_item /* This is roughly statement_item in the LRM */
6107 /* assign and deassign statements are procedural code to do
6108 structural assignments, and to turn that structural assignment
6109 off. This is stronger than any other assign, but weaker than the
6110 force assignments. */
6112 : K_assign lpvalue '=' expression ';'
6113 { PCAssign*tmp = new PCAssign($2, $4);
6118 | K_deassign lpvalue ';'
6119 { PDeassign*tmp = new PDeassign($2);
6125 /* Force and release statements are similar to assignments,
6126 syntactically, but they will be elaborated differently. */
6128 | K_force lpvalue '=' expression ';'
6129 { PForce*tmp = new PForce($2, $4);
6133 | K_release lpvalue ';'
6134 { PRelease*tmp = new PRelease($2);
6139 /* begin-end blocks come in a variety of forms, including named and
6140 anonymous. The named blocks can also carry their own reg
6141 variables, which are placed in the scope created by the block
6142 name. These are handled by pushing the scope name, then matching
6143 the declarations. The scope is popped at the end of the block. */
6146 { PBlock*tmp = new PBlock(PBlock::BL_SEQ);
6150 /* In SystemVerilog an unnamed block can contain variable declarations. */
6152 { PBlock*tmp = pform_push_block_scope(0, PBlock::BL_SEQ);
6154 current_block_stack.push(tmp);
6156 block_item_decls_opt
6158 if (! gn_system_verilog()) {
6159 yyerror("error: Variable declaration in unnamed block "
6160 "requires SystemVerilog.");
6163 /* If there are no declarations in the scope then just delete it. */
6165 assert(! current_block_stack.empty());
6166 PBlock*tmp = current_block_stack.top();
6167 current_block_stack.pop();
6171 statement_or_null_list K_end
6175 assert(! current_block_stack.empty());
6176 tmp = current_block_stack.top();
6177 current_block_stack.pop();
6179 tmp = new PBlock(PBlock::BL_SEQ);
6182 if ($5) tmp->set_statement(*$5);
6186 | K_begin ':' IDENTIFIER
6187 { PBlock*tmp = pform_push_block_scope($3, PBlock::BL_SEQ);
6189 current_block_stack.push(tmp);
6191 block_item_decls_opt
6192 statement_or_null_list_opt K_end endlabel_opt
6193 { pform_pop_scope();
6194 assert(! current_block_stack.empty());
6195 PBlock*tmp = current_block_stack.top();
6196 current_block_stack.pop();
6197 if ($6) tmp->set_statement(*$6);
6200 if (strcmp($3,$8) != 0) {
6201 yyerror(@8, "error: End label doesn't match begin name");
6203 if (! gn_system_verilog()) {
6204 yyerror(@8, "error: Begin end labels require "
6213 /* fork-join blocks are very similar to begin-end blocks. In fact,
6214 from the parser's perspective there is no real difference. All we
6215 need to do is remember that this is a parallel block so that the
6216 code generator can do the right thing. */
6218 | K_fork join_keyword
6219 { PBlock*tmp = new PBlock($2);
6223 /* In SystemVerilog an unnamed block can contain variable declarations. */
6225 { PBlock*tmp = pform_push_block_scope(0, PBlock::BL_PAR);
6227 current_block_stack.push(tmp);
6229 block_item_decls_opt
6231 if (! gn_system_verilog()) {
6232 yyerror("error: Variable declaration in unnamed block "
6233 "requires SystemVerilog.");
6236 /* If there are no declarations in the scope then just delete it. */
6238 assert(! current_block_stack.empty());
6239 PBlock*tmp = current_block_stack.top();
6240 current_block_stack.pop();
6244 statement_or_null_list join_keyword
6248 assert(! current_block_stack.empty());
6249 tmp = current_block_stack.top();
6250 current_block_stack.pop();
6251 tmp->set_join_type($6);
6253 tmp = new PBlock($6);
6256 if ($5) tmp->set_statement(*$5);
6260 | K_fork ':' IDENTIFIER
6261 { PBlock*tmp = pform_push_block_scope($3, PBlock::BL_PAR);
6263 current_block_stack.push(tmp);
6265 block_item_decls_opt
6266 statement_or_null_list_opt join_keyword endlabel_opt
6267 { pform_pop_scope();
6268 assert(! current_block_stack.empty());
6269 PBlock*tmp = current_block_stack.top();
6270 current_block_stack.pop();
6271 tmp->set_join_type($7);
6272 if ($6) tmp->set_statement(*$6);
6275 if (strcmp($3,$8) != 0) {
6276 yyerror(@8, "error: End label doesn't match fork name");
6278 if (! gn_system_verilog()) {
6279 yyerror(@8, "error: Fork end labels require "
6288 | K_disable hierarchy_identifier ';'
6289 { PDisable*tmp = new PDisable(*$2);
6294 | K_disable K_fork ';'
6295 { pform_name_t tmp_name;
6296 PDisable*tmp = new PDisable(tmp_name);
6300 | K_TRIGGER hierarchy_identifier ';'
6301 { PTrigger*tmp = new PTrigger(*$2);
6307 | procedural_assertion_statement { $$ = $1; }
6309 | loop_statement { $$ = $1; }
6311 | jump_statement { $$ = $1; }
6313 | K_case '(' expression ')' case_items K_endcase
6314 { PCase*tmp = new PCase(NetCase::EQ, $3, $5);
6318 | K_casex '(' expression ')' case_items K_endcase
6319 { PCase*tmp = new PCase(NetCase::EQX, $3, $5);
6323 | K_casez '(' expression ')' case_items K_endcase
6324 { PCase*tmp = new PCase(NetCase::EQZ, $3, $5);
6328 | K_case '(' expression ')' error K_endcase
6330 | K_casex '(' expression ')' error K_endcase
6332 | K_casez '(' expression ')' error K_endcase
6334 | K_if '(' expression ')' statement_or_null %prec less_than_K_else
6335 { PCondit*tmp = new PCondit($3, $5, 0);
6339 | K_if '(' expression ')' statement_or_null K_else statement_or_null
6340 { PCondit*tmp = new PCondit($3, $5, $7);
6344 | K_if '(' error ')' statement_or_null %prec less_than_K_else
6345 { yyerror(@1, "error: Malformed conditional expression.");
6348 | K_if '(' error ')' statement_or_null K_else statement_or_null
6349 { yyerror(@1, "error: Malformed conditional expression.");
6352 /* SystemVerilog adds the compressed_statement */
6354 | compressed_statement ';'
6357 /* increment/decrement expressions can also be statements. When used
6358 as statements, we can rewrite a++ as a += 1, and so on. */
6360 | inc_or_dec_expression ';'
6361 { $$ = pform_compressed_assign_from_inc_dec(@1, $1); }
6365 | delay1 statement_or_null
6366 { PExpr*del = $1->front();
6367 assert($1->size() == 1);
6369 PDelayStatement*tmp = new PDelayStatement(del, $2);
6374 | event_control statement_or_null
6375 { PEventStatement*tmp = $1;
6377 yyerror(@1, "error: Invalid event control.");
6380 tmp->set_statement($2);
6384 | '@' '*' statement_or_null
6385 { PEventStatement*tmp = new PEventStatement;
6387 tmp->set_statement($3);
6390 | '@' '(' '*' ')' statement_or_null
6391 { PEventStatement*tmp = new PEventStatement;
6393 tmp->set_statement($5);
6397 /* Various assignment statements */
6399 | lpvalue '=' expression ';'
6400 { PAssign*tmp = new PAssign($1,$3);
6405 | error '=' expression ';'
6406 { yyerror(@2, "Syntax in assignment statement l-value.");
6410 | lpvalue K_LE expression ';'
6411 { PAssignNB*tmp = new PAssignNB($1,$3);
6415 | error K_LE expression ';'
6416 { yyerror(@2, "Syntax in assignment statement l-value.");
6420 | lpvalue '=' delay1 expression ';'
6421 { PExpr*del = $3->front(); $3->pop_front();
6422 assert($3->empty());
6423 PAssign*tmp = new PAssign($1,del,$4);
6427 | lpvalue K_LE delay1 expression ';'
6428 { PExpr*del = $3->front(); $3->pop_front();
6429 assert($3->empty());
6430 PAssignNB*tmp = new PAssignNB($1,del,$4);
6434 | lpvalue '=' event_control expression ';'
6435 { PAssign*tmp = new PAssign($1,0,$3,$4);
6439 | lpvalue '=' K_repeat '(' expression ')' event_control expression ';'
6440 { PAssign*tmp = new PAssign($1,$5,$7,$8);
6442 tmp->set_lineno(@1.first_line);
6445 | lpvalue K_LE event_control expression ';'
6446 { PAssignNB*tmp = new PAssignNB($1,0,$3,$4);
6450 | lpvalue K_LE K_repeat '(' expression ')' event_control expression ';'
6451 { PAssignNB*tmp = new PAssignNB($1,$5,$7,$8);
6456 /* The IEEE1800 standard defines dynamic_array_new assignment as a
6457 different rule from regular assignment. That implies that the
6458 dynamic_array_new is not an expression in general, which makes
6459 some sense. Elaboration should make sure the lpvalue is an array name. */
6461 | lpvalue '=' dynamic_array_new ';'
6462 { PAssign*tmp = new PAssign($1,$3);
6467 /* The class new and dynamic array new expressions are special, so
6468 sit in rules of their own. */
6470 | lpvalue '=' class_new ';'
6471 { PAssign*tmp = new PAssign($1,$3);
6476 | K_wait '(' expression ')' statement_or_null
6477 { PEventStatement*tmp;
6478 PEEvent*etmp = new PEEvent(PEEvent::POSITIVE, $3);
6479 tmp = new PEventStatement(etmp);
6481 tmp->set_statement($5);
6485 { PEventStatement*tmp = new PEventStatement((PEEvent*)0);
6489 | SYSTEM_IDENTIFIER '(' expression_list_with_nuls ')' ';'
6490 { PCallTask*tmp = new PCallTask(lex_strings.make($1), *$3);
6496 | SYSTEM_IDENTIFIER ';'
6498 PCallTask*tmp = new PCallTask(lex_strings.make($1), pt);
6504 | hierarchy_identifier '(' expression_list_with_nuls ')' ';'
6505 { PCallTask*tmp = pform_make_call_task(@1, *$1, *$3);
6511 | hierarchy_identifier K_with '{' constraint_block_item_list_opt '}' ';'
6512 { /* ....randomize with { <constraints> } */
6513 if ($1 && peek_tail_name(*$1) == "randomize") {
6514 if (!gn_system_verilog())
6515 yyerror(@2, "error: Randomize with constraint requires SystemVerilog.");
6517 yyerror(@2, "sorry: Randomize with constraint not supported.");
6519 yyerror(@2, "error: Constraint block can only be applied to randomize method.");
6522 PCallTask*tmp = new PCallTask(*$1, pt);
6528 | implicit_class_handle '.' hierarchy_identifier '(' expression_list_with_nuls ')' ';'
6529 { pform_name_t*t_name = $1;
6530 while (! $3->empty()) {
6531 t_name->push_back($3->front());
6534 PCallTask*tmp = new PCallTask(*t_name, *$5);
6542 | hierarchy_identifier ';'
6544 PCallTask*tmp = pform_make_call_task(@1, *$1, pt);
6549 /* IEEE1800 A.1.8: class_constructor_declaration with a call to
6550 parent constructor. Note that the implicit_class_handle must
6551 be K_super ("this.new" makes little sense) but that would
6552 cause a conflict. Anyhow, this statement must be in the
6553 beginning of a constructor, but let the elaborator figure that
6556 | implicit_class_handle '.' K_new '(' expression_list_with_nuls ')' ';'
6557 { PChainConstructor*tmp = new PChainConstructor(*$5);
6562 | hierarchy_identifier '(' error ')' ';'
6563 { yyerror(@3, "error: Syntax error in task arguments.");
6565 PCallTask*tmp = pform_make_call_task(@1, *$1, pt);
6571 { yyerror(@2, "error: malformed statement");
6578 compressed_statement
6579 : lpvalue K_PLUS_EQ expression
6580 { PAssign*tmp = new PAssign($1, '+', $3);
6584 | lpvalue K_MINUS_EQ expression
6585 { PAssign*tmp = new PAssign($1, '-', $3);
6589 | lpvalue K_MUL_EQ expression
6590 { PAssign*tmp = new PAssign($1, '*', $3);
6594 | lpvalue K_DIV_EQ expression
6595 { PAssign*tmp = new PAssign($1, '/', $3);
6599 | lpvalue K_MOD_EQ expression
6600 { PAssign*tmp = new PAssign($1, '%', $3);
6604 | lpvalue K_AND_EQ expression
6605 { PAssign*tmp = new PAssign($1, '&', $3);
6609 | lpvalue K_OR_EQ expression
6610 { PAssign*tmp = new PAssign($1, '|', $3);
6614 | lpvalue K_XOR_EQ expression
6615 { PAssign*tmp = new PAssign($1, '^', $3);
6619 | lpvalue K_LS_EQ expression
6620 { PAssign *tmp = new PAssign($1, 'l', $3);
6624 | lpvalue K_RS_EQ expression
6625 { PAssign*tmp = new PAssign($1, 'r', $3);
6629 | lpvalue K_RSS_EQ expression
6630 { PAssign *tmp = new PAssign($1, 'R', $3);
6637 statement_or_null_list_opt
6638 : statement_or_null_list
6644 statement_or_null_list
6645 : statement_or_null_list statement_or_null
6646 { vector<Statement*>*tmp = $1;
6647 if ($2) tmp->push_back($2);
6651 { vector<Statement*>*tmp = new vector<Statement*>(0);
6652 if ($1) tmp->push_back($1);
6658 : branch_probe_expression K_CONTRIBUTE expression ';'
6659 { $$ = pform_contribution_statement(@2, $1, $3); }
6662 /* Task items are, other than the statement, task port items and
6663 other block items. */
6665 : block_item_decl { $$ = new vector<pform_tf_port_t>(0); }
6666 | tf_port_declaration { $$ = $1; }
6670 : task_item_list task_item
6671 { vector<pform_tf_port_t>*tmp = $1;
6672 size_t s1 = tmp->size();
6673 tmp->resize(s1 + $2->size());
6674 for (size_t idx = 0 ; idx < $2->size() ; idx += 1)
6675 tmp->at(s1 + idx) = $2->at(idx);
6691 : tf_port_list { $$ = $1; }
6695 /* Note that the lexor notices the "table" keyword and starts
6696 the UDPTABLE state. It needs to happen there so that all the
6697 characters in the table are interpreted in that mode. It is still
6698 up to this rule to take us out of the UDPTABLE state. */
6700 : K_table udp_entry_list K_endtable
6704 | K_table K_endtable
6706 yyerror(@1, "error: Empty UDP table.");
6709 | K_table error K_endtable
6711 yyerror(@2, "Errors in UDP table");
6718 : udp_comb_entry_list
6719 | udp_sequ_entry_list
6723 : udp_input_list ':' udp_output_sym ';'
6724 { char*tmp = new char[strlen($1)+3];
6726 char*tp = tmp+strlen(tmp);
6737 { list<string>*tmp = new list<string>;
6742 | udp_comb_entry_list udp_comb_entry
6743 { list<string>*tmp = $1;
6752 { list<string>*tmp = new list<string>;
6757 | udp_sequ_entry_list udp_sequ_entry
6758 { list<string>*tmp = $1;
6766 : udp_input_list ':' udp_input_sym ':' udp_output_sym ';'
6767 { char*tmp = new char[strlen($1)+5];
6769 char*tp = tmp+strlen(tmp);
6780 : K_initial IDENTIFIER '=' number ';'
6781 { PExpr*etmp = new PENumber($4);
6782 PEIdent*itmp = new PEIdent(lex_strings.make($2));
6783 PAssign*atmp = new PAssign(itmp, etmp);
6784 FILE_NAME(atmp, @2);
6791 : udp_initial { $$ = $1; }
6797 { char*tmp = new char[2];
6802 | udp_input_list udp_input_sym
6803 { char*tmp = new char[strlen($1)+2];
6805 char*tp = tmp+strlen(tmp);
6837 | DEC_NUMBER { yyerror(@1, "internal error: Input digits parse as decimal number!"); $$ = '0'; }
6845 | DEC_NUMBER { yyerror(@1, "internal error: Output digits parse as decimal number!"); $$ = '0'; }
6848 /* Port declarations create wires for the inputs and the output. The
6849 makes for these ports are scoped within the UDP, so there is no
6850 hierarchy involved. */
6852 : K_input list_of_identifiers ';'
6853 { $$ = pform_make_udp_input_ports($2); }
6854 | K_output IDENTIFIER ';'
6855 { perm_string pname = lex_strings.make($2);
6856 PWire*pp = new PWire(pname, NetNet::IMPLICIT, NetNet::POUTPUT, IVL_VT_LOGIC);
6857 vector<PWire*>*tmp = new vector<PWire*>(1);
6862 | K_reg IDENTIFIER ';'
6863 { perm_string pname = lex_strings.make($2);
6864 PWire*pp = new PWire(pname, NetNet::REG, NetNet::PIMPLICIT, IVL_VT_LOGIC);
6865 vector<PWire*>*tmp = new vector<PWire*>(1);
6870 | K_reg K_output IDENTIFIER ';'
6871 { perm_string pname = lex_strings.make($3);
6872 PWire*pp = new PWire(pname, NetNet::REG, NetNet::POUTPUT, IVL_VT_LOGIC);
6873 vector<PWire*>*tmp = new vector<PWire*>(1);
6883 | udp_port_decls udp_port_decl
6884 { vector<PWire*>*tmp = $1;
6885 size_t s1 = $1->size();
6886 tmp->resize(s1+$2->size());
6887 for (size_t idx = 0 ; idx < $2->size() ; idx += 1)
6888 tmp->at(s1+idx) = $2->at(idx);
6896 { list<perm_string>*tmp = new list<perm_string>;
6897 tmp->push_back(lex_strings.make($1));
6901 | udp_port_list ',' IDENTIFIER
6902 { list<perm_string>*tmp = $1;
6903 tmp->push_back(lex_strings.make($3));
6909 udp_reg_opt: K_reg { $$ = true; } | { $$ = false; };
6911 udp_initial_expr_opt
6912 : '=' expression { $$ = $2; }
6916 udp_input_declaration_list
6917 : K_input IDENTIFIER
6918 { list<perm_string>*tmp = new list<perm_string>;
6919 tmp->push_back(lex_strings.make($2));
6923 | udp_input_declaration_list ',' K_input IDENTIFIER
6924 { list<perm_string>*tmp = $1;
6925 tmp->push_back(lex_strings.make($4));
6932 /* This is the syntax for primitives that uses the IEEE1364-1995
6933 format. The ports are simply names in the port list, and the
6934 declarations are in the body. */
6936 : K_primitive IDENTIFIER '(' udp_port_list ')' ';'
6940 K_endprimitive endlabel_opt
6942 { perm_string tmp2 = lex_strings.make($2);
6943 pform_make_udp(tmp2, $4, $7, $9, $8,
6944 @2.text, @2.first_line);
6946 if (strcmp($2,$11) != 0) {
6947 yyerror(@11, "error: End label doesn't match "
6950 if (! gn_system_verilog()) {
6951 yyerror(@11, "error: Primitive end labels "
6952 "require SystemVerilog.");
6959 /* This is the syntax for IEEE1364-2001 format definitions. The port
6960 names and declarations are all in the parameter list. */
6962 | K_primitive IDENTIFIER
6963 '(' K_output udp_reg_opt IDENTIFIER udp_initial_expr_opt ','
6964 udp_input_declaration_list ')' ';'
6966 K_endprimitive endlabel_opt
6968 { perm_string tmp2 = lex_strings.make($2);
6969 perm_string tmp6 = lex_strings.make($6);
6970 pform_make_udp(tmp2, $5, tmp6, $7, $9, $12,
6971 @2.text, @2.first_line);
6973 if (strcmp($2,$14) != 0) {
6974 yyerror(@14, "error: End label doesn't match "
6977 if (! gn_system_verilog()) {
6978 yyerror(@14, "error: Primitive end labels "
6979 "require SystemVerilog.");
6988 /* Many keywords can be optional in the syntax, although their
6989 presence is significant. This is a fairly common pattern so
6990 collect those rules here. */
6992 K_packed_opt : K_packed { $$ = true; } | { $$ = false; } ;
6993 K_reg_opt : K_reg { $$ = true; } | { $$ = false; } ;
6994 K_static_opt : K_static { $$ = true; } | { $$ = false; } ;
6995 K_virtual_opt : K_virtual { $$ = true; } | { $$ = false; } ;