2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "blifparse.h"
21 #include "kernel/log.h"
25 static bool read_next_line(char *buffer
, int &line_count
, FILE *f
)
31 int buffer_len
= strlen(buffer
);
32 while (buffer_len
> 0 && (buffer
[buffer_len
-1] == ' ' || buffer
[buffer_len
-1] == '\t' ||
33 buffer
[buffer_len
-1] == '\r' || buffer
[buffer_len
-1] == '\n'))
34 buffer
[--buffer_len
] = 0;
36 if (buffer_len
== 0 || buffer
[buffer_len
-1] == '\\') {
37 if (buffer
[buffer_len
-1] == '\\')
38 buffer
[--buffer_len
] = 0;
40 if (fgets(buffer
+buffer_len
, 4096-buffer_len
, f
) == NULL
)
47 RTLIL::Design
*abc_parse_blif(FILE *f
)
49 RTLIL::Design
*design
= new RTLIL::Design
;
50 RTLIL::Module
*module
= new RTLIL::Module
;
52 RTLIL::Const
*lutptr
= NULL
;
53 RTLIL::State lut_default_state
= RTLIL::State::Sx
;
56 module
->name
= "\\netlist";
57 design
->modules
[module
->name
] = module
;
64 if (!read_next_line(buffer
, line_count
, f
))
67 continue_without_read
:
74 for (auto &bit
: lutptr
->bits
)
75 if (bit
== RTLIL::State::Sx
)
76 bit
= lut_default_state
;
78 lut_default_state
= RTLIL::State::Sx
;
81 char *cmd
= strtok(buffer
, " \t\r\n");
83 if (!strcmp(cmd
, ".model"))
86 if (!strcmp(cmd
, ".end"))
89 if (!strcmp(cmd
, ".inputs") || !strcmp(cmd
, ".outputs")) {
91 while ((p
= strtok(NULL
, " \t\r\n")) != NULL
) {
92 RTLIL::Wire
*wire
= new RTLIL::Wire
;
93 wire
->name
= stringf("\\%s", p
);
94 wire
->port_id
= ++port_count
;
95 if (!strcmp(cmd
, ".inputs"))
96 wire
->port_input
= true;
98 wire
->port_output
= true;
104 if (!strcmp(cmd
, ".names"))
107 RTLIL::SigSpec input_sig
, output_sig
;
108 while ((p
= strtok(NULL
, " \t\r\n")) != NULL
) {
110 if (module
->wires
.count(stringf("\\%s", p
)) > 0) {
111 wire
= module
->wires
.at(stringf("\\%s", p
));
113 wire
= new RTLIL::Wire
;
114 wire
->name
= stringf("\\%s", p
);
117 input_sig
.append(wire
);
119 output_sig
= input_sig
.extract(input_sig
.width
-1, 1);
120 input_sig
= input_sig
.extract(0, input_sig
.width
-1);
122 if (input_sig
.width
== 0) {
123 RTLIL::State state
= RTLIL::State::Sa
;
125 if (!read_next_line(buffer
, line_count
, f
))
127 for (int i
= 0; buffer
[i
]; i
++) {
128 if (buffer
[i
] == ' ' || buffer
[i
] == '\t')
130 if (i
== 0 && buffer
[i
] == '.')
131 goto finished_parsing_constval
;
132 if (buffer
[i
] == '0') {
133 if (state
== RTLIL::State::S1
)
135 state
= RTLIL::State::S0
;
138 if (buffer
[i
] == '1') {
139 if (state
== RTLIL::State::S0
)
141 state
= RTLIL::State::S1
;
147 finished_parsing_constval
:
148 if (state
== RTLIL::State::Sa
)
149 state
= RTLIL::State::S1
;
150 module
->connections
.push_back(RTLIL::SigSig(output_sig
, state
));
151 goto continue_without_read
;
154 input_sig
.optimize();
155 output_sig
.optimize();
157 RTLIL::Cell
*cell
= new RTLIL::Cell
;
160 cell
->parameters
["\\WIDTH"] = RTLIL::Const(input_sig
.width
);
161 cell
->parameters
["\\LUT"] = RTLIL::Const(RTLIL::State::Sx
, 1 << input_sig
.width
);
162 cell
->connections
["\\I"] = input_sig
;
163 cell
->connections
["\\O"] = output_sig
;
164 lutptr
= &cell
->parameters
.at("\\LUT");
165 lut_default_state
= RTLIL::State::Sx
;
176 char *input
= strtok(buffer
, " \t\r\n");
177 char *output
= strtok(NULL
, " \t\r\n");
179 if (input
== NULL
|| output
== NULL
|| (strcmp(output
, "0") && strcmp(output
, "1")))
182 int input_len
= strlen(input
);
186 for (int i
= 0; i
< (1 << input_len
); i
++) {
187 for (int j
= 0; j
< input_len
; j
++) {
190 char c2
= (i
& (1 << j
)) != 0 ? '1' : '0';
195 lutptr
->bits
.at(i
) = !strcmp(output
, "0") ? RTLIL::State::S0
: RTLIL::State::S1
;
199 lut_default_state
= !strcmp(output
, "0") ? RTLIL::State::S1
: RTLIL::State::S0
;
203 log_error("Syntax error in line %d!\n", line_count
);