passes/abc/blifparse.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "blifparse.h"
  21 #include "kernel/log.h"
  22 #include <stdio.h>
  23 #include <string.h>
  24
  25 static bool read_next_line(char *buffer, int &line_count, FILE *f)
  26 {
  27         buffer[0] = 0;
  28
  29         while (1)
  30         {
  31                 int buffer_len = strlen(buffer);
  32                 while (buffer_len > 0 && (buffer[buffer_len-1] == ' ' || buffer[buffer_len-1] == '\t' ||
  33                                 buffer[buffer_len-1] == '\r' || buffer[buffer_len-1] == '\n'))
  34                         buffer[--buffer_len] = 0;
  35
  36                 if (buffer_len == 0 || buffer[buffer_len-1] == '\\') {
  37                         if (buffer[buffer_len-1] == '\\')
  38                                 buffer[--buffer_len] = 0;
  39                         line_count++;
  40                         if (fgets(buffer+buffer_len, 4096-buffer_len, f) == NULL)
  41                                 return false;
  42                 } else
  43                         return true;
  44         }
  45 }
  46
  47 RTLIL::Design *abc_parse_blif(FILE *f)
  48 {
  49         RTLIL::Design *design = new RTLIL::Design;
  50         RTLIL::Module *module = new RTLIL::Module;
  51
  52         RTLIL::Const *lutptr = NULL;
  53         RTLIL::State lut_default_state = RTLIL::State::Sx;
  54
  55         int port_count = 0;
  56         module->name = "\\netlist";
  57         design->modules[module->name] = module;
  58
  59         char buffer[4096];
  60         int line_count = 0;
  61
  62         while (1)
  63         {
  64                 if (!read_next_line(buffer, line_count, f))
  65                         goto error;
  66
  67         continue_without_read:
  68                 if (buffer[0] == '#')
  69                         continue;
  70
  71                 if (buffer[0] == '.')
  72                 {
  73                         if (lutptr) {
  74                                 for (auto &bit : lutptr->bits)
  75                                         if (bit == RTLIL::State::Sx)
  76                                                 bit = lut_default_state;
  77                                 lutptr = NULL;
  78                                 lut_default_state = RTLIL::State::Sx;
  79                         }
  80
  81                         char *cmd = strtok(buffer, " \t\r\n");
  82
  83                         if (!strcmp(cmd, ".model"))
  84                                 continue;
  85
  86                         if (!strcmp(cmd, ".end"))
  87                                 return design;
  88
  89                         if (!strcmp(cmd, ".inputs") || !strcmp(cmd, ".outputs")) {
  90                                 char *p;
  91                                 while ((p = strtok(NULL, " \t\r\n")) != NULL) {
  92                                         RTLIL::Wire *wire = new RTLIL::Wire;
  93                                         wire->name = stringf("\\%s", p);
  94                                         wire->port_id = ++port_count;
  95                                         if (!strcmp(cmd, ".inputs"))
  96                                                 wire->port_input = true;
  97                                         else
  98                                                 wire->port_output = true;
  99                                         module->add(wire);
 100                                 }
 101                                 continue;
 102                         }
 103
 104                         if (!strcmp(cmd, ".names"))
 105                         {
 106                                 char *p;
 107                                 RTLIL::SigSpec input_sig, output_sig;
 108                                 while ((p = strtok(NULL, " \t\r\n")) != NULL) {
 109                                         RTLIL::Wire *wire;
 110                                         if (module->wires.count(stringf("\\%s", p)) > 0) {
 111                                                 wire = module->wires.at(stringf("\\%s", p));
 112                                         } else {
 113                                                 wire = new RTLIL::Wire;
 114                                                 wire->name = stringf("\\%s", p);
 115                                                 module->add(wire);
 116                                         }
 117                                         input_sig.append(wire);
 118                                 }
 119                                 output_sig = input_sig.extract(input_sig.width-1, 1);
 120                                 input_sig = input_sig.extract(0, input_sig.width-1);
 121
 122                                 if (input_sig.width == 0) {
 123                                         RTLIL::State state = RTLIL::State::Sa;
 124                                         while (1) {
 125                                                 if (!read_next_line(buffer, line_count, f))
 126                                                         goto error;
 127                                                 for (int i = 0; buffer[i]; i++) {
 128                                                         if (buffer[i] == ' ' || buffer[i] == '\t')
 129                                                                 continue;
 130                                                         if (i == 0 && buffer[i] == '.')
 131                                                                 goto finished_parsing_constval;
 132                                                         if (buffer[i] == '0') {
 133                                                                 if (state == RTLIL::State::S1)
 134                                                                         goto error;
 135                                                                 state = RTLIL::State::S0;
 136                                                                 continue;
 137                                                         }
 138                                                         if (buffer[i] == '1') {
 139                                                                 if (state == RTLIL::State::S0)
 140                                                                         goto error;
 141                                                                 state = RTLIL::State::S1;
 142                                                                 continue;
 143                                                         }
 144                                                         goto error;
 145                                                 }
 146                                         }
 147                                 finished_parsing_constval:
 148                                         if (state == RTLIL::State::Sa)
 149                                                 state = RTLIL::State::S1;
 150                                         module->connections.push_back(RTLIL::SigSig(output_sig, state));
 151                                         goto continue_without_read;
 152                                 }
 153
 154                                 input_sig.optimize();
 155                                 output_sig.optimize();
 156
 157                                 RTLIL::Cell *cell = new RTLIL::Cell;
 158                                 cell->name = NEW_ID;
 159                                 cell->type = "$lut";
 160                                 cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.width);
 161                                 cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.width);
 162                                 cell->connections["\\I"] = input_sig;
 163                                 cell->connections["\\O"] = output_sig;
 164                                 lutptr = &cell->parameters.at("\\LUT");
 165                                 lut_default_state = RTLIL::State::Sx;
 166                                 module->add(cell);
 167                                 continue;
 168                         }
 169
 170                         goto error;
 171                 }
 172
 173                 if (lutptr == NULL)
 174                         goto error;
 175
 176                 char *input = strtok(buffer, " \t\r\n");
 177                 char *output = strtok(NULL, " \t\r\n");
 178
 179                 if (input == NULL || output == NULL || (strcmp(output, "0") && strcmp(output, "1")))
 180                         goto error;
 181
 182                 int input_len = strlen(input);
 183                 if (input_len > 8)
 184                         goto error;
 185
 186                 for (int i = 0; i < (1 << input_len); i++) {
 187                         for (int j = 0; j < input_len; j++) {
 188                                 char c1 = input[j];
 189                                 if (c1 != '-') {
 190                                         char c2 = (i & (1 << j)) != 0 ? '1' : '0';
 191                                         if (c1 != c2)
 192                                                 goto try_next_value;
 193                                 }
 194                         }
 195                         lutptr->bits.at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1;
 196                 try_next_value:;
 197                 }
 198
 199                 lut_default_state = !strcmp(output, "0") ? RTLIL::State::S1 : RTLIL::State::S0;
 200         }
 201
 202 error:
 203         log_error("Syntax error in line %d!\n", line_count);
 204         // delete design;
 205         // return NULL;
 206 }
 207