2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
23 PRIVATE_NAMESPACE_BEGIN
25 static void add_wire(RTLIL::Design
*design
, RTLIL::Module
*module
, std::string name
, int width
, bool flag_input
, bool flag_output
, bool flag_global
)
27 RTLIL::Wire
*wire
= NULL
;
28 name
= RTLIL::escape_id(name
);
30 if (module
->count_id(name
) != 0)
32 if (module
->wires_
.count(name
) > 0)
33 wire
= module
->wires_
.at(name
);
35 if (wire
!= NULL
&& wire
->width
!= width
)
38 if (wire
!= NULL
&& wire
->port_input
!= flag_input
)
41 if (wire
!= NULL
&& wire
->port_output
!= flag_output
)
45 log_cmd_error("Found incompatible object with same name in module %s!\n", module
->name
.c_str());
47 log("Module %s already has such an object.\n", module
->name
.c_str());
51 wire
= module
->addWire(name
, width
);
52 wire
->port_input
= flag_input
;
53 wire
->port_output
= flag_output
;
55 if (flag_input
|| flag_output
) {
56 wire
->port_id
= module
->wires_
.size();
57 module
->fixup_ports();
60 log("Added wire %s to module %s.\n", name
.c_str(), module
->name
.c_str());
66 for (auto &it
: module
->cells_
)
68 if (design
->modules_
.count(it
.second
->type
) == 0)
71 RTLIL::Module
*mod
= design
->modules_
.at(it
.second
->type
);
72 if (!design
->selected_whole_module(mod
->name
))
74 if (mod
->get_blackbox_attribute())
76 if (it
.second
->hasPort(name
))
79 it
.second
->setPort(name
, wire
);
80 log("Added connection %s to cell %s.%s (%s).\n", name
.c_str(), module
->name
.c_str(), it
.first
.c_str(), it
.second
->type
.c_str());
84 struct AddPass
: public Pass
{
85 AddPass() : Pass("add", "add objects to the design") { }
86 void help() YS_OVERRIDE
88 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
90 log(" add <command> [selection]\n");
92 log("This command adds objects to the design. It operates on all fully selected\n");
93 log("modules. So e.g. 'add -wire foo' will add a wire foo to all selected modules.\n");
96 log(" add {-wire|-input|-inout|-output} <name> <width> [selection]\n");
98 log("Add a wire (input, inout, output port) with the given name and width. The\n");
99 log("command will fail if the object exists already and has different properties\n");
100 log("than the object to be created.\n");
103 log(" add -global_input <name> <width> [selection]\n");
105 log("Like 'add -input', but also connect the signal between instances of the\n");
106 log("selected modules.\n");
109 log(" add -mod <name[s]>\n");
111 log("Add module[s] with the specified name[s].\n");
114 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
117 std::string arg_name
;
118 bool arg_flag_input
= false;
119 bool arg_flag_output
= false;
120 bool arg_flag_global
= false;
121 bool mod_mode
= false;
125 for (argidx
= 1; argidx
< args
.size(); argidx
++)
127 std::string arg
= args
[argidx
];
128 if (arg
== "-wire" || arg
== "-input" || arg
== "-inout" || arg
== "-output" || arg
== "-global_input") {
129 if (argidx
+2 >= args
.size())
132 if (arg
== "-input" || arg
== "-inout" || arg
== "-global_input")
133 arg_flag_input
= true;
134 if (arg
== "-output" || arg
== "-inout")
135 arg_flag_output
= true;
136 if (arg
== "-global_input")
137 arg_flag_global
= true;
138 arg_name
= args
[++argidx
];
139 arg_width
= atoi(args
[++argidx
].c_str());
151 for (; argidx
< args
.size(); argidx
++)
152 design
->addModule(RTLIL::escape_id(args
[argidx
]));
156 extra_args(args
, argidx
, design
);
158 for (auto &mod
: design
->modules_
)
160 RTLIL::Module
*module
= mod
.second
;
161 if (!design
->selected_whole_module(module
->name
))
163 if (module
->get_bool_attribute("\\blackbox"))
166 if (command
== "wire")
167 add_wire(design
, module
, arg_name
, arg_width
, arg_flag_input
, arg_flag_output
, arg_flag_global
);
172 PRIVATE_NAMESPACE_END