passes/cmds/autoname.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21
  22 USING_YOSYS_NAMESPACE
  23 PRIVATE_NAMESPACE_BEGIN
  24
  25 int autoname_worker(Module *module)
  26 {
  27         dict<Cell*, pair<int, IdString>> proposed_cell_names;
  28         dict<Wire*, pair<int, IdString>> proposed_wire_names;
  29         dict<Wire*, int> wire_score;
  30         int best_score = -1;
  31
  32         for (auto cell : module->selected_cells())
  33         for (auto &conn : cell->connections())
  34         for (auto bit : conn.second)
  35                 if (bit.wire != nullptr)
  36                         wire_score[bit.wire]++;
  37
  38         for (auto cell : module->selected_cells()) {
  39                 if (cell->name[0] == '$') {
  40                         for (auto &conn : cell->connections()) {
  41                                 string suffix = stringf("_%s_%s", log_id(cell->type), log_id(conn.first));
  42                                 for (auto bit : conn.second)
  43                                         if (bit.wire != nullptr && bit.wire->name[0] != '$') {
  44                                                 IdString new_name(bit.wire->name.str() + suffix);
  45                                                 int score = wire_score.at(bit.wire);
  46                                                 if (cell->output(conn.first)) score = 0;
  47                                                 score = 10000*score + new_name.size();
  48                                                 if (!proposed_cell_names.count(cell) || score < proposed_cell_names.at(cell).first) {
  49                                                         if (best_score < 0 || score < best_score)
  50                                                                 best_score = score;
  51                                                         proposed_cell_names[cell] = make_pair(score, new_name);
  52                                                 }
  53                                         }
  54                         }
  55                 } else {
  56                         for (auto &conn : cell->connections()) {
  57                                 string suffix = stringf("_%s", log_id(conn.first));
  58                                 for (auto bit : conn.second)
  59                                         if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) {
  60                                                 IdString new_name(cell->name.str() + suffix);
  61                                                 int score = wire_score.at(bit.wire);
  62                                                 if (cell->output(conn.first)) score = 0;
  63                                                 score = 10000*score + new_name.size();
  64                                                 if (!proposed_wire_names.count(bit.wire) || score < proposed_wire_names.at(bit.wire).first) {
  65                                                         if (best_score < 0 || score < best_score)
  66                                                                 best_score = score;
  67                                                         proposed_wire_names[bit.wire] = make_pair(score, new_name);
  68                                                 }
  69                                         }
  70                         }
  71                 }
  72         }
  73
  74         for (auto &it : proposed_cell_names) {
  75                 if (best_score*2 < it.second.first)
  76                         continue;
  77                 IdString n = module->uniquify(it.second.second);
  78                 log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
  79                 module->rename(it.first, n);
  80         }
  81
  82         for (auto &it : proposed_wire_names) {
  83                 if (best_score*2 < it.second.first)
  84                         continue;
  85                 IdString n = module->uniquify(it.second.second);
  86                 log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
  87                 module->rename(it.first, n);
  88         }
  89
  90         return proposed_cell_names.size() + proposed_wire_names.size();
  91 }
  92
  93 struct AutonamePass : public Pass {
  94         AutonamePass() : Pass("autoname", "automatically assign names to objects") { }
  95         void help() YS_OVERRIDE
  96         {
  97                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  98                 log("\n");
  99                 log("    autoname [selection]\n");
 100                 log("\n");
 101                 log("Assign auto-generated public names to objects with private names (the ones\n");
 102                 log("with $-prefix).\n");
 103                 log("\n");
 104         }
 105         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 106         {
 107                 size_t argidx;
 108                 for (argidx = 1; argidx < args.size(); argidx++)
 109                 {
 110                         // if (args[argidx] == "-foo") {
 111                         //      foo = true;
 112                         //      continue;
 113                         // }
 114                         break;
 115                 }
 116
 117                 log_header(design, "Executing AUTONAME pass.\n");
 118
 119                 for (auto module : design->selected_modules())
 120                 {
 121                         int count = 0, iter = 0;
 122                         while (1) {
 123                                 iter++;
 124                                 int n = autoname_worker(module);
 125                                 if (!n) break;
 126                                 count += n;
 127                         }
 128                         if (count > 0)
 129                                 log("Renamed %d objects in module %s (%d iterations).\n", count, log_id(module), iter);
 130                 }
 131         }
 132 } AutonamePass;
 133
 134 PRIVATE_NAMESPACE_END