passes/cmds/blackbox.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21
  22 USING_YOSYS_NAMESPACE
  23 PRIVATE_NAMESPACE_BEGIN
  24
  25 struct BlackboxPass : public Pass {
  26         BlackboxPass() : Pass("blackbox", "convert modules into blackbox modules") { }
  27         void help() YS_OVERRIDE
  28         {
  29                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  30                 log("\n");
  31                 log("    blackbox [options] [selection]\n");
  32                 log("\n");
  33                 log("Convert modules into blackbox modules (remove contents and set the blackbox\n");
  34                 log("module attribute).\n");
  35                 log("\n");
  36         }
  37         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  38         {
  39                 size_t argidx;
  40                 for (argidx = 1; argidx < args.size(); argidx++)
  41                 {
  42                         // if (args[argidx] == "-???") {
  43                         //      continue;
  44                         // }
  45                         break;
  46                 }
  47                 extra_args(args, argidx, design);
  48
  49                 for (auto module : design->selected_whole_modules_warn())
  50                 {
  51                         pool<Cell*> remove_cells;
  52                         pool<Wire*> remove_wires;
  53
  54                         for (auto cell : module->cells())
  55                                 remove_cells.insert(cell);
  56
  57                         for (auto wire : module->wires())
  58                                 if (wire->port_id == 0)
  59                                         remove_wires.insert(wire);
  60
  61                         for (auto it = module->memories.begin(); it != module->memories.end(); ++it)
  62                                 delete it->second;
  63                         module->memories.clear();
  64
  65                         for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
  66                                 delete it->second;
  67                         module->processes.clear();
  68
  69                         module->new_connections(std::vector<RTLIL::SigSig>());
  70
  71                         for (auto cell : remove_cells)
  72                                 module->remove(cell);
  73
  74                         module->remove(remove_wires);
  75
  76                         module->set_bool_attribute(ID::blackbox);
  77                 }
  78         }
  79 } BlackboxPass;
  80
  81 PRIVATE_NAMESPACE_END