passes/cmds/check.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/sigtools.h"
  22 #include "kernel/celltypes.h"
  23 #include "kernel/utils.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct CheckPass : public Pass {
  29         CheckPass() : Pass("check", "check for obvious problems in the design") { }
  30         void help() YS_OVERRIDE
  31         {
  32                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  33                 log("\n");
  34                 log("    check [options] [selection]\n");
  35                 log("\n");
  36                 log("This pass identifies the following problems in the current design:\n");
  37                 log("\n");
  38                 log(" - combinatorial loops\n");
  39                 log("\n");
  40                 log(" - two or more conflicting drivers for one wire\n");
  41                 log("\n");
  42                 log(" - used wires that do not have a driver\n");
  43                 log("\n");
  44                 log("Options:\n");
  45                 log("\n");
  46                 log("  -noinit\n");
  47                 log("    Also check for wires which have the 'init' attribute set.\n");
  48                 log("\n");
  49                 log("  -initdrv\n");
  50                 log("    Also check for wires that have the 'init' attribute set and are not\n");
  51                 log("    driven by an FF cell type.\n");
  52                 log("\n");
  53                 log("  -mapped\n");
  54                 log("    Also check for internal cells that have not been mapped to cells of the\n");
  55                 log("    target architecture.\n");
  56                 log("\n");
  57                 log("  -allow-tbuf\n");
  58                 log("    Modify the -mapped behavior to still allow $_TBUF_ cells.\n");
  59                 log("\n");
  60                 log("  -assert\n");
  61                 log("    Produce a runtime error if any problems are found in the current design.\n");
  62                 log("\n");
  63         }
  64         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  65         {
  66                 int counter = 0;
  67                 bool noinit = false;
  68                 bool initdrv = false;
  69                 bool mapped = false;
  70                 bool allow_tbuf = false;
  71                 bool assert_mode = false;
  72
  73                 size_t argidx;
  74                 for (argidx = 1; argidx < args.size(); argidx++) {
  75                         if (args[argidx] == "-noinit") {
  76                                 noinit = true;
  77                                 continue;
  78                         }
  79                         if (args[argidx] == "-initdrv") {
  80                                 initdrv = true;
  81                                 continue;
  82                         }
  83                         if (args[argidx] == "-mapped") {
  84                                 mapped = true;
  85                                 continue;
  86                         }
  87                         if (args[argidx] == "-allow-tbuf") {
  88                                 allow_tbuf = true;
  89                                 continue;
  90                         }
  91                         if (args[argidx] == "-assert") {
  92                                 assert_mode = true;
  93                                 continue;
  94                         }
  95                         break;
  96                 }
  97                 extra_args(args, argidx, design);
  98
  99                 log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
 100
 101                 for (auto module : design->selected_whole_modules_warn())
 102                 {
 103                         if (module->has_processes_warn())
 104                                 continue;
 105
 106                         log("checking module %s..\n", log_id(module));
 107
 108                         SigMap sigmap(module);
 109                         dict<SigBit, vector<string>> wire_drivers;
 110                         dict<SigBit, int> wire_drivers_count;
 111                         pool<SigBit> used_wires;
 112                         TopoSort<string> topo;
 113
 114                         for (auto cell : module->cells())
 115                         {
 116                                 if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
 117                                         if (allow_tbuf && cell->type == ID($_TBUF_)) goto cell_allowed;
 118                                         log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", log_id(module), log_id(cell), log_id(cell->type));
 119                                         counter++;
 120                                 cell_allowed:;
 121                                 }
 122                                 for (auto &conn : cell->connections()) {
 123                                         SigSpec sig = sigmap(conn.second);
 124                                         bool logic_cell = yosys_celltypes.cell_evaluable(cell->type);
 125                                         if (cell->input(conn.first))
 126                                                 for (auto bit : sig)
 127                                                         if (bit.wire) {
 128                                                                 if (logic_cell)
 129                                                                         topo.edge(stringf("wire %s", log_signal(bit)),
 130                                                                                         stringf("cell %s (%s)", log_id(cell), log_id(cell->type)));
 131                                                                 used_wires.insert(bit);
 132                                                         }
 133                                         if (cell->output(conn.first))
 134                                                 for (int i = 0; i < GetSize(sig); i++) {
 135                                                         if (logic_cell)
 136                                                                 topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)),
 137                                                                                 stringf("wire %s", log_signal(sig[i])));
 138                                                         if (sig[i].wire)
 139                                                                 wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)",
 140                                                                                 log_id(conn.first), i, log_id(cell), log_id(cell->type)));
 141                                                 }
 142                                         if (!cell->input(conn.first) && cell->output(conn.first))
 143                                                 for (auto bit : sig)
 144                                                         if (bit.wire) wire_drivers_count[bit]++;
 145                                 }
 146                         }
 147
 148                         pool<SigBit> init_bits;
 149
 150                         for (auto wire : module->wires()) {
 151                                 if (wire->port_input) {
 152                                         SigSpec sig = sigmap(wire);
 153                                         for (int i = 0; i < GetSize(sig); i++)
 154                                                 wire_drivers[sig[i]].push_back(stringf("module input %s[%d]", log_id(wire), i));
 155                                 }
 156                                 if (wire->port_output)
 157                                         for (auto bit : sigmap(wire))
 158                                                 if (bit.wire) used_wires.insert(bit);
 159                                 if (wire->port_input && !wire->port_output)
 160                                         for (auto bit : sigmap(wire))
 161                                                 if (bit.wire) wire_drivers_count[bit]++;
 162                                 if (wire->attributes.count(ID::init)) {
 163                                         Const initval = wire->attributes.at(ID::init);
 164                                         for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++)
 165                                                 if (initval[i] == State::S0 || initval[i] == State::S1)
 166                                                         init_bits.insert(sigmap(SigBit(wire, i)));
 167                                         if (noinit) {
 168                                                 log_warning("Wire %s.%s has an unprocessed 'init' attribute.\n", log_id(module), log_id(wire));
 169                                                 counter++;
 170                                         }
 171                                 }
 172                         }
 173
 174                         for (auto it : wire_drivers)
 175                                 if (wire_drivers_count[it.first] > 1) {
 176                                         string message = stringf("multiple conflicting drivers for %s.%s:\n", log_id(module), log_signal(it.first));
 177                                         for (auto str : it.second)
 178                                                 message += stringf("    %s\n", str.c_str());
 179                                         log_warning("%s", message.c_str());
 180                                         counter++;
 181                                 }
 182
 183                         for (auto bit : used_wires)
 184                                 if (!wire_drivers.count(bit)) {
 185                                         log_warning("Wire %s.%s is used but has no driver.\n", log_id(module), log_signal(bit));
 186                                         counter++;
 187                                 }
 188
 189                         topo.sort();
 190                         for (auto &loop : topo.loops) {
 191                                 string message = stringf("found logic loop in module %s:\n", log_id(module));
 192                                 for (auto &str : loop)
 193                                         message += stringf("    %s\n", str.c_str());
 194                                 log_warning("%s", message.c_str());
 195                                 counter++;
 196                         }
 197
 198                         if (initdrv)
 199                         {
 200                                 for (auto cell : module->cells())
 201                                 {
 202                                         if (RTLIL::builtin_ff_cell_types().count(cell->type) == 0)
 203                                                 continue;
 204
 205                                         for (auto bit : sigmap(cell->getPort(ID::Q)))
 206                                                 init_bits.erase(bit);
 207                                 }
 208
 209                                 SigSpec init_sig(init_bits);
 210                                 init_sig.sort_and_unify();
 211
 212                                 for (auto chunk : init_sig.chunks()) {
 213                                         log_warning("Wire %s.%s has 'init' attribute and is not driven by an FF cell.\n", log_id(module), log_signal(chunk));
 214                                         counter++;
 215                                 }
 216                         }
 217                 }
 218
 219                 log("found and reported %d problems.\n", counter);
 220
 221                 if (assert_mode && counter > 0)
 222                         log_error("Found %d problems in 'check -assert'.\n", counter);
 223         }
 224 } CheckPass;
 225
 226 PRIVATE_NAMESPACE_END