2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/rtlil.h"
22 #include "kernel/log.h"
24 struct DeleteWireWorker
26 RTLIL::Module
*module
;
27 std::set
<std::string
> *delete_wires_p
;
29 void operator()(RTLIL::SigSpec
&sig
) {
31 for (auto &c
: sig
.__chunks
)
32 if (c
.wire
!= NULL
&& delete_wires_p
->count(c
.wire
->name
)) {
33 c
.wire
= module
->addWire(NEW_ID
, c
.width
);
39 struct DeletePass
: public Pass
{
40 DeletePass() : Pass("delete", "delete objects in the design") { }
43 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
45 log(" delete [selection]\n");
47 log("Deletes the selected objects. This will also remove entire modules, if the\n");
48 log("whole module is selected.\n");
51 log(" delete {-input|-output|-port} [selection]\n");
53 log("Does not delete any object but removes the input and/or output flag on the\n");
54 log("selected wires, thus 'deleting' module ports.\n");
57 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
59 bool flag_input
= false;
60 bool flag_output
= false;
63 for (argidx
= 1; argidx
< args
.size(); argidx
++)
65 if (args
[argidx
] == "-input") {
69 if (args
[argidx
] == "-output") {
73 if (args
[argidx
] == "-port") {
80 extra_args(args
, argidx
, design
);
82 std::vector
<std::string
> delete_mods
;
84 for (auto &mod_it
: design
->modules
)
86 if (design
->selected_whole_module(mod_it
.first
) && !flag_input
&& !flag_output
) {
87 delete_mods
.push_back(mod_it
.first
);
91 if (!design
->selected_module(mod_it
.first
))
94 RTLIL::Module
*module
= mod_it
.second
;
96 if (flag_input
|| flag_output
) {
97 for (auto &it
: module
->wires
)
98 if (design
->selected(module
, it
.second
)) {
100 it
.second
->port_input
= false;
102 it
.second
->port_output
= false;
104 module
->fixup_ports();
108 std::set
<std::string
> delete_wires
;
109 std::set
<std::string
> delete_cells
;
110 std::set
<std::string
> delete_procs
;
111 std::set
<std::string
> delete_mems
;
113 for (auto &it
: module
->wires
)
114 if (design
->selected(module
, it
.second
))
115 delete_wires
.insert(it
.first
);
117 for (auto &it
: module
->memories
)
118 if (design
->selected(module
, it
.second
))
119 delete_mems
.insert(it
.first
);
121 for (auto &it
: module
->cells
) {
122 if (design
->selected(module
, it
.second
))
123 delete_cells
.insert(it
.first
);
124 if ((it
.second
->type
== "$memrd" || it
.second
->type
== "$memwr") &&
125 delete_mems
.count(it
.second
->parameters
.at("\\MEMID").decode_string()) != 0)
126 delete_cells
.insert(it
.first
);
129 for (auto &it
: module
->processes
)
130 if (design
->selected(module
, it
.second
))
131 delete_procs
.insert(it
.first
);
133 DeleteWireWorker delete_wire_worker
;
134 delete_wire_worker
.module
= module
;
135 delete_wire_worker
.delete_wires_p
= &delete_wires
;
136 module
->rewrite_sigspecs(delete_wire_worker
);
138 for (auto &it
: delete_wires
) {
139 delete module
->wires
.at(it
);
140 module
->wires
.erase(it
);
143 for (auto &it
: delete_mems
) {
144 delete module
->memories
.at(it
);
145 module
->memories
.erase(it
);
148 for (auto &it
: delete_cells
) {
149 delete module
->cells
.at(it
);
150 module
->cells
.erase(it
);
153 for (auto &it
: delete_procs
) {
154 delete module
->processes
.at(it
);
155 module
->processes
.erase(it
);
158 module
->fixup_ports();
161 for (auto &it
: delete_mods
) {
162 delete design
->modules
.at(it
);
163 design
->modules
.erase(it
);