passes/cmds/delete.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21
  22 USING_YOSYS_NAMESPACE
  23 PRIVATE_NAMESPACE_BEGIN
  24
  25 struct DeletePass : public Pass {
  26         DeletePass() : Pass("delete", "delete objects in the design") { }
  27         void help() YS_OVERRIDE
  28         {
  29                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  30                 log("\n");
  31                 log("    delete [selection]\n");
  32                 log("\n");
  33                 log("Deletes the selected objects. This will also remove entire modules, if the\n");
  34                 log("whole module is selected.\n");
  35                 log("\n");
  36                 log("\n");
  37                 log("    delete {-input|-output|-port} [selection]\n");
  38                 log("\n");
  39                 log("Does not delete any object but removes the input and/or output flag on the\n");
  40                 log("selected wires, thus 'deleting' module ports.\n");
  41                 log("\n");
  42         }
  43         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  44         {
  45                 bool flag_input = false;
  46                 bool flag_output = false;
  47
  48                 size_t argidx;
  49                 for (argidx = 1; argidx < args.size(); argidx++)
  50                 {
  51                         if (args[argidx] == "-input") {
  52                                 flag_input = true;
  53                                 continue;
  54                         }
  55                         if (args[argidx] == "-output") {
  56                                 flag_output = true;
  57                                 continue;
  58                         }
  59                         if (args[argidx] == "-port") {
  60                                 flag_input = true;
  61                                 flag_output = true;
  62                                 continue;
  63                         }
  64                         break;
  65                 }
  66                 extra_args(args, argidx, design);
  67
  68                 std::vector<RTLIL::IdString> delete_mods;
  69
  70                 for (auto &mod_it : design->modules_)
  71                 {
  72                         if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) {
  73                                 delete_mods.push_back(mod_it.first);
  74                                 continue;
  75                         }
  76
  77                         if (!design->selected_module(mod_it.first))
  78                                 continue;
  79
  80                         RTLIL::Module *module = mod_it.second;
  81
  82                         if (flag_input || flag_output) {
  83                                 for (auto &it : module->wires_)
  84                                         if (design->selected(module, it.second)) {
  85                                                 if (flag_input)
  86                                                         it.second->port_input = false;
  87                                                 if (flag_output)
  88                                                         it.second->port_output = false;
  89                                         }
  90                                 module->fixup_ports();
  91                                 continue;
  92                         }
  93
  94                         pool<RTLIL::Wire*> delete_wires;
  95                         pool<RTLIL::Cell*> delete_cells;
  96                         pool<RTLIL::IdString> delete_procs;
  97                         pool<RTLIL::IdString> delete_mems;
  98
  99                         for (auto &it : module->wires_)
 100                                 if (design->selected(module, it.second))
 101                                         delete_wires.insert(it.second);
 102
 103                         for (auto &it : module->memories)
 104                                 if (design->selected(module, it.second))
 105                                         delete_mems.insert(it.first);
 106
 107                         for (auto &it : module->cells_) {
 108                                 if (design->selected(module, it.second))
 109                                         delete_cells.insert(it.second);
 110                                 if (it.second->type.in("$memrd", "$memwr") &&
 111                                                 delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0)
 112                                         delete_cells.insert(it.second);
 113                         }
 114
 115                         for (auto &it : module->processes)
 116                                 if (design->selected(module, it.second))
 117                                         delete_procs.insert(it.first);
 118
 119                         for (auto &it : delete_mems) {
 120                                 delete module->memories.at(it);
 121                                 module->memories.erase(it);
 122                         }
 123
 124                         for (auto &it : delete_cells)
 125                                 module->remove(it);
 126
 127                         for (auto &it : delete_procs) {
 128                                 delete module->processes.at(it);
 129                                 module->processes.erase(it);
 130                         }
 131
 132                         module->remove(delete_wires);
 133
 134                         module->fixup_ports();
 135                 }
 136
 137                 for (auto &it : delete_mods) {
 138                         delete design->modules_.at(it);
 139                         design->modules_.erase(it);
 140                 }
 141         }
 142 } DeletePass;
 143
 144 PRIVATE_NAMESPACE_END