passes/cmds/design.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "frontends/verilog/preproc.h"
  22 #include "frontends/ast/ast.h"
  23
  24 YOSYS_NAMESPACE_BEGIN
  25
  26 std::map<std::string, RTLIL::Design*> saved_designs;
  27 std::vector<RTLIL::Design*> pushed_designs;
  28
  29 struct DesignPass : public Pass {
  30         DesignPass() : Pass("design", "save, restore and reset current design") { }
  31         ~DesignPass() YS_OVERRIDE {
  32                 for (auto &it : saved_designs)
  33                         delete it.second;
  34                 saved_designs.clear();
  35                 for (auto &it : pushed_designs)
  36                         delete it;
  37                 pushed_designs.clear();
  38         }
  39         void help() YS_OVERRIDE
  40         {
  41                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  42                 log("\n");
  43                 log("    design -reset\n");
  44                 log("\n");
  45                 log("Clear the current design.\n");
  46                 log("\n");
  47                 log("\n");
  48                 log("    design -save <name>\n");
  49                 log("\n");
  50                 log("Save the current design under the given name.\n");
  51                 log("\n");
  52                 log("\n");
  53                 log("    design -stash <name>\n");
  54                 log("\n");
  55                 log("Save the current design under the given name and then clear the current design.\n");
  56                 log("\n");
  57                 log("\n");
  58                 log("    design -push\n");
  59                 log("\n");
  60                 log("Push the current design to the stack and then clear the current design.\n");
  61                 log("\n");
  62                 log("\n");
  63                 log("    design -push-copy\n");
  64                 log("\n");
  65                 log("Push the current design to the stack without clearing the current design.\n");
  66                 log("\n");
  67                 log("\n");
  68                 log("    design -pop\n");
  69                 log("\n");
  70                 log("Reset the current design and pop the last design from the stack.\n");
  71                 log("\n");
  72                 log("\n");
  73                 log("    design -load <name>\n");
  74                 log("\n");
  75                 log("Reset the current design and load the design previously saved under the given\n");
  76                 log("name.\n");
  77                 log("\n");
  78                 log("\n");
  79                 log("    design -copy-from <name> [-as <new_mod_name>] <selection>\n");
  80                 log("\n");
  81                 log("Copy modules from the specified design into the current one. The selection is\n");
  82                 log("evaluated in the other design.\n");
  83                 log("\n");
  84                 log("\n");
  85                 log("    design -copy-to <name> [-as <new_mod_name>] [selection]\n");
  86                 log("\n");
  87                 log("Copy modules from the current design into the specified one.\n");
  88                 log("\n");
  89                 log("\n");
  90                 log("    design -import <name> [-as <new_top_name>] [selection]\n");
  91                 log("\n");
  92                 log("Import the specified design into the current design. The source design must\n");
  93                 log("either have a selected top module or the selection must contain exactly one\n");
  94                 log("module that is then used as top module for this command.\n");
  95                 log("\n");
  96                 log("\n");
  97                 log("    design -reset-vlog\n");
  98                 log("\n");
  99                 log("The Verilog front-end remembers defined macros and top-level declarations\n");
 100                 log("between calls to 'read_verilog'. This command resets this memory.\n");
 101                 log("\n");
 102                 log("    design -delete <name>\n");
 103                 log("\n");
 104                 log("Delete the design previously saved under the given name.\n");
 105                 log("\n");
 106
 107         }
 108         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 109         {
 110                 bool got_mode = false;
 111                 bool reset_mode = false;
 112                 bool reset_vlog_mode = false;
 113                 bool push_mode = false;
 114                 bool push_copy_mode = false;
 115                 bool pop_mode = false;
 116                 bool import_mode = false;
 117                 RTLIL::Design *copy_from_design = NULL, *copy_to_design = NULL;
 118                 std::string save_name, load_name, as_name, delete_name;
 119                 std::vector<RTLIL::Module*> copy_src_modules;
 120
 121                 size_t argidx;
 122                 for (argidx = 1; argidx < args.size(); argidx++)
 123                 {
 124                         std::string arg = args[argidx];
 125                         if (!got_mode && args[argidx] == "-reset") {
 126                                 got_mode = true;
 127                                 reset_mode = true;
 128                                 continue;
 129                         }
 130                         if (!got_mode && args[argidx] == "-reset-vlog") {
 131                                 got_mode = true;
 132                                 reset_vlog_mode = true;
 133                                 continue;
 134                         }
 135                         if (!got_mode && args[argidx] == "-push") {
 136                                 got_mode = true;
 137                                 push_mode = true;
 138                                 continue;
 139                         }
 140                         if (!got_mode && args[argidx] == "-push-copy") {
 141                                 got_mode = true;
 142                                 push_copy_mode = true;
 143                                 continue;
 144                         }
 145                         if (!got_mode && args[argidx] == "-pop") {
 146                                 got_mode = true;
 147                                 pop_mode = true;
 148                                 continue;
 149                         }
 150                         if (!got_mode && args[argidx] == "-save" && argidx+1 < args.size()) {
 151                                 got_mode = true;
 152                                 save_name = args[++argidx];
 153                                 continue;
 154                         }
 155                         if (!got_mode && args[argidx] == "-stash" && argidx+1 < args.size()) {
 156                                 got_mode = true;
 157                                 save_name = args[++argidx];
 158                                 reset_mode = true;
 159                                 continue;
 160                         }
 161                         if (!got_mode && args[argidx] == "-load" && argidx+1 < args.size()) {
 162                                 got_mode = true;
 163                                 load_name = args[++argidx];
 164                                 if (saved_designs.count(load_name) == 0)
 165                                         log_cmd_error("No saved design '%s' found!\n", load_name.c_str());
 166                                 continue;
 167                         }
 168                         if (!got_mode && args[argidx] == "-copy-from" && argidx+1 < args.size()) {
 169                                 got_mode = true;
 170                                 if (saved_designs.count(args[++argidx]) == 0)
 171                                         log_cmd_error("No saved design '%s' found!\n", args[argidx].c_str());
 172                                 copy_from_design = saved_designs.at(args[argidx]);
 173                                 copy_to_design = design;
 174                                 continue;
 175                         }
 176                         if (!got_mode && args[argidx] == "-copy-to" && argidx+1 < args.size()) {
 177                                 got_mode = true;
 178                                 if (saved_designs.count(args[++argidx]) == 0)
 179                                         saved_designs[args[argidx]] = new RTLIL::Design;
 180                                 copy_to_design = saved_designs.at(args[argidx]);
 181                                 copy_from_design = design;
 182                                 continue;
 183                         }
 184                         if (!got_mode && args[argidx] == "-import" && argidx+1 < args.size()) {
 185                                 got_mode = true;
 186                                 import_mode = true;
 187                                 if (saved_designs.count(args[++argidx]) == 0)
 188                                         log_cmd_error("No saved design '%s' found!\n", args[argidx].c_str());
 189                                 copy_from_design = saved_designs.at(args[argidx]);
 190                                 copy_to_design = design;
 191                                 as_name = args[argidx];
 192                                 continue;
 193                         }
 194                         if (copy_from_design != NULL && args[argidx] == "-as" && argidx+1 < args.size()) {
 195                                 as_name = args[++argidx];
 196                                 continue;
 197                         }
 198                         if (!got_mode && args[argidx] == "-delete" && argidx+1 < args.size()) {
 199                                 got_mode = true;
 200                                 delete_name = args[++argidx];
 201                                 if (saved_designs.count(delete_name) == 0)
 202                                         log_cmd_error("No saved design '%s' found!\n", delete_name.c_str());
 203                                 continue;
 204                         }
 205                         break;
 206                 }
 207
 208                 if (copy_from_design != NULL)
 209                 {
 210                         if (copy_from_design != design && argidx == args.size() && !import_mode)
 211                                 cmd_error(args, argidx, "Missing selection.");
 212
 213                         RTLIL::Selection sel;
 214                         if (argidx != args.size()) {
 215                                 handle_extra_select_args(this, args, argidx, args.size(), copy_from_design);
 216                                 sel = copy_from_design->selection_stack.back();
 217                                 copy_from_design->selection_stack.pop_back();
 218                                 argidx = args.size();
 219                         }
 220
 221                         for (auto mod : copy_from_design->modules()) {
 222                                 if (sel.selected_whole_module(mod->name)) {
 223                                         copy_src_modules.push_back(mod);
 224                                         continue;
 225                                 }
 226                                 if (sel.selected_module(mod->name))
 227                                         log_cmd_error("Module %s is only partly selected.\n", log_id(mod->name));
 228                         }
 229
 230                         if (import_mode) {
 231                                 std::vector<RTLIL::Module*> candidates;
 232                                 for (auto module : copy_src_modules)
 233                                 {
 234                                         if (module->get_bool_attribute(ID::top)) {
 235                                                 candidates.clear();
 236                                                 candidates.push_back(module);
 237                                                 break;
 238                                         }
 239                                         if (!module->get_blackbox_attribute())
 240                                                 candidates.push_back(module);
 241                                 }
 242
 243                                 if (GetSize(candidates) == 1)
 244                                         copy_src_modules = std::move(candidates);
 245                         }
 246                 }
 247
 248                 extra_args(args, argidx, design, false);
 249
 250                 if (!got_mode)
 251                         cmd_error(args, argidx, "Missing mode argument.");
 252
 253                 if (pop_mode && pushed_designs.empty())
 254                         log_cmd_error("No pushed designs.\n");
 255
 256                 if (import_mode)
 257                 {
 258                         std::string prefix = RTLIL::escape_id(as_name);
 259
 260                         pool<Module*> queue;
 261                         dict<IdString, IdString> done;
 262
 263                         if (copy_to_design->module(prefix) != nullptr)
 264                                 copy_to_design->remove(copy_to_design->module(prefix));
 265
 266                         if (GetSize(copy_src_modules) != 1)
 267                                 log_cmd_error("No top module found in source design.\n");
 268
 269                         for (auto mod : copy_src_modules)
 270                         {
 271                                 log("Importing %s as %s.\n", log_id(mod), log_id(prefix));
 272
 273                                 RTLIL::Module *t = mod->clone();
 274                                 t->name = prefix;
 275                                 t->design = copy_to_design;
 276                                 t->attributes.erase(ID::top);
 277                                 copy_to_design->add(t);
 278
 279                                 queue.insert(t);
 280                                 done[mod->name] = prefix;
 281                         }
 282
 283                         while (!queue.empty())
 284                         {
 285                                 pool<Module*> old_queue;
 286                                 old_queue.swap(queue);
 287
 288                                 for (auto mod : old_queue)
 289                                 for (auto cell : mod->cells())
 290                                 {
 291                                         Module *fmod = copy_from_design->module(cell->type);
 292
 293                                         if (fmod == nullptr)
 294                                                 continue;
 295
 296                                         if (done.count(cell->type) == 0)
 297                                         {
 298                                                 std::string trg_name = prefix + "." + (cell->type.c_str() + (*cell->type.c_str() == '\\'));
 299
 300                                                 log("Importing %s as %s.\n", log_id(fmod), log_id(trg_name));
 301
 302                                                 if (copy_to_design->module(trg_name) != nullptr)
 303                                                         copy_to_design->remove(copy_to_design->module(trg_name));
 304
 305                                                 RTLIL::Module *t = fmod->clone();
 306                                                 t->name = trg_name;
 307                                                 t->design = copy_to_design;
 308                                                 t->attributes.erase(ID::top);
 309                                                 copy_to_design->add(t);
 310
 311                                                 queue.insert(t);
 312                                                 done[cell->type] = trg_name;
 313                                         }
 314
 315                                         cell->type = done.at(cell->type);
 316                                 }
 317                         }
 318                 }
 319                 else
 320                 if (copy_to_design != NULL)
 321                 {
 322                         if (!as_name.empty() && copy_src_modules.size() > 1)
 323                                 log_cmd_error("Only one module can be selected in combination with -as.\n");
 324
 325                         for (auto mod : copy_src_modules)
 326                         {
 327                                 std::string trg_name = as_name.empty() ? mod->name.str() : RTLIL::escape_id(as_name);
 328
 329                                 if (copy_to_design->module(trg_name) != nullptr)
 330                                         copy_to_design->remove(copy_to_design->module(trg_name));
 331
 332                                 RTLIL::Module *t = mod->clone();
 333                                 t->name = trg_name;
 334                                 t->design = copy_to_design;
 335                                 copy_to_design->add(t);
 336                         }
 337                 }
 338
 339                 if (!save_name.empty() || push_mode || push_copy_mode)
 340                 {
 341                         RTLIL::Design *design_copy = new RTLIL::Design;
 342
 343                         for (auto mod : design->modules())
 344                                 design_copy->add(mod->clone());
 345
 346                         design_copy->selection_stack = design->selection_stack;
 347                         design_copy->selection_vars = design->selection_vars;
 348                         design_copy->selected_active_module = design->selected_active_module;
 349
 350                         if (saved_designs.count(save_name))
 351                                 delete saved_designs.at(save_name);
 352
 353                         if (push_mode || push_copy_mode)
 354                                 pushed_designs.push_back(design_copy);
 355                         else
 356                                 saved_designs[save_name] = design_copy;
 357                 }
 358
 359                 if (reset_mode || !load_name.empty() || push_mode || pop_mode)
 360                 {
 361                         for (auto mod : design->modules().to_vector())
 362                                 design->remove(mod);
 363
 364                         design->selection_stack.clear();
 365                         design->selection_vars.clear();
 366                         design->selected_active_module.clear();
 367
 368                         design->selection_stack.push_back(RTLIL::Selection());
 369                 }
 370
 371                 if (reset_mode || reset_vlog_mode || !load_name.empty() || push_mode || pop_mode)
 372                 {
 373                         for (auto node : design->verilog_packages)
 374                                 delete node;
 375                         design->verilog_packages.clear();
 376
 377                         for (auto node : design->verilog_globals)
 378                                 delete node;
 379                         design->verilog_globals.clear();
 380
 381                         design->verilog_defines->clear();
 382                 }
 383
 384                 if (!load_name.empty() || pop_mode)
 385                 {
 386                         RTLIL::Design *saved_design = pop_mode ? pushed_designs.back() : saved_designs.at(load_name);
 387
 388                         for (auto mod : saved_design->modules())
 389                                 design->add(mod->clone());
 390
 391                         design->selection_stack = saved_design->selection_stack;
 392                         design->selection_vars = saved_design->selection_vars;
 393                         design->selected_active_module = saved_design->selected_active_module;
 394
 395                         if (pop_mode) {
 396                                 delete saved_design;
 397                                 pushed_designs.pop_back();
 398                         }
 399                 }
 400
 401                 if (!delete_name.empty())
 402                 {
 403                         auto it = saved_designs.find(delete_name);
 404                         log_assert(it != saved_designs.end());
 405                         delete it->second;
 406                         saved_designs.erase(it);
 407                 }
 408         }
 409 } DesignPass;
 410
 411 YOSYS_NAMESPACE_END
 412