2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
24 PRIVATE_NAMESPACE_BEGIN
26 struct EdgetypePass
: public Pass
{
27 EdgetypePass() : Pass("edgetypes", "list all types of edges in selection") { }
28 void help() YS_OVERRIDE
30 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
32 log(" edgetypes [options] [selection]\n");
34 log("This command lists all unique types of 'edges' found in the selection. An 'edge'\n");
35 log("is a 4-tuple of source and sink cell type and port name.\n");
38 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
41 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
42 // if (args[argidx] == "-ltr") {
48 extra_args(args
, argidx
, design
);
50 pool
<string
> edge_cache
;
52 for (auto module
: design
->selected_modules())
54 SigMap
sigmap(module
);
55 dict
<SigBit
, pool
<tuple
<IdString
, IdString
, int>>> bit_sources
, bit_sinks
;
56 pool
<std::pair
<IdString
, IdString
>> multibit_ports
;
58 for (auto cell
: module
->selected_cells())
59 for (auto conn
: cell
->connections())
61 IdString cell_type
= cell
->type
;
62 IdString port_name
= conn
.first
;
63 SigSpec sig
= sigmap(conn
.second
);
66 multibit_ports
.insert(std::pair
<IdString
, IdString
>(cell_type
, port_name
));
68 for (int i
= 0; i
< GetSize(sig
); i
++) {
69 if (cell
->output(port_name
))
70 bit_sources
[sig
[i
]].insert(tuple
<IdString
, IdString
, int>(cell_type
, port_name
, i
));
71 if (cell
->input(port_name
))
72 bit_sinks
[sig
[i
]].insert(tuple
<IdString
, IdString
, int>(cell_type
, port_name
, i
));
76 for (auto &it
: bit_sources
)
77 for (auto &source
: it
.second
)
78 for (auto &sink
: bit_sinks
[it
.first
])
80 auto source_cell_type
= std::get
<0>(source
);
81 auto source_port_name
= std::get
<1>(source
);
82 auto source_bit_index
= std::get
<2>(source
);
84 auto sink_cell_type
= std::get
<0>(sink
);
85 auto sink_port_name
= std::get
<1>(sink
);
86 auto sink_bit_index
= std::get
<2>(sink
);
88 string source_str
= multibit_ports
.count(std::pair
<IdString
, IdString
>(source_cell_type
, source_port_name
)) ?
89 stringf("%s.%s[%d]", log_id(source_cell_type
), log_id(source_port_name
), source_bit_index
) :
90 stringf("%s.%s", log_id(source_cell_type
), log_id(source_port_name
));
92 string sink_str
= multibit_ports
.count(std::pair
<IdString
, IdString
>(sink_cell_type
, sink_port_name
)) ?
93 stringf("%s.%s[%d]", log_id(sink_cell_type
), log_id(sink_port_name
), sink_bit_index
) :
94 stringf("%s.%s", log_id(sink_cell_type
), log_id(sink_port_name
));
96 edge_cache
.insert(source_str
+ " " + sink_str
);
101 for (auto &str
: edge_cache
)
102 log("%s\n", str
.c_str());
106 PRIVATE_NAMESPACE_END