passes/cmds/portlist.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/sigtools.h"
  22
  23 USING_YOSYS_NAMESPACE
  24 PRIVATE_NAMESPACE_BEGIN
  25
  26 struct PortlistPass : public Pass {
  27         PortlistPass() : Pass("portlist", "list (top-level) ports") { }
  28         void help() YS_OVERRIDE
  29         {
  30                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  31                 log("\n");
  32                 log("    portlist [options] [selection]\n");
  33                 log("\n");
  34                 log("This command lists all module ports found in the selected modules.\n");
  35                 log("\n");
  36                 log("If no selection is provided then it lists the ports on the top module.\n");
  37                 log("\n");
  38                 log("  -m\n");
  39                 log("    print verilog blackbox module definitions instead of port lists\n");
  40                 log("\n");
  41         }
  42         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  43         {
  44                 bool m_mode = false;
  45
  46                 size_t argidx;
  47                 for (argidx = 1; argidx < args.size(); argidx++) {
  48                         if (args[argidx] == "-m") {
  49                                 m_mode = true;
  50                                 continue;
  51                         }
  52                         break;
  53                 }
  54
  55                 bool first_module = true;
  56
  57                 auto handle_module = [&](RTLIL::Module *module) {
  58                         vector<string> ports;
  59                         if (first_module)
  60                                 first_module = false;
  61                         else
  62                                 log("\n");
  63                         for (auto port : module->ports) {
  64                                 auto *w = module->wire(port);
  65                                 ports.push_back(stringf("%s [%d:%d] %s", w->port_input ? w->port_output ? "inout" : "input" : "output",
  66                                                 w->upto ? w->start_offset : w->start_offset + w->width - 1,
  67                                                 w->upto ? w->start_offset + w->width - 1 : w->start_offset,
  68                                                 log_id(w)));
  69                         }
  70                         log("module %s%s\n", log_id(module), m_mode ? " (" : "");
  71                         for (int i = 0; i < GetSize(ports); i++)
  72                                 log("%s%s\n", ports[i].c_str(), m_mode && i+1 < GetSize(ports) ? "," : "");
  73                         if (m_mode)
  74                                 log(");\nendmodule\n");
  75                 };
  76
  77                 if (argidx == args.size())
  78                 {
  79                         auto *top = design->top_module();
  80                         if (top == nullptr)
  81                                 log_cmd_error("Can't find top module in current design!\n");
  82                         handle_module(top);
  83                 }
  84                 else
  85                 {
  86                         extra_args(args, argidx, design);
  87                         for (auto module : design->selected_modules())
  88                                 handle_module(module);
  89                 }
  90         }
  91 } PortlistPass;
  92
  93 PRIVATE_NAMESPACE_END