2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
24 PRIVATE_NAMESPACE_BEGIN
26 struct PortlistPass
: public Pass
{
27 PortlistPass() : Pass("portlist", "list (top-level) ports") { }
28 void help() YS_OVERRIDE
30 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
32 log(" portlist [options] [selection]\n");
34 log("This command lists all module ports found in the selected modules.\n");
36 log("If no selection is provided then it lists the ports on the top module.\n");
39 log(" print verilog blackbox module definitions instead of port lists\n");
42 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
47 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
48 if (args
[argidx
] == "-m") {
55 bool first_module
= true;
57 auto handle_module
= [&](RTLIL::Module
*module
) {
63 for (auto port
: module
->ports
) {
64 auto *w
= module
->wire(port
);
65 ports
.push_back(stringf("%s [%d:%d] %s", w
->port_input
? w
->port_output
? "inout" : "input" : "output",
66 w
->upto
? w
->start_offset
: w
->start_offset
+ w
->width
- 1,
67 w
->upto
? w
->start_offset
+ w
->width
- 1 : w
->start_offset
,
70 log("module %s%s\n", log_id(module
), m_mode
? " (" : "");
71 for (int i
= 0; i
< GetSize(ports
); i
++)
72 log("%s%s\n", ports
[i
].c_str(), m_mode
&& i
+1 < GetSize(ports
) ? "," : "");
74 log(");\nendmodule\n");
77 if (argidx
== args
.size())
79 auto *top
= design
->top_module();
81 log_cmd_error("Can't find top module in current design!\n");
86 extra_args(args
, argidx
, design
);
87 for (auto module
: design
->selected_modules())
88 handle_module(module
);