2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2020 Alberto Gonzalez <boqwxp@airmail.cc>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
23 PRIVATE_NAMESPACE_BEGIN
25 struct PrintAttrsPass
: public Pass
{
26 PrintAttrsPass() : Pass("printattrs", "print attributes of selected objects") { }
27 void help() YS_OVERRIDE
29 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
31 log(" printattrs [selection]\n");
33 log("Print all attributes of the selected objects.\n");
37 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
40 extra_args(args
, argidx
, design
);
42 unsigned int indent
= 0;
43 for (auto mod
: design
->selected_modules())
46 if (design
->selected_whole_module(mod
)) {
47 log("%s%s\n", stringf(stringf("%%%ds", indent
).c_str(), " ").c_str(), log_id(mod
->name
));
49 for (auto &it
: mod
->attributes
)
50 log("%s(* %s=\"%s\" %s *)\n", stringf(stringf("%%%ds", indent
).c_str(), " ").c_str(), log_id(it
.first
), it
.second
.decode_string().c_str(), it
.second
.as_string().c_str());
53 for (auto cell
: mod
->selected_cells()) {
54 log("%s%s\n", stringf(stringf("%%%ds", indent
).c_str(), " ").c_str(), log_id(cell
->name
));
56 for (auto &it
: cell
->attributes
) {
57 log("%s(* %s=\"%s\" %s *)\n", stringf(stringf("%%%ds", indent
).c_str(), " ").c_str(), log_id(it
.first
), it
.second
.decode_string().c_str(), it
.second
.as_string().c_str());
62 for (auto wire
: mod
->selected_wires()) {
63 log("%s%s\n", stringf(stringf("%%%ds", indent
).c_str(), " ").c_str(), log_id(wire
->name
));
65 for (auto &it
: wire
->attributes
) {
66 log("%s(* %s=\"%s\" %s *)\n", stringf(stringf("%%%ds", indent
).c_str(), " ").c_str(), log_id(it
.first
), it
.second
.decode_string().c_str(), it
.second
.as_string().c_str());
71 if (design
->selected_whole_module(mod
))