misc: Add `printattrs` command.
[yosys.git] / passes / cmds / printattrs.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2020 Alberto Gonzalez <boqwxp@airmail.cc>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21
22 USING_YOSYS_NAMESPACE
23 PRIVATE_NAMESPACE_BEGIN
24
25 struct PrintAttrsPass : public Pass {
26 PrintAttrsPass() : Pass("printattrs", "print attributes of selected objects") { }
27 void help() YS_OVERRIDE
28 {
29 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
30 log("\n");
31 log(" printattrs [selection]\n");
32 log("\n");
33 log("Print all attributes of the selected objects.\n");
34 log("\n");
35 log("\n");
36 }
37 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
38 {
39 size_t argidx = 1;
40 extra_args(args, argidx, design);
41
42 unsigned int indent = 0;
43 for (auto mod : design->selected_modules())
44 {
45
46 if (design->selected_whole_module(mod)) {
47 log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(mod->name));
48 indent += 2;
49 for (auto &it : mod->attributes)
50 log("%s(* %s=\"%s\" %s *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(it.first), it.second.decode_string().c_str(), it.second.as_string().c_str());
51 }
52
53 for (auto cell : mod->selected_cells()) {
54 log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(cell->name));
55 indent += 2;
56 for (auto &it : cell->attributes) {
57 log("%s(* %s=\"%s\" %s *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(it.first), it.second.decode_string().c_str(), it.second.as_string().c_str());
58 }
59 indent -= 2;
60 }
61
62 for (auto wire : mod->selected_wires()) {
63 log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(wire->name));
64 indent += 2;
65 for (auto &it : wire->attributes) {
66 log("%s(* %s=\"%s\" %s *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(it.first), it.second.decode_string().c_str(), it.second.as_string().c_str());
67 }
68 indent -= 2;
69 }
70
71 if (design->selected_whole_module(mod))
72 indent -= 2;
73 }
74
75 log("\n");
76 }
77 } PrintAttrsPass;
78
79 PRIVATE_NAMESPACE_END