passes/cmds/printattrs.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2020  Alberto Gonzalez <boqwxp@airmail.cc>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21
  22 USING_YOSYS_NAMESPACE
  23 PRIVATE_NAMESPACE_BEGIN
  24
  25 struct PrintAttrsPass : public Pass {
  26         PrintAttrsPass() : Pass("printattrs", "print attributes of selected objects") { }
  27         void help() YS_OVERRIDE
  28         {
  29                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  30                 log("\n");
  31                 log("    printattrs [selection]\n");
  32                 log("\n");
  33                 log("Print all attributes of the selected objects.\n");
  34                 log("\n");
  35                 log("\n");
  36         }
  37
  38         static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) {
  39                 if (x.flags == RTLIL::CONST_FLAG_STRING)
  40                         log("%s(* %s=\"%s\" *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(s), x.decode_string().c_str());
  41                 else if (x.flags == RTLIL::CONST_FLAG_NONE)
  42                         log("%s(* %s=%s *)\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(s), x.as_string().c_str());
  43                 else
  44                         log_assert(x.flags == RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
  45         }
  46
  47         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  48         {
  49                 size_t argidx = 1;
  50                 extra_args(args, argidx, design);
  51
  52                 unsigned int indent = 0;
  53                 for (auto mod : design->selected_modules())
  54                 {
  55                         if (design->selected_whole_module(mod)) {
  56                                 log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(mod->name));
  57                                 indent += 2;
  58                                 for (auto &it : mod->attributes)
  59                                         log_const(it.first, it.second, indent);
  60                         }
  61
  62                         for (auto cell : mod->selected_cells()) {
  63                                 log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(cell->name));
  64                                 indent += 2;
  65                                 for (auto &it : cell->attributes)
  66                                         log_const(it.first, it.second, indent);
  67                                 indent -= 2;
  68                         }
  69
  70                         for (auto wire : mod->selected_wires()) {
  71                                 log("%s%s\n", stringf(stringf("%%%ds", indent).c_str(), " ").c_str(), log_id(wire->name));
  72                                 indent += 2;
  73                                 for (auto &it : wire->attributes)
  74                                         log_const(it.first, it.second, indent);
  75                                 indent -= 2;
  76                         }
  77
  78                         if (design->selected_whole_module(mod))
  79                                 indent -= 2;
  80                 }
  81
  82                 log("\n");
  83         }
  84 } PrintAttrsPass;
  85
  86 PRIVATE_NAMESPACE_END