passes/cmds/rename.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/rtlil.h"
  22 #include "kernel/log.h"
  23
  24 USING_YOSYS_NAMESPACE
  25 PRIVATE_NAMESPACE_BEGIN
  26
  27 static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name)
  28 {
  29         from_name = RTLIL::escape_id(from_name);
  30         to_name = RTLIL::escape_id(to_name);
  31
  32         if (module->count_id(to_name))
  33                 log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str());
  34
  35         for (auto &it : module->wires_)
  36                 if (it.first == from_name) {
  37                         Wire *w = it.second;
  38                         log("Renaming wire %s to %s in module %s.\n", log_id(w), log_id(to_name), log_id(module));
  39                         module->rename(w, to_name);
  40                         if (w->port_id)
  41                                 module->fixup_ports();
  42                         return;
  43                 }
  44
  45         for (auto &it : module->cells_)
  46                 if (it.first == from_name) {
  47                         log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
  48                         module->rename(it.second, to_name);
  49                         return;
  50                 }
  51
  52         log_cmd_error("Object `%s' not found!\n", from_name.c_str());
  53 }
  54
  55 struct RenamePass : public Pass {
  56         RenamePass() : Pass("rename", "rename object in the design") { }
  57         virtual void help()
  58         {
  59                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  60                 log("\n");
  61                 log("    rename old_name new_name\n");
  62                 log("\n");
  63                 log("Rename the specified object. Note that selection patterns are not supported\n");
  64                 log("by this command.\n");
  65                 log("\n");
  66                 log("\n");
  67                 log("    rename -enumerate [-pattern <pattern>] [selection]\n");
  68                 log("\n");
  69                 log("Assign short auto-generated names to all selected wires and cells with private\n");
  70                 log("names. The -pattern option can be used to set the pattern for the new names.\n");
  71                 log("The character %% in the pattern is replaced with a integer number. The default\n");
  72                 log("pattern is '_%%_'.\n");
  73                 log("\n");
  74                 log("    rename -hide [selection]\n");
  75                 log("\n");
  76                 log("Assign private names (the ones with $-prefix) to all selected wires and cells\n");
  77                 log("with public names. This ignores all selected ports.\n");
  78                 log("\n");
  79                 log("    rename -top new_name\n");
  80                 log("\n");
  81                 log("Rename top module.\n");
  82                 log("\n");
  83         }
  84         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
  85         {
  86                 std::string pattern_prefix = "_", pattern_suffix = "_";
  87                 bool flag_enumerate = false;
  88                 bool flag_hide = false;
  89                 bool flag_top = false;
  90                 bool got_mode = false;
  91
  92                 size_t argidx;
  93                 for (argidx = 1; argidx < args.size(); argidx++)
  94                 {
  95                         std::string arg = args[argidx];
  96                         if (arg == "-enumerate" && !got_mode) {
  97                                 flag_enumerate = true;
  98                                 got_mode = true;
  99                                 continue;
 100                         }
 101                         if (arg == "-hide" && !got_mode) {
 102                                 flag_hide = true;
 103                                 got_mode = true;
 104                                 continue;
 105                         }
 106                         if (arg == "-top" && !got_mode) {
 107                                 flag_top = true;
 108                                 got_mode = true;
 109                                 continue;
 110                         }
 111                         if (arg == "-pattern" && argidx+1 < args.size() && args[argidx+1].find('%') != std::string::npos) {
 112                                 int pos = args[++argidx].find('%');
 113                                 pattern_prefix = args[argidx].substr(0, pos);
 114                                 pattern_suffix = args[argidx].substr(pos+1);
 115                                 continue;
 116                         }
 117                         break;
 118                 }
 119
 120                 if (flag_enumerate)
 121                 {
 122                         extra_args(args, argidx, design);
 123
 124                         for (auto &mod : design->modules_)
 125                         {
 126                                 int counter = 0;
 127
 128                                 RTLIL::Module *module = mod.second;
 129                                 if (!design->selected(module))
 130                                         continue;
 131
 132                                 dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
 133                                 for (auto &it : module->wires_) {
 134                                         if (it.first[0] == '$' && design->selected(module, it.second))
 135                                                 do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
 136                                                 while (module->count_id(it.second->name) > 0);
 137                                         new_wires[it.second->name] = it.second;
 138                                 }
 139                                 module->wires_.swap(new_wires);
 140                                 module->fixup_ports();
 141
 142                                 dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
 143                                 for (auto &it : module->cells_) {
 144                                         if (it.first[0] == '$' && design->selected(module, it.second))
 145                                                 do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
 146                                                 while (module->count_id(it.second->name) > 0);
 147                                         new_cells[it.second->name] = it.second;
 148                                 }
 149                                 module->cells_.swap(new_cells);
 150                         }
 151                 }
 152                 else
 153                 if (flag_hide)
 154                 {
 155                         extra_args(args, argidx, design);
 156
 157                         for (auto &mod : design->modules_)
 158                         {
 159                                 RTLIL::Module *module = mod.second;
 160                                 if (!design->selected(module))
 161                                         continue;
 162
 163                                 dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
 164                                 for (auto &it : module->wires_) {
 165                                         if (design->selected(module, it.second))
 166                                                 if (it.first[0] == '\\' && it.second->port_id == 0)
 167                                                         it.second->name = NEW_ID;
 168                                         new_wires[it.second->name] = it.second;
 169                                 }
 170                                 module->wires_.swap(new_wires);
 171                                 module->fixup_ports();
 172
 173                                 dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
 174                                 for (auto &it : module->cells_) {
 175                                         if (design->selected(module, it.second))
 176                                                 if (it.first[0] == '\\')
 177                                                         it.second->name = NEW_ID;
 178                                         new_cells[it.second->name] = it.second;
 179                                 }
 180                                 module->cells_.swap(new_cells);
 181                         }
 182                 }
 183                 else
 184                 if (flag_top)
 185                 {
 186                         if (argidx+1 != args.size())
 187                                 log_cmd_error("Invalid number of arguments!\n");
 188
 189                         IdString new_name = RTLIL::escape_id(args[argidx]);
 190                         RTLIL::Module *module = design->top_module();
 191
 192                         if (module == NULL)
 193                                 log_cmd_error("No top module found!\n");
 194
 195                         log("Renaming module %s to %s.\n", log_id(module), log_id(new_name));
 196                         design->rename(module, new_name);
 197                 }
 198                 else
 199                 {
 200                         if (argidx+2 != args.size())
 201                                 log_cmd_error("Invalid number of arguments!\n");
 202
 203                         std::string from_name = args[argidx++];
 204                         std::string to_name = args[argidx++];
 205
 206                         if (!design->selected_active_module.empty())
 207                         {
 208                                 if (design->modules_.count(design->selected_active_module) > 0)
 209                                         rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name);
 210                         }
 211                         else
 212                         {
 213                                 for (auto &mod : design->modules_) {
 214                                         if (mod.first == from_name || RTLIL::unescape_id(mod.first) == from_name) {
 215                                                 to_name = RTLIL::escape_id(to_name);
 216                                                 log("Renaming module %s to %s.\n", mod.first.c_str(), to_name.c_str());
 217                                                 RTLIL::Module *module = mod.second;
 218                                                 design->modules_.erase(module->name);
 219                                                 module->name = to_name;
 220                                                 design->modules_[module->name] = module;
 221                                                 goto rename_ok;
 222                                         }
 223                                 }
 224
 225                                 log_cmd_error("Object `%s' not found!\n", from_name.c_str());
 226                         rename_ok:;
 227                         }
 228                 }
 229         }
 230 } RenamePass;
 231
 232 PRIVATE_NAMESPACE_END