passes/cmds/rename.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/rtlil.h"
  22 #include "kernel/log.h"
  23
  24 USING_YOSYS_NAMESPACE
  25 PRIVATE_NAMESPACE_BEGIN
  26
  27 static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name, bool flag_output)
  28 {
  29         from_name = RTLIL::escape_id(from_name);
  30         to_name = RTLIL::escape_id(to_name);
  31
  32         if (module->count_id(to_name))
  33                 log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str());
  34
  35         RTLIL::Wire *wire_to_rename = module->wire(from_name);
  36         RTLIL::Cell *cell_to_rename = module->cell(from_name);
  37
  38         if (wire_to_rename != nullptr) {
  39                 log("Renaming wire %s to %s in module %s.\n", log_id(wire_to_rename), log_id(to_name), log_id(module));
  40                 module->rename(wire_to_rename, to_name);
  41                 if (wire_to_rename->port_id || flag_output) {
  42                         if (flag_output)
  43                                 wire_to_rename->port_output = true;
  44                         module->fixup_ports();
  45                 }
  46                 return;
  47         }
  48
  49         if (cell_to_rename != nullptr) {
  50                 if (flag_output)
  51                         log_cmd_error("Called with -output but the specified object is a cell.\n");
  52                 log("Renaming cell %s to %s in module %s.\n", log_id(cell_to_rename), log_id(to_name), log_id(module));
  53                 module->rename(cell_to_rename, to_name);
  54                 return;
  55         }
  56
  57         log_cmd_error("Object `%s' not found!\n", from_name.c_str());
  58 }
  59
  60 static std::string derive_name_from_src(const std::string &src, int counter)
  61 {
  62         std::string src_base = src.substr(0, src.find('|'));
  63         if (src_base.empty())
  64                 return stringf("$%d", counter);
  65         else
  66                 return stringf("\\%s$%d", src_base.c_str(), counter);
  67 }
  68
  69 static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell)
  70 {
  71         // Find output
  72         const SigSpec *output = nullptr;
  73         int num_outputs = 0;
  74         for (auto &connection : cell->connections()) {
  75                 if (cell->output(connection.first)) {
  76                         output = &connection.second;
  77                         num_outputs++;
  78                 }
  79         }
  80
  81         if (num_outputs != 1) // Skip cells thad drive multiple outputs
  82                 return cell->name;
  83
  84         std::string name = "";
  85         for (auto &chunk : output->chunks()) {
  86                 // Skip cells that drive privately named wires
  87                 if (!chunk.wire || chunk.wire->name.str()[0] == '$')
  88                         return cell->name;
  89
  90                 if (name != "")
  91                         name += "$";
  92
  93                 name += chunk.wire->name.str();
  94                 if (chunk.wire->width != chunk.width) {
  95                         name += "[";
  96                         if (chunk.width != 1)
  97                                 name += std::to_string(chunk.offset + chunk.width) + ":";
  98                         name += std::to_string(chunk.offset) + "]";
  99                 }
 100         }
 101
 102         return name + cell->type.str();
 103 }
 104
 105 struct RenamePass : public Pass {
 106         RenamePass() : Pass("rename", "rename object in the design") { }
 107         void help() override
 108         {
 109                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 110                 log("\n");
 111                 log("    rename old_name new_name\n");
 112                 log("\n");
 113                 log("Rename the specified object. Note that selection patterns are not supported\n");
 114                 log("by this command.\n");
 115                 log("\n");
 116                 log("\n");
 117                 log("\n");
 118                 log("    rename -output old_name new_name\n");
 119                 log("\n");
 120                 log("Like above, but also make the wire an output. This will fail if the object is\n");
 121                 log("not a wire.\n");
 122                 log("\n");
 123                 log("\n");
 124                 log("    rename -src [selection]\n");
 125                 log("\n");
 126                 log("Assign names auto-generated from the src attribute to all selected wires and\n");
 127                 log("cells with private names.\n");
 128                 log("\n");
 129                 log("\n");
 130                 log("    rename -wire [selection]\n");
 131                 log("\n");
 132                 log("Assign auto-generated names based on the wires they drive to all selected\n");
 133                 log("cells with private names. Ignores cells driving privatly named wires.\n");
 134                 log("\n");
 135                 log("\n");
 136                 log("    rename -enumerate [-pattern <pattern>] [selection]\n");
 137                 log("\n");
 138                 log("Assign short auto-generated names to all selected wires and cells with private\n");
 139                 log("names. The -pattern option can be used to set the pattern for the new names.\n");
 140                 log("The character %% in the pattern is replaced with a integer number. The default\n");
 141                 log("pattern is '_%%_'.\n");
 142                 log("\n");
 143                 log("\n");
 144                 log("    rename -hide [selection]\n");
 145                 log("\n");
 146                 log("Assign private names (the ones with $-prefix) to all selected wires and cells\n");
 147                 log("with public names. This ignores all selected ports.\n");
 148                 log("\n");
 149                 log("\n");
 150                 log("    rename -top new_name\n");
 151                 log("\n");
 152                 log("Rename top module.\n");
 153                 log("\n");
 154         }
 155         void execute(std::vector<std::string> args, RTLIL::Design *design) override
 156         {
 157                 std::string pattern_prefix = "_", pattern_suffix = "_";
 158                 bool flag_src = false;
 159                 bool flag_wire = false;
 160                 bool flag_enumerate = false;
 161                 bool flag_hide = false;
 162                 bool flag_top = false;
 163                 bool flag_output = false;
 164                 bool got_mode = false;
 165
 166                 size_t argidx;
 167                 for (argidx = 1; argidx < args.size(); argidx++)
 168                 {
 169                         std::string arg = args[argidx];
 170                         if (arg == "-src" && !got_mode) {
 171                                 flag_src = true;
 172                                 got_mode = true;
 173                                 continue;
 174                         }
 175                         if (arg == "-output" && !got_mode) {
 176                                 flag_output = true;
 177                                 got_mode = true;
 178                                 continue;
 179                         }
 180                         if (arg == "-wire" && !got_mode) {
 181                                 flag_wire = true;
 182                                 got_mode = true;
 183                                 continue;
 184                         }
 185                         if (arg == "-enumerate" && !got_mode) {
 186                                 flag_enumerate = true;
 187                                 got_mode = true;
 188                                 continue;
 189                         }
 190                         if (arg == "-hide" && !got_mode) {
 191                                 flag_hide = true;
 192                                 got_mode = true;
 193                                 continue;
 194                         }
 195                         if (arg == "-top" && !got_mode) {
 196                                 flag_top = true;
 197                                 got_mode = true;
 198                                 continue;
 199                         }
 200                         if (arg == "-pattern" && argidx+1 < args.size() && args[argidx+1].find('%') != std::string::npos) {
 201                                 int pos = args[++argidx].find('%');
 202                                 pattern_prefix = args[argidx].substr(0, pos);
 203                                 pattern_suffix = args[argidx].substr(pos+1);
 204                                 continue;
 205                         }
 206                         break;
 207                 }
 208
 209                 if (flag_src)
 210                 {
 211                         extra_args(args, argidx, design);
 212
 213                         for (auto module : design->selected_modules())
 214                         {
 215                                 int counter = 0;
 216                                 dict<RTLIL::Wire *, IdString> new_wire_names;
 217                                 dict<RTLIL::Cell *, IdString> new_cell_names;
 218
 219                                 for (auto wire : module->selected_wires())
 220                                         if (wire->name[0] == '$')
 221                                                 new_wire_names.emplace(wire, derive_name_from_src(wire->get_src_attribute(), counter++));
 222
 223                                 for (auto cell : module->selected_cells())
 224                                         if (cell->name[0] == '$')
 225                                                 new_cell_names.emplace(cell, derive_name_from_src(cell->get_src_attribute(), counter++));
 226
 227                                 for (auto &it : new_wire_names)
 228                                         module->rename(it.first, it.second);
 229
 230                                 for (auto &it : new_cell_names)
 231                                         module->rename(it.first, it.second);
 232                         }
 233                 }
 234                 else
 235                 if (flag_wire)
 236                 {
 237                         extra_args(args, argidx, design);
 238
 239                         for (auto module : design->selected_modules()) {
 240                                 dict<RTLIL::Cell *, IdString> new_cell_names;
 241                                 for (auto cell : module->selected_cells())
 242                                         if (cell->name[0] == '$')
 243                                                 new_cell_names[cell] = derive_name_from_cell_output_wire(cell);
 244                                 for (auto &it : new_cell_names)
 245                                         module->rename(it.first, it.second);
 246                         }
 247                 }
 248                 else
 249                 if (flag_enumerate)
 250                 {
 251                         extra_args(args, argidx, design);
 252
 253                         for (auto module : design->selected_modules())
 254                         {
 255                                 int counter = 0;
 256                                 dict<RTLIL::Wire *, IdString> new_wire_names;
 257                                 dict<RTLIL::Cell *, IdString> new_cell_names;
 258
 259                                 for (auto wire : module->selected_wires())
 260                                         if (wire->name[0] == '$') {
 261                                                 RTLIL::IdString buf;
 262                                                 do buf = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
 263                                                 while (module->wire(buf) != nullptr);
 264                                                 new_wire_names[wire] = buf;
 265                                         }
 266
 267                                 for (auto cell : module->selected_cells())
 268                                         if (cell->name[0] == '$') {
 269                                                 RTLIL::IdString buf;
 270                                                 do buf = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
 271                                                 while (module->cell(buf) != nullptr);
 272                                                 new_cell_names[cell] = buf;
 273                                         }
 274
 275                                 for (auto &it : new_wire_names)
 276                                         module->rename(it.first, it.second);
 277
 278                                 for (auto &it : new_cell_names)
 279                                         module->rename(it.first, it.second);
 280                         }
 281                 }
 282                 else
 283                 if (flag_hide)
 284                 {
 285                         extra_args(args, argidx, design);
 286
 287                         for (auto module : design->selected_modules())
 288                         {
 289                                 dict<RTLIL::Wire *, IdString> new_wire_names;
 290                                 dict<RTLIL::Cell *, IdString> new_cell_names;
 291
 292                                 for (auto wire : module->selected_wires())
 293                                         if (wire->name.isPublic() && wire->port_id == 0)
 294                                                 new_wire_names[wire] = NEW_ID;
 295
 296                                 for (auto cell : module->selected_cells())
 297                                         if (cell->name.isPublic())
 298                                                 new_cell_names[cell] = NEW_ID;
 299
 300                                 for (auto &it : new_wire_names)
 301                                         module->rename(it.first, it.second);
 302
 303                                 for (auto &it : new_cell_names)
 304                                         module->rename(it.first, it.second);
 305                         }
 306                 }
 307                 else
 308                 if (flag_top)
 309                 {
 310                         if (argidx+1 != args.size())
 311                                 log_cmd_error("Invalid number of arguments!\n");
 312
 313                         IdString new_name = RTLIL::escape_id(args[argidx]);
 314                         RTLIL::Module *module = design->top_module();
 315
 316                         if (module == nullptr)
 317                                 log_cmd_error("No top module found!\n");
 318
 319                         log("Renaming module %s to %s.\n", log_id(module), log_id(new_name));
 320                         design->rename(module, new_name);
 321                 }
 322                 else
 323                 {
 324                         if (argidx+2 != args.size())
 325                                 log_cmd_error("Invalid number of arguments!\n");
 326
 327                         std::string from_name = args[argidx++];
 328                         std::string to_name = args[argidx++];
 329
 330                         if (!design->selected_active_module.empty())
 331                         {
 332                                 if (design->module(design->selected_active_module) != nullptr)
 333                                         rename_in_module(design->module(design->selected_active_module), from_name, to_name, flag_output);
 334                         }
 335                         else
 336                         {
 337                                 if (flag_output)
 338                                         log_cmd_error("Mode -output requires that there is an active module selected.\n");
 339
 340                                 RTLIL::Module *module_to_rename = nullptr;
 341                                 for (auto module : design->modules())
 342                                         if (module->name == from_name || RTLIL::unescape_id(module->name) == from_name) {
 343                                                 module_to_rename = module;
 344                                                 break;
 345                                         }
 346
 347                                 if (module_to_rename != nullptr) {
 348                                         to_name = RTLIL::escape_id(to_name);
 349                                         log("Renaming module %s to %s.\n", module_to_rename->name.c_str(), to_name.c_str());
 350                                         design->rename(module_to_rename, to_name);
 351                                 } else
 352                                         log_cmd_error("Object `%s' not found!\n", from_name.c_str());
 353                         }
 354                 }
 355         }
 356 } RenamePass;
 357
 358 PRIVATE_NAMESPACE_END