2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 struct ScatterPass
: public Pass
{
29 ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
30 void help() YS_OVERRIDE
32 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
34 log(" scatter [selection]\n");
36 log("This command adds additional intermediate nets on all cell ports. This is used\n");
37 log("for testing the correct use of the SigMap helper in passes. If you don't know\n");
38 log("what this means: don't worry -- you only need this pass when testing your own\n");
39 log("extensions to Yosys.\n");
41 log("Use the opt_clean command to get rid of the additional nets.\n");
44 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
47 extra_args(args
, 1, design
);
49 for (auto &mod_it
: design
->modules_
)
51 if (!design
->selected(mod_it
.second
))
54 for (auto &c
: mod_it
.second
->cells_
)
55 for (auto &p
: c
.second
->connections_
)
57 RTLIL::Wire
*wire
= mod_it
.second
->addWire(NEW_ID
, p
.second
.size());
59 if (ct
.cell_output(c
.second
->type
, p
.first
)) {
60 RTLIL::SigSig
sigsig(p
.second
, wire
);
61 mod_it
.second
->connect(sigsig
);
63 RTLIL::SigSig
sigsig(wire
, p
.second
);
64 mod_it
.second
->connect(sigsig
);