passes/cmds/scatter.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 struct ScatterPass : public Pass {
  26         ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
  27         virtual void help()
  28         {
  29                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  30                 log("\n");
  31                 log("    scatter [selection]\n");
  32                 log("\n");
  33                 log("This command adds additional intermediate nets on all cell ports. This is used\n");
  34                 log("for testing the correct use of the SigMap helper in passes. If you don't know\n");
  35                 log("what this means: don't worry -- you only need this pass when testing your own\n");
  36                 log("extensions to Yosys.\n");
  37                 log("\n");
  38                 log("Use the opt_clean command to get rid of the additional nets.\n");
  39                 log("\n");
  40         }
  41         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
  42         {
  43                 CellTypes ct(design);
  44                 extra_args(args, 1, design);
  45
  46                 for (auto &mod_it : design->modules)
  47                 {
  48                         if (!design->selected(mod_it.second))
  49                                 continue;
  50
  51                         for (auto &c : mod_it.second->cells)
  52                         for (auto &p : c.second->connections)
  53                         {
  54                                 RTLIL::Wire *wire = new RTLIL::Wire;
  55                                 wire->name = NEW_ID;
  56                                 wire->width = p.second.width;
  57                                 mod_it.second->add(wire);
  58
  59                                 if (ct.cell_output(c.second->type, p.first)) {
  60                                         RTLIL::SigSig sigsig(p.second, wire);
  61                                         mod_it.second->connections.push_back(sigsig);
  62                                 } else {
  63                                         RTLIL::SigSig sigsig(wire, p.second);
  64                                         mod_it.second->connections.push_back(sigsig);
  65                                 }
  66
  67                                 p.second = wire;
  68                         }
  69                 }
  70         }
  71 } ScatterPass;
  72