2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 struct ScatterPass
: public Pass
{
29 ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
32 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
34 log(" scatter [selection]\n");
36 log("This command adds additional intermediate nets on all cell ports. This is used\n");
37 log("for testing the correct use of the SigMap helper in passes. If you don't know\n");
38 log("what this means: don't worry -- you only need this pass when testing your own\n");
39 log("extensions to Yosys.\n");
41 log("Use the opt_clean command to get rid of the additional nets.\n");
44 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) override
47 extra_args(args
, 1, design
);
49 for (auto module
: design
->selected_modules())
51 for (auto cell
: module
->cells()) {
52 dict
<RTLIL::IdString
, RTLIL::SigSig
> new_connections
;
53 for (auto conn
: cell
->connections())
54 new_connections
.emplace(conn
.first
, RTLIL::SigSig(conn
.second
, module
->addWire(NEW_ID
, GetSize(conn
.second
))));
55 for (auto &it
: new_connections
) {
56 if (ct
.cell_output(cell
->type
, it
.first
))
57 module
->connect(RTLIL::SigSig(it
.second
.first
, it
.second
.second
));
59 module
->connect(RTLIL::SigSig(it
.second
.second
, it
.second
.first
));
60 cell
->setPort(it
.first
, it
.second
.second
);