2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/sigtools.h"
27 PRIVATE_NAMESPACE_BEGIN
31 static std::vector
<RTLIL::Selection
> work_stack
;
33 static bool match_ids(RTLIL::IdString id
, const std::string
&pattern
)
38 const char *id_c
= id
.c_str();
39 const char *pat_c
= pattern
.c_str();
40 size_t id_size
= strlen(id_c
);
41 size_t pat_size
= pattern
.size();
43 if (*id_c
== '\\' && id_size
== 1 + pat_size
&& memcmp(id_c
+ 1, pat_c
, pat_size
) == 0)
45 if (patmatch(pat_c
, id_c
))
47 if (*id_c
== '\\' && patmatch(pat_c
, id_c
+ 1))
49 if (*id_c
== '$' && *pat_c
== '$') {
50 const char *q
= strrchr(id_c
, '$');
57 static bool match_attr_val(const RTLIL::Const
&value
, const std::string
&pattern
, char match_op
)
62 if ((value
.flags
& RTLIL::CONST_FLAG_STRING
) == 0)
64 RTLIL::SigSpec sig_value
;
66 if (!RTLIL::SigSpec::parse(sig_value
, nullptr, pattern
))
69 RTLIL::Const pattern_value
= sig_value
.as_const();
72 return value
== pattern_value
;
74 return value
!= pattern_value
;
76 return value
.as_int() < pattern_value
.as_int();
78 return value
.as_int() > pattern_value
.as_int();
80 return value
.as_int() <= pattern_value
.as_int();
82 return value
.as_int() >= pattern_value
.as_int();
86 std::string value_str
= value
.decode_string();
89 if (patmatch(pattern
.c_str(), value
.decode_string().c_str()))
93 return value_str
== pattern
;
95 return value_str
!= pattern
;
97 return value_str
< pattern
;
99 return value_str
> pattern
;
101 return value_str
<= pattern
;
103 return value_str
>= pattern
;
109 static bool match_attr(const dict
<RTLIL::IdString
, RTLIL::Const
> &attributes
, const std::string
&name_pat
, const std::string
&value_pat
, char match_op
)
111 if (name_pat
.find('*') != std::string::npos
|| name_pat
.find('?') != std::string::npos
|| name_pat
.find('[') != std::string::npos
) {
112 for (auto &it
: attributes
) {
113 if (patmatch(name_pat
.c_str(), it
.first
.c_str()) && match_attr_val(it
.second
, value_pat
, match_op
))
115 if (it
.first
.size() > 0 && it
.first
[0] == '\\' && patmatch(name_pat
.c_str(), it
.first
.substr(1).c_str()) && match_attr_val(it
.second
, value_pat
, match_op
))
119 if (name_pat
.size() > 0 && (name_pat
[0] == '\\' || name_pat
[0] == '$') && attributes
.count(name_pat
) && match_attr_val(attributes
.at(name_pat
), value_pat
, match_op
))
121 if (attributes
.count("\\" + name_pat
) && match_attr_val(attributes
.at("\\" + name_pat
), value_pat
, match_op
))
127 static bool match_attr(const dict
<RTLIL::IdString
, RTLIL::Const
> &attributes
, const std::string
&match_expr
)
129 size_t pos
= match_expr
.find_first_of("<!=>");
131 if (pos
!= std::string::npos
) {
132 if (match_expr
.compare(pos
, 2, "!=") == 0)
133 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), '!');
134 if (match_expr
.compare(pos
, 2, "<=") == 0)
135 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), '[');
136 if (match_expr
.compare(pos
, 2, ">=") == 0)
137 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), ']');
138 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+1), match_expr
[pos
]);
141 return match_attr(attributes
, match_expr
, std::string(), 0);
144 static void select_op_neg(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
146 if (lhs
.full_selection
) {
147 lhs
.full_selection
= false;
148 lhs
.selected_modules
.clear();
149 lhs
.selected_members
.clear();
153 if (lhs
.selected_modules
.size() == 0 && lhs
.selected_members
.size() == 0) {
154 lhs
.full_selection
= true;
158 RTLIL::Selection
new_sel(false);
160 for (auto mod
: design
->modules())
162 if (lhs
.selected_whole_module(mod
->name
))
164 if (!lhs
.selected_module(mod
->name
)) {
165 new_sel
.selected_modules
.insert(mod
->name
);
169 for (auto wire
: mod
->wires())
170 if (!lhs
.selected_member(mod
->name
, wire
->name
))
171 new_sel
.selected_members
[mod
->name
].insert(wire
->name
);
172 for (auto &it
: mod
->memories
)
173 if (!lhs
.selected_member(mod
->name
, it
.first
))
174 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
175 for (auto cell
: mod
->cells())
176 if (!lhs
.selected_member(mod
->name
, cell
->name
))
177 new_sel
.selected_members
[mod
->name
].insert(cell
->name
);
178 for (auto &it
: mod
->processes
)
179 if (!lhs
.selected_member(mod
->name
, it
.first
))
180 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
183 lhs
.selected_modules
.swap(new_sel
.selected_modules
);
184 lhs
.selected_members
.swap(new_sel
.selected_members
);
187 static int my_xorshift32_rng() {
188 static uint32_t x32
= 314159265;
192 return x32
& 0x0fffffff;
195 static void select_op_random(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, int count
)
197 vector
<pair
<IdString
, IdString
>> objects
;
199 for (auto mod
: design
->modules())
201 if (!lhs
.selected_module(mod
->name
))
204 for (auto cell
: mod
->cells()) {
205 if (lhs
.selected_member(mod
->name
, cell
->name
))
206 objects
.push_back(make_pair(mod
->name
, cell
->name
));
209 for (auto wire
: mod
->wires()) {
210 if (lhs
.selected_member(mod
->name
, wire
->name
))
211 objects
.push_back(make_pair(mod
->name
, wire
->name
));
215 lhs
= RTLIL::Selection(false);
217 while (!objects
.empty() && count
-- > 0)
219 int idx
= my_xorshift32_rng() % GetSize(objects
);
220 lhs
.selected_members
[objects
[idx
].first
].insert(objects
[idx
].second
);
221 objects
[idx
] = objects
.back();
225 lhs
.optimize(design
);
228 static void select_op_submod(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
230 for (auto mod
: design
->modules())
232 if (lhs
.selected_whole_module(mod
->name
))
234 for (auto cell
: mod
->cells())
236 if (design
->module(cell
->type
) == nullptr)
238 lhs
.selected_modules
.insert(cell
->type
);
244 static void select_op_cells_to_modules(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
246 RTLIL::Selection
new_sel(false);
247 for (auto mod
: design
->modules())
248 if (lhs
.selected_module(mod
->name
))
249 for (auto cell
: mod
->cells())
250 if (lhs
.selected_member(mod
->name
, cell
->name
) && (design
->module(cell
->type
) != nullptr))
251 new_sel
.selected_modules
.insert(cell
->type
);
255 static void select_op_module_to_cells(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
257 RTLIL::Selection
new_sel(false);
258 for (auto mod
: design
->modules())
259 for (auto cell
: mod
->cells())
260 if ((design
->module(cell
->type
) != nullptr) && lhs
.selected_whole_module(cell
->type
))
261 new_sel
.selected_members
[mod
->name
].insert(cell
->name
);
265 static void select_op_fullmod(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
267 lhs
.optimize(design
);
268 for (auto &it
: lhs
.selected_members
)
269 lhs
.selected_modules
.insert(it
.first
);
270 lhs
.selected_members
.clear();
273 static void select_op_alias(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
275 for (auto mod
: design
->modules())
277 if (lhs
.selected_whole_module(mod
->name
))
279 if (!lhs
.selected_module(mod
->name
))
283 SigPool selected_bits
;
285 for (auto wire
: mod
->wires())
286 if (lhs
.selected_member(mod
->name
, wire
->name
))
287 selected_bits
.add(sigmap(wire
));
289 for (auto wire
: mod
->wires())
290 if (!lhs
.selected_member(mod
->name
, wire
->name
) && selected_bits
.check_any(sigmap(wire
)))
291 lhs
.selected_members
[mod
->name
].insert(wire
->name
);
295 static void select_op_union(RTLIL::Design
*, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
297 if (rhs
.full_selection
) {
298 lhs
.full_selection
= true;
299 lhs
.selected_modules
.clear();
300 lhs
.selected_members
.clear();
304 if (lhs
.full_selection
)
307 for (auto &it
: rhs
.selected_members
)
308 for (auto &it2
: it
.second
)
309 lhs
.selected_members
[it
.first
].insert(it2
);
311 for (auto &it
: rhs
.selected_modules
) {
312 lhs
.selected_modules
.insert(it
);
313 lhs
.selected_members
.erase(it
);
317 static void select_op_diff(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
319 if (rhs
.full_selection
) {
320 lhs
.full_selection
= false;
321 lhs
.selected_modules
.clear();
322 lhs
.selected_members
.clear();
326 if (lhs
.full_selection
) {
327 if (!rhs
.full_selection
&& rhs
.selected_modules
.size() == 0 && rhs
.selected_members
.size() == 0)
329 lhs
.full_selection
= false;
330 for (auto mod
: design
->modules())
331 lhs
.selected_modules
.insert(mod
->name
);
334 for (auto &it
: rhs
.selected_modules
) {
335 lhs
.selected_modules
.erase(it
);
336 lhs
.selected_members
.erase(it
);
339 for (auto &it
: rhs
.selected_members
)
341 if (design
->module(it
.first
) == nullptr)
344 RTLIL::Module
*mod
= design
->module(it
.first
);
346 if (lhs
.selected_modules
.count(mod
->name
) > 0)
348 for (auto wire
: mod
->wires())
349 lhs
.selected_members
[mod
->name
].insert(wire
->name
);
350 for (auto &it
: mod
->memories
)
351 lhs
.selected_members
[mod
->name
].insert(it
.first
);
352 for (auto cell
: mod
->cells())
353 lhs
.selected_members
[mod
->name
].insert(cell
->name
);
354 for (auto &it
: mod
->processes
)
355 lhs
.selected_members
[mod
->name
].insert(it
.first
);
356 lhs
.selected_modules
.erase(mod
->name
);
359 if (lhs
.selected_members
.count(mod
->name
) == 0)
362 for (auto &it2
: it
.second
)
363 lhs
.selected_members
[mod
->name
].erase(it2
);
367 static void select_op_intersect(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
369 if (rhs
.full_selection
)
372 if (lhs
.full_selection
) {
373 lhs
.full_selection
= false;
374 for (auto mod
: design
->modules())
375 lhs
.selected_modules
.insert(mod
->name
);
378 std::vector
<RTLIL::IdString
> del_list
;
380 for (auto &it
: lhs
.selected_modules
)
381 if (rhs
.selected_modules
.count(it
) == 0) {
382 if (rhs
.selected_members
.count(it
) > 0)
383 for (auto &it2
: rhs
.selected_members
.at(it
))
384 lhs
.selected_members
[it
].insert(it2
);
385 del_list
.push_back(it
);
387 for (auto &it
: del_list
)
388 lhs
.selected_modules
.erase(it
);
391 for (auto &it
: lhs
.selected_members
) {
392 if (rhs
.selected_modules
.count(it
.first
) > 0)
394 if (rhs
.selected_members
.count(it
.first
) == 0) {
395 del_list
.push_back(it
.first
);
398 std::vector
<RTLIL::IdString
> del_list2
;
399 for (auto &it2
: it
.second
)
400 if (rhs
.selected_members
.at(it
.first
).count(it2
) == 0)
401 del_list2
.push_back(it2
);
402 for (auto &it2
: del_list2
)
403 it
.second
.erase(it2
);
404 if (it
.second
.size() == 0)
405 del_list
.push_back(it
.first
);
407 for (auto &it
: del_list
)
408 lhs
.selected_members
.erase(it
);
412 struct expand_rule_t
{
414 std::set
<RTLIL::IdString
> cell_types
, port_names
;
418 static int parse_comma_list(std::set
<RTLIL::IdString
> &tokens
, const std::string
&str
, size_t pos
, std::string stopchar
)
422 size_t endpos
= str
.find_first_of(stopchar
, pos
);
423 if (endpos
== std::string::npos
)
426 tokens
.insert(RTLIL::escape_id(str
.substr(pos
, endpos
-pos
)));
428 if (pos
== str
.size() || str
[pos
] != ',')
434 static int select_op_expand(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, std::vector
<expand_rule_t
> &rules
, std::set
<RTLIL::IdString
> &limits
, int max_objects
, char mode
, CellTypes
&ct
, bool eval_only
)
437 bool is_input
, is_output
;
438 for (auto mod
: design
->modules())
440 if (lhs
.selected_whole_module(mod
->name
) || !lhs
.selected_module(mod
->name
))
443 std::set
<RTLIL::Wire
*> selected_wires
;
444 auto selected_members
= lhs
.selected_members
[mod
->name
];
446 for (auto wire
: mod
->wires())
447 if (lhs
.selected_member(mod
->name
, wire
->name
) && limits
.count(wire
->name
) == 0)
448 selected_wires
.insert(wire
);
450 for (auto &conn
: mod
->connections())
452 std::vector
<RTLIL::SigBit
> conn_lhs
= conn
.first
.to_sigbit_vector();
453 std::vector
<RTLIL::SigBit
> conn_rhs
= conn
.second
.to_sigbit_vector();
455 for (size_t i
= 0; i
< conn_lhs
.size(); i
++) {
456 if (conn_lhs
[i
].wire
== nullptr || conn_rhs
[i
].wire
== nullptr)
458 if (mode
!= 'i' && selected_wires
.count(conn_rhs
[i
].wire
) && selected_members
.count(conn_lhs
[i
].wire
->name
) == 0)
459 lhs
.selected_members
[mod
->name
].insert(conn_lhs
[i
].wire
->name
), sel_objects
++, max_objects
--;
460 if (mode
!= 'o' && selected_wires
.count(conn_lhs
[i
].wire
) && selected_members
.count(conn_rhs
[i
].wire
->name
) == 0)
461 lhs
.selected_members
[mod
->name
].insert(conn_rhs
[i
].wire
->name
), sel_objects
++, max_objects
--;
465 for (auto cell
: mod
->cells())
466 for (auto &conn
: cell
->connections())
468 char last_mode
= '-';
469 if (eval_only
&& !yosys_celltypes
.cell_evaluable(cell
->type
))
471 for (auto &rule
: rules
) {
472 last_mode
= rule
.mode
;
473 if (rule
.cell_types
.size() > 0 && rule
.cell_types
.count(cell
->type
) == 0)
475 if (rule
.port_names
.size() > 0 && rule
.port_names
.count(conn
.first
) == 0)
477 if (rule
.mode
== '+')
482 if (last_mode
== '+')
485 is_input
= mode
== 'x' || ct
.cell_input(cell
->type
, conn
.first
);
486 is_output
= mode
== 'x' || ct
.cell_output(cell
->type
, conn
.first
);
487 for (auto &chunk
: conn
.second
.chunks())
488 if (chunk
.wire
!= nullptr) {
489 if (max_objects
!= 0 && selected_wires
.count(chunk
.wire
) > 0 && selected_members
.count(cell
->name
) == 0)
490 if (mode
== 'x' || (mode
== 'i' && is_output
) || (mode
== 'o' && is_input
))
491 lhs
.selected_members
[mod
->name
].insert(cell
->name
), sel_objects
++, max_objects
--;
492 if (max_objects
!= 0 && selected_members
.count(cell
->name
) > 0 && limits
.count(cell
->name
) == 0 && selected_members
.count(chunk
.wire
->name
) == 0)
493 if (mode
== 'x' || (mode
== 'i' && is_input
) || (mode
== 'o' && is_output
))
494 lhs
.selected_members
[mod
->name
].insert(chunk
.wire
->name
), sel_objects
++, max_objects
--;
503 static void select_op_expand(RTLIL::Design
*design
, const std::string
&arg
, char mode
, bool eval_only
)
505 int pos
= (mode
== 'x' ? 2 : 3) + (eval_only
? 1 : 0);
506 int levels
= 1, rem_objects
= -1;
507 std::vector
<expand_rule_t
> rules
;
508 std::set
<RTLIL::IdString
> limits
;
515 if (pos
< int(arg
.size()) && arg
[pos
] == '*') {
519 if (pos
< int(arg
.size()) && '0' <= arg
[pos
] && arg
[pos
] <= '9') {
520 size_t endpos
= arg
.find_first_not_of("0123456789", pos
);
521 if (endpos
== std::string::npos
)
523 levels
= atoi(arg
.substr(pos
, endpos
-pos
).c_str());
527 if (pos
< int(arg
.size()) && arg
[pos
] == '.') {
528 size_t endpos
= arg
.find_first_not_of("0123456789", ++pos
);
529 if (endpos
== std::string::npos
)
531 if (int(endpos
) > pos
)
532 rem_objects
= atoi(arg
.substr(pos
, endpos
-pos
).c_str());
536 while (pos
< int(arg
.size())) {
537 if (arg
[pos
] != ':' || pos
+1 == int(arg
.size()))
538 log_cmd_error("Syntax error in expand operator '%s'.\n", arg
.c_str());
540 if (arg
[pos
] == '+' || arg
[pos
] == '-') {
542 rule
.mode
= arg
[pos
++];
543 pos
= parse_comma_list(rule
.cell_types
, arg
, pos
, "[:");
544 if (pos
< int(arg
.size()) && arg
[pos
] == '[') {
545 pos
= parse_comma_list(rule
.port_names
, arg
, pos
+1, "]:");
546 if (pos
< int(arg
.size()) && arg
[pos
] == ']')
549 rules
.push_back(rule
);
551 size_t endpos
= arg
.find(':', pos
);
552 if (endpos
== std::string::npos
)
554 if (int(endpos
) > pos
) {
555 std::string str
= arg
.substr(pos
, endpos
-pos
);
557 str
= RTLIL::escape_id(str
.substr(1));
558 if (design
->selection_vars
.count(str
) > 0) {
559 for (auto i1
: design
->selection_vars
.at(str
).selected_members
)
560 for (auto i2
: i1
.second
)
563 log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str
).c_str());
565 limits
.insert(RTLIL::escape_id(str
));
572 log("expand by %d levels (max. %d objects):\n", levels
, rem_objects
);
573 for (auto &rule
: rules
) {
574 log(" rule (%c):\n", rule
.mode
);
575 if (rule
.cell_types
.size() > 0) {
577 for (auto &it
: rule
.cell_types
)
578 log(" %s", it
.c_str());
581 if (rule
.port_names
.size() > 0) {
583 for (auto &it
: rule
.port_names
)
584 log(" %s", it
.c_str());
588 if (limits
.size() > 0) {
590 for (auto &it
: limits
)
591 log(" %s", it
.c_str());
596 while (levels
-- > 0 && rem_objects
!= 0) {
597 int num_objects
= select_op_expand(design
, work_stack
.back(), rules
, limits
, rem_objects
, mode
, ct
, eval_only
);
598 if (num_objects
== 0)
600 rem_objects
-= num_objects
;
603 if (rem_objects
== 0)
604 log_warning("reached configured limit at `%s'.\n", arg
.c_str());
607 static void select_filter_active_mod(RTLIL::Design
*design
, RTLIL::Selection
&sel
)
609 if (design
->selected_active_module
.empty())
612 if (sel
.full_selection
) {
613 sel
.full_selection
= false;
614 sel
.selected_modules
.clear();
615 sel
.selected_members
.clear();
616 sel
.selected_modules
.insert(design
->selected_active_module
);
620 std::vector
<RTLIL::IdString
> del_list
;
621 for (auto mod_name
: sel
.selected_modules
)
622 if (mod_name
!= design
->selected_active_module
)
623 del_list
.push_back(mod_name
);
624 for (auto &it
: sel
.selected_members
)
625 if (it
.first
!= design
->selected_active_module
)
626 del_list
.push_back(it
.first
);
627 for (auto mod_name
: del_list
) {
628 sel
.selected_modules
.erase(mod_name
);
629 sel
.selected_members
.erase(mod_name
);
633 static void select_stmt(RTLIL::Design
*design
, std::string arg
, bool disable_empty_warning
= false)
635 std::string arg_mod
, arg_memb
;
636 std::unordered_map
<std::string
, bool> arg_mod_found
;
637 std::unordered_map
<std::string
, bool> arg_memb_found
;
639 auto isprefixed
= [](const string
&s
) {
640 return GetSize(s
) >= 2 && ((s
[0] >= 'a' && s
[0] <= 'z') || (s
[0] >= 'A' && s
[0] <= 'Z')) && s
[1] == ':';
648 if (design
->selection_stack
.size() > 0)
649 work_stack
.push_back(design
->selection_stack
.back());
652 while (work_stack
.size() > 1) {
653 select_op_union(design
, work_stack
.front(), work_stack
.back());
654 work_stack
.pop_back();
658 if (work_stack
.size() < 1)
659 log_cmd_error("Must have at least one element on the stack for operator %%n.\n");
660 select_op_neg(design
, work_stack
[work_stack
.size()-1]);
663 if (work_stack
.size() < 2)
664 log_cmd_error("Must have at least two elements on the stack for operator %%u.\n");
665 select_op_union(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
666 work_stack
.pop_back();
669 if (work_stack
.size() < 2)
670 log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
671 select_op_diff(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
672 work_stack
.pop_back();
675 if (work_stack
.size() < 2)
676 log_cmd_error("Must have at least two elements on the stack for operator %%D.\n");
677 select_op_diff(design
, work_stack
[work_stack
.size()-1], work_stack
[work_stack
.size()-2]);
678 work_stack
[work_stack
.size()-2] = work_stack
[work_stack
.size()-1];
679 work_stack
.pop_back();
682 if (work_stack
.size() < 2)
683 log_cmd_error("Must have at least two elements on the stack for operator %%i.\n");
684 select_op_intersect(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
685 work_stack
.pop_back();
687 if (arg
.size() >= 2 && arg
[0] == '%' && arg
[1] == 'R') {
688 if (work_stack
.size() < 1)
689 log_cmd_error("Must have at least one element on the stack for operator %%R.\n");
690 int count
= arg
.size() > 2 ? atoi(arg
.c_str() + 2) : 1;
691 select_op_random(design
, work_stack
[work_stack
.size()-1], count
);
694 if (work_stack
.size() < 1)
695 log_cmd_error("Must have at least one element on the stack for operator %%s.\n");
696 select_op_submod(design
, work_stack
[work_stack
.size()-1]);
699 if (work_stack
.size() < 1)
700 log_cmd_error("Must have at least one element on the stack for operator %%M.\n");
701 select_op_cells_to_modules(design
, work_stack
[work_stack
.size()-1]);
704 if (work_stack
.size() < 1)
705 log_cmd_error("Must have at least one element on the stack for operator %%C.\n");
706 select_op_module_to_cells(design
, work_stack
[work_stack
.size()-1]);
709 if (work_stack
.size() < 1)
710 log_cmd_error("Must have at least one element on the stack for operator %%c.\n");
711 work_stack
.push_back(work_stack
.back());
714 if (work_stack
.size() < 1)
715 log_cmd_error("Must have at least one element on the stack for operator %%m.\n");
716 select_op_fullmod(design
, work_stack
[work_stack
.size()-1]);
719 if (work_stack
.size() < 1)
720 log_cmd_error("Must have at least one element on the stack for operator %%a.\n");
721 select_op_alias(design
, work_stack
[work_stack
.size()-1]);
723 if (arg
== "%x" || (arg
.size() > 2 && arg
.compare(0, 2, "%x") == 0 && (arg
[2] == ':' || arg
[2] == '*' || arg
[2] == '.' || ('0' <= arg
[2] && arg
[2] <= '9')))) {
724 if (work_stack
.size() < 1)
725 log_cmd_error("Must have at least one element on the stack for operator %%x.\n");
726 select_op_expand(design
, arg
, 'x', false);
728 if (arg
== "%ci" || (arg
.size() > 3 && arg
.compare(0, 3, "%ci") == 0 && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
729 if (work_stack
.size() < 1)
730 log_cmd_error("Must have at least one element on the stack for operator %%ci.\n");
731 select_op_expand(design
, arg
, 'i', false);
733 if (arg
== "%co" || (arg
.size() > 3 && arg
.compare(0, 3, "%co") == 0 && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
734 if (work_stack
.size() < 1)
735 log_cmd_error("Must have at least one element on the stack for operator %%co.\n");
736 select_op_expand(design
, arg
, 'o', false);
738 if (arg
== "%xe" || (arg
.size() > 3 && arg
.compare(0, 3, "%xe") == 0 && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
739 if (work_stack
.size() < 1)
740 log_cmd_error("Must have at least one element on the stack for operator %%xe.\n");
741 select_op_expand(design
, arg
, 'x', true);
743 if (arg
== "%cie" || (arg
.size() > 4 && arg
.compare(0, 4, "%cie") == 0 && (arg
[4] == ':' || arg
[4] == '*' || arg
[4] == '.' || ('0' <= arg
[4] && arg
[4] <= '9')))) {
744 if (work_stack
.size() < 1)
745 log_cmd_error("Must have at least one element on the stack for operator %%cie.\n");
746 select_op_expand(design
, arg
, 'i', true);
748 if (arg
== "%coe" || (arg
.size() > 4 && arg
.compare(0, 4, "%coe") == 0 && (arg
[4] == ':' || arg
[4] == '*' || arg
[4] == '.' || ('0' <= arg
[4] && arg
[4] <= '9')))) {
749 if (work_stack
.size() < 1)
750 log_cmd_error("Must have at least one element on the stack for operator %%coe.\n");
751 select_op_expand(design
, arg
, 'o', true);
753 log_cmd_error("Unknown selection operator '%s'.\n", arg
.c_str());
754 if (work_stack
.size() >= 1)
755 select_filter_active_mod(design
, work_stack
.back());
760 std::string set_name
= RTLIL::escape_id(arg
.substr(1));
761 if (design
->selection_vars
.count(set_name
) > 0)
762 work_stack
.push_back(design
->selection_vars
[set_name
]);
764 log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name
).c_str());
765 select_filter_active_mod(design
, work_stack
.back());
769 bool select_blackboxes
= false;
770 if (arg
.substr(0, 1) == "=") {
772 select_blackboxes
= true;
775 if (!design
->selected_active_module
.empty()) {
776 arg_mod
= design
->selected_active_module
;
778 if (!isprefixed(arg_memb
))
779 arg_memb_found
[arg_memb
] = false;
781 if (isprefixed(arg
) && arg
[0] >= 'a' && arg
[0] <= 'z') {
782 arg_mod
= "*", arg_memb
= arg
;
784 size_t pos
= arg
.find('/');
785 if (pos
== std::string::npos
) {
787 if (!isprefixed(arg_mod
))
788 arg_mod_found
[arg_mod
] = false;
790 arg_mod
= arg
.substr(0, pos
);
791 if (!isprefixed(arg_mod
))
792 arg_mod_found
[arg_mod
] = false;
793 arg_memb
= arg
.substr(pos
+1);
794 if (!isprefixed(arg_memb
))
795 arg_memb_found
[arg_memb
] = false;
799 work_stack
.push_back(RTLIL::Selection());
800 RTLIL::Selection
&sel
= work_stack
.back();
802 if (arg
== "*" && arg_mod
== "*" && select_blackboxes
) {
803 select_filter_active_mod(design
, work_stack
.back());
807 sel
.full_selection
= false;
808 for (auto mod
: design
->modules())
810 if (!select_blackboxes
&& mod
->get_blackbox_attribute())
813 if (arg_mod
.compare(0, 2, "A:") == 0) {
814 if (!match_attr(mod
->attributes
, arg_mod
.substr(2)))
817 if (arg_mod
.compare(0, 2, "N:") == 0) {
818 if (!match_ids(mod
->name
, arg_mod
.substr(2)))
821 if (!match_ids(mod
->name
, arg_mod
))
824 arg_mod_found
[arg_mod
] = true;
826 if (arg_memb
== "") {
827 sel
.selected_modules
.insert(mod
->name
);
831 if (arg_memb
.compare(0, 2, "w:") == 0) {
832 for (auto wire
: mod
->wires())
833 if (match_ids(wire
->name
, arg_memb
.substr(2)))
834 sel
.selected_members
[mod
->name
].insert(wire
->name
);
836 if (arg_memb
.compare(0, 2, "i:") == 0) {
837 for (auto wire
: mod
->wires())
838 if (wire
->port_input
&& match_ids(wire
->name
, arg_memb
.substr(2)))
839 sel
.selected_members
[mod
->name
].insert(wire
->name
);
841 if (arg_memb
.compare(0, 2, "o:") == 0) {
842 for (auto wire
: mod
->wires())
843 if (wire
->port_output
&& match_ids(wire
->name
, arg_memb
.substr(2)))
844 sel
.selected_members
[mod
->name
].insert(wire
->name
);
846 if (arg_memb
.compare(0, 2, "x:") == 0) {
847 for (auto wire
: mod
->wires())
848 if ((wire
->port_input
|| wire
->port_output
) && match_ids(wire
->name
, arg_memb
.substr(2)))
849 sel
.selected_members
[mod
->name
].insert(wire
->name
);
851 if (arg_memb
.compare(0, 2, "s:") == 0) {
852 size_t delim
= arg_memb
.substr(2).find(':');
853 if (delim
== std::string::npos
) {
854 int width
= atoi(arg_memb
.substr(2).c_str());
855 for (auto wire
: mod
->wires())
856 if (wire
->width
== width
)
857 sel
.selected_members
[mod
->name
].insert(wire
->name
);
859 std::string min_str
= arg_memb
.substr(2, delim
);
860 std::string max_str
= arg_memb
.substr(2+delim
+1);
861 int min_width
= min_str
.empty() ? 0 : atoi(min_str
.c_str());
862 int max_width
= max_str
.empty() ? -1 : atoi(max_str
.c_str());
863 for (auto wire
: mod
->wires())
864 if (min_width
<= wire
->width
&& (wire
->width
<= max_width
|| max_width
== -1))
865 sel
.selected_members
[mod
->name
].insert(wire
->name
);
868 if (arg_memb
.compare(0, 2, "m:") == 0) {
869 for (auto &it
: mod
->memories
)
870 if (match_ids(it
.first
, arg_memb
.substr(2)))
871 sel
.selected_members
[mod
->name
].insert(it
.first
);
873 if (arg_memb
.compare(0, 2, "c:") == 0) {
874 for (auto cell
: mod
->cells())
875 if (match_ids(cell
->name
, arg_memb
.substr(2)))
876 sel
.selected_members
[mod
->name
].insert(cell
->name
);
878 if (arg_memb
.compare(0, 2, "t:") == 0) {
879 for (auto cell
: mod
->cells())
880 if (match_ids(cell
->type
, arg_memb
.substr(2)))
881 sel
.selected_members
[mod
->name
].insert(cell
->name
);
883 if (arg_memb
.compare(0, 2, "p:") == 0) {
884 for (auto &it
: mod
->processes
)
885 if (match_ids(it
.first
, arg_memb
.substr(2)))
886 sel
.selected_members
[mod
->name
].insert(it
.first
);
888 if (arg_memb
.compare(0, 2, "a:") == 0) {
889 for (auto wire
: mod
->wires())
890 if (match_attr(wire
->attributes
, arg_memb
.substr(2)))
891 sel
.selected_members
[mod
->name
].insert(wire
->name
);
892 for (auto &it
: mod
->memories
)
893 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
894 sel
.selected_members
[mod
->name
].insert(it
.first
);
895 for (auto cell
: mod
->cells())
896 if (match_attr(cell
->attributes
, arg_memb
.substr(2)))
897 sel
.selected_members
[mod
->name
].insert(cell
->name
);
898 for (auto &it
: mod
->processes
)
899 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
900 sel
.selected_members
[mod
->name
].insert(it
.first
);
902 if (arg_memb
.compare(0, 2, "r:") == 0) {
903 for (auto cell
: mod
->cells())
904 if (match_attr(cell
->parameters
, arg_memb
.substr(2)))
905 sel
.selected_members
[mod
->name
].insert(cell
->name
);
907 std::string orig_arg_memb
= arg_memb
;
908 if (arg_memb
.compare(0, 2, "n:") == 0)
909 arg_memb
= arg_memb
.substr(2);
910 for (auto wire
: mod
->wires())
911 if (match_ids(wire
->name
, arg_memb
)) {
912 sel
.selected_members
[mod
->name
].insert(wire
->name
);
913 arg_memb_found
[orig_arg_memb
] = true;
915 for (auto &it
: mod
->memories
)
916 if (match_ids(it
.first
, arg_memb
)) {
917 sel
.selected_members
[mod
->name
].insert(it
.first
);
918 arg_memb_found
[orig_arg_memb
] = true;
920 for (auto cell
: mod
->cells())
921 if (match_ids(cell
->name
, arg_memb
)) {
922 sel
.selected_members
[mod
->name
].insert(cell
->name
);
923 arg_memb_found
[orig_arg_memb
] = true;
925 for (auto &it
: mod
->processes
)
926 if (match_ids(it
.first
, arg_memb
)) {
927 sel
.selected_members
[mod
->name
].insert(it
.first
);
928 arg_memb_found
[orig_arg_memb
] = true;
933 select_filter_active_mod(design
, work_stack
.back());
935 for (auto &it
: arg_mod_found
) {
936 if (it
.second
== false && !disable_empty_warning
) {
937 log_warning("Selection \"%s\" did not match any module.\n", it
.first
.c_str());
940 for (auto &it
: arg_memb_found
) {
941 if (it
.second
== false && !disable_empty_warning
) {
942 log_warning("Selection \"%s\" did not match any object.\n", it
.first
.c_str());
947 static std::string
describe_selection_for_assert(RTLIL::Design
*design
, RTLIL::Selection
*sel
)
949 std::string desc
= "Selection contains:\n";
950 for (auto mod
: design
->modules())
952 if (sel
->selected_module(mod
->name
)) {
953 for (auto wire
: mod
->wires())
954 if (sel
->selected_member(mod
->name
, wire
->name
))
955 desc
+= stringf("%s/%s\n", id2cstr(mod
->name
), id2cstr(wire
->name
));
956 for (auto &it
: mod
->memories
)
957 if (sel
->selected_member(mod
->name
, it
.first
))
958 desc
+= stringf("%s/%s\n", id2cstr(mod
->name
), id2cstr(it
.first
));
959 for (auto cell
: mod
->cells())
960 if (sel
->selected_member(mod
->name
, cell
->name
))
961 desc
+= stringf("%s/%s\n", id2cstr(mod
->name
), id2cstr(cell
->name
));
962 for (auto &it
: mod
->processes
)
963 if (sel
->selected_member(mod
->name
, it
.first
))
964 desc
+= stringf("%s/%s\n", id2cstr(mod
->name
), id2cstr(it
.first
));
970 PRIVATE_NAMESPACE_END
971 YOSYS_NAMESPACE_BEGIN
973 // used in kernel/register.cc and maybe other locations, extern decl. in register.h
974 void handle_extra_select_args(Pass
*pass
, const vector
<string
> &args
, size_t argidx
, size_t args_size
, RTLIL::Design
*design
)
977 for (; argidx
< args_size
; argidx
++) {
978 if (args
[argidx
].compare(0, 1, "-") == 0) {
980 pass
->cmd_error(args
, argidx
, "Unexpected option in selection arguments.");
982 log_cmd_error("Unexpected option in selection arguments.");
984 select_stmt(design
, args
[argidx
]);
986 while (work_stack
.size() > 1) {
987 select_op_union(design
, work_stack
.front(), work_stack
.back());
988 work_stack
.pop_back();
990 if (work_stack
.empty())
991 design
->selection_stack
.push_back(RTLIL::Selection(false));
993 design
->selection_stack
.push_back(work_stack
.back());
996 // extern decl. in register.h
997 RTLIL::Selection
eval_select_args(const vector
<string
> &args
, RTLIL::Design
*design
)
1000 for (auto &arg
: args
)
1001 select_stmt(design
, arg
);
1002 while (work_stack
.size() > 1) {
1003 select_op_union(design
, work_stack
.front(), work_stack
.back());
1004 work_stack
.pop_back();
1006 if (work_stack
.empty())
1007 return RTLIL::Selection(false);
1008 return work_stack
.back();
1011 // extern decl. in register.h
1012 void eval_select_op(vector
<RTLIL::Selection
> &work
, const string
&op
, RTLIL::Design
*design
)
1014 work_stack
.swap(work
);
1015 select_stmt(design
, op
);
1016 work_stack
.swap(work
);
1020 PRIVATE_NAMESPACE_BEGIN
1022 struct SelectPass
: public Pass
{
1023 SelectPass() : Pass("select", "modify and view the list of selected objects") { }
1024 void help() override
1026 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1028 log(" select [ -add | -del | -set <name> ] {-read <filename> | <selection>}\n");
1029 log(" select [ -unset <name> ]\n");
1030 log(" select [ <assert_option> ] {-read <filename> | <selection>}\n");
1031 log(" select [ -list | -write <filename> | -count | -clear ]\n");
1032 log(" select -module <modname>\n");
1034 log("Most commands use the list of currently selected objects to determine which part\n");
1035 log("of the design to operate on. This command can be used to modify and view this\n");
1036 log("list of selected objects.\n");
1038 log("Note that many commands support an optional [selection] argument that can be\n");
1039 log("used to override the global selection for the command. The syntax of this\n");
1040 log("optional argument is identical to the syntax of the <selection> argument\n");
1041 log("described here.\n");
1043 log(" -add, -del\n");
1044 log(" add or remove the given objects to the current selection.\n");
1045 log(" without this options the current selection is replaced.\n");
1047 log(" -set <name>\n");
1048 log(" do not modify the current selection. instead save the new selection\n");
1049 log(" under the given name (see @<name> below). to save the current selection,\n");
1050 log(" use \"select -set <name> %%\"\n");
1052 log(" -unset <name>\n");
1053 log(" do not modify the current selection. instead remove a previously saved\n");
1054 log(" selection under the given name (see @<name> below).");
1056 log(" -assert-none\n");
1057 log(" do not modify the current selection. instead assert that the given\n");
1058 log(" selection is empty. i.e. produce an error if any object matching the\n");
1059 log(" selection is found.\n");
1061 log(" -assert-any\n");
1062 log(" do not modify the current selection. instead assert that the given\n");
1063 log(" selection is non-empty. i.e. produce an error if no object matching\n");
1064 log(" the selection is found.\n");
1066 log(" -assert-count N\n");
1067 log(" do not modify the current selection. instead assert that the given\n");
1068 log(" selection contains exactly N objects.\n");
1070 log(" -assert-max N\n");
1071 log(" do not modify the current selection. instead assert that the given\n");
1072 log(" selection contains less than or exactly N objects.\n");
1074 log(" -assert-min N\n");
1075 log(" do not modify the current selection. instead assert that the given\n");
1076 log(" selection contains at least N objects.\n");
1079 log(" list all objects in the current selection\n");
1081 log(" -write <filename>\n");
1082 log(" like -list but write the output to the specified file\n");
1084 log(" -read <filename>\n");
1085 log(" read the specified file (written by -write)\n");
1088 log(" count all objects in the current selection\n");
1091 log(" clear the current selection. this effectively selects the whole\n");
1092 log(" design. it also resets the selected module (see -module). use the\n");
1093 log(" command 'select *' to select everything but stay in the current module.\n");
1096 log(" create an empty selection. the current module is unchanged.\n");
1098 log(" -module <modname>\n");
1099 log(" limit the current scope to the specified module.\n");
1100 log(" the difference between this and simply selecting the module\n");
1101 log(" is that all object names are interpreted relative to this\n");
1102 log(" module after this command until the selection is cleared again.\n");
1104 log("When this command is called without an argument, the current selection\n");
1105 log("is displayed in a compact form (i.e. only the module name when a whole module\n");
1106 log("is selected).\n");
1108 log("The <selection> argument itself is a series of commands for a simple stack\n");
1109 log("machine. Each element on the stack represents a set of selected objects.\n");
1110 log("After this commands have been executed, the union of all remaining sets\n");
1111 log("on the stack is computed and used as selection for the command.\n");
1113 log("Pushing (selecting) object when not in -module mode:\n");
1115 log(" <mod_pattern>\n");
1116 log(" select the specified module(s)\n");
1118 log(" <mod_pattern>/<obj_pattern>\n");
1119 log(" select the specified object(s) from the module(s)\n");
1121 log("Pushing (selecting) object when in -module mode:\n");
1123 log(" <obj_pattern>\n");
1124 log(" select the specified object(s) from the current module\n");
1126 log("By default, patterns will not match black/white-box modules or their");
1127 log("contents. To include such objects, prefix the pattern with '='.\n");
1129 log("A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])\n");
1130 log("matching module names, or one of the following:\n");
1132 log(" A:<pattern>, A:<pattern>=<pattern>\n");
1133 log(" all modules with an attribute matching the given pattern\n");
1134 log(" in addition to = also <, <=, >=, and > are supported\n");
1136 log(" N:<pattern>\n");
1137 log(" all modules with a name matching the given pattern\n");
1138 log(" (i.e. 'N:' is optional as it is the default matching rule)\n");
1140 log("An <obj_pattern> can be an object name, wildcard expression, or one of\n");
1141 log("the following:\n");
1143 log(" w:<pattern>\n");
1144 log(" all wires with a name matching the given wildcard pattern\n");
1146 log(" i:<pattern>, o:<pattern>, x:<pattern>\n");
1147 log(" all inputs (i:), outputs (o:) or any ports (x:) with matching names\n");
1149 log(" s:<size>, s:<min>:<max>\n");
1150 log(" all wires with a matching width\n");
1152 log(" m:<pattern>\n");
1153 log(" all memories with a name matching the given pattern\n");
1155 log(" c:<pattern>\n");
1156 log(" all cells with a name matching the given pattern\n");
1158 log(" t:<pattern>\n");
1159 log(" all cells with a type matching the given pattern\n");
1161 log(" p:<pattern>\n");
1162 log(" all processes with a name matching the given pattern\n");
1164 log(" a:<pattern>\n");
1165 log(" all objects with an attribute name matching the given pattern\n");
1167 log(" a:<pattern>=<pattern>\n");
1168 log(" all objects with a matching attribute name-value-pair.\n");
1169 log(" in addition to = also <, <=, >=, and > are supported\n");
1171 log(" r:<pattern>, r:<pattern>=<pattern>\n");
1172 log(" cells with matching parameters. also with <, <=, >= and >.\n");
1174 log(" n:<pattern>\n");
1175 log(" all objects with a name matching the given pattern\n");
1176 log(" (i.e. 'n:' is optional as it is the default matching rule)\n");
1179 log(" push the selection saved prior with 'select -set <name> ...'\n");
1181 log("The following actions can be performed on the top sets on the stack:\n");
1184 log(" push a copy of the current selection to the stack\n");
1187 log(" replace the stack with a union of all elements on it\n");
1190 log(" replace top set with its invert\n");
1193 log(" replace the two top sets on the stack with their union\n");
1196 log(" replace the two top sets on the stack with their intersection\n");
1199 log(" pop the top set from the stack and subtract it from the new top\n");
1202 log(" like %%d but swap the roles of two top sets on the stack\n");
1205 log(" create a copy of the top set from the stack and push it\n");
1207 log(" %%x[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
1208 log(" expand top set <num1> num times according to the specified rules.\n");
1209 log(" (i.e. select all cells connected to selected wires and select all\n");
1210 log(" wires connected to selected cells) The rules specify which cell\n");
1211 log(" ports to use for this. the syntax for a rule is a '-' for exclusion\n");
1212 log(" and a '+' for inclusion, followed by an optional comma separated\n");
1213 log(" list of cell types followed by an optional comma separated list of\n");
1214 log(" cell ports in square brackets. a rule can also be just a cell or wire\n");
1215 log(" name that limits the expansion (is included but does not go beyond).\n");
1216 log(" select at most <num2> objects. a warning message is printed when this\n");
1217 log(" limit is reached. When '*' is used instead of <num1> then the process\n");
1218 log(" is repeated until no further object are selected.\n");
1220 log(" %%ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
1221 log(" %%co[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
1222 log(" similar to %%x, but only select input (%%ci) or output cones (%%co)\n");
1224 log(" %%xe[...] %%cie[...] %%coe\n");
1225 log(" like %%x, %%ci, and %%co but only consider combinatorial cells\n");
1228 log(" expand top set by selecting all wires that are (at least in part)\n");
1229 log(" aliases for selected wires.\n");
1232 log(" expand top set by adding all modules that implement cells in selected\n");
1236 log(" expand top set by selecting all modules that contain selected objects\n");
1239 log(" select modules that implement selected cells\n");
1242 log(" select cells that implement selected modules\n");
1244 log(" %%R[<num>]\n");
1245 log(" select <num> random objects from top selection (default 1)\n");
1247 log("Example: the following command selects all wires that are connected to a\n");
1248 log("'GATE' input of a 'SWITCH' cell:\n");
1250 log(" select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n");
1253 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) override
1255 bool add_mode
= false;
1256 bool del_mode
= false;
1257 bool clear_mode
= false;
1258 bool none_mode
= false;
1259 bool list_mode
= false;
1260 bool count_mode
= false;
1261 bool got_module
= false;
1262 bool assert_none
= false;
1263 bool assert_any
= false;
1264 int assert_count
= -1;
1265 int assert_max
= -1;
1266 int assert_min
= -1;
1267 std::string write_file
, read_file
;
1268 std::string set_name
, unset_name
, sel_str
;
1273 for (argidx
= 1; argidx
< args
.size(); argidx
++)
1275 std::string arg
= args
[argidx
];
1276 if (arg
== "-add") {
1280 if (arg
== "-del") {
1284 if (arg
== "-assert-none") {
1288 if (arg
== "-assert-any") {
1292 if (arg
== "-assert-count" && argidx
+1 < args
.size()) {
1293 assert_count
= atoi(args
[++argidx
].c_str());
1296 if (arg
== "-assert-max" && argidx
+1 < args
.size()) {
1297 assert_max
= atoi(args
[++argidx
].c_str());
1300 if (arg
== "-assert-min" && argidx
+1 < args
.size()) {
1301 assert_min
= atoi(args
[++argidx
].c_str());
1304 if (arg
== "-clear") {
1308 if (arg
== "-none") {
1312 if (arg
== "-list") {
1316 if (arg
== "-write" && argidx
+1 < args
.size()) {
1317 write_file
= args
[++argidx
];
1320 if (arg
== "-read" && argidx
+1 < args
.size()) {
1321 read_file
= args
[++argidx
];
1324 if (arg
== "-count") {
1328 if (arg
== "-module" && argidx
+1 < args
.size()) {
1329 RTLIL::IdString mod_name
= RTLIL::escape_id(args
[++argidx
]);
1330 if (design
->module(mod_name
) == nullptr)
1331 log_cmd_error("No such module: %s\n", id2cstr(mod_name
));
1332 design
->selected_active_module
= mod_name
.str();
1336 if (arg
== "-set" && argidx
+1 < args
.size()) {
1337 set_name
= RTLIL::escape_id(args
[++argidx
]);
1340 if (arg
== "-unset" && argidx
+1 < args
.size()) {
1341 unset_name
= RTLIL::escape_id(args
[++argidx
]);
1344 if (arg
.size() > 0 && arg
[0] == '-')
1345 log_cmd_error("Unknown option %s.\n", arg
.c_str());
1346 bool disable_empty_warning
= count_mode
|| assert_none
|| assert_any
|| (assert_count
!= -1) || (assert_max
!= -1) || (assert_min
!= -1);
1347 select_stmt(design
, arg
, disable_empty_warning
);
1348 sel_str
+= " " + arg
;
1351 if (!read_file
.empty())
1353 if (!sel_str
.empty())
1354 log_cmd_error("Option -read can not be combined with a selection expression.\n");
1356 std::ifstream
f(read_file
);
1357 yosys_input_files
.insert(read_file
);
1359 log_error("Can't open '%s' for reading: %s\n", read_file
.c_str(), strerror(errno
));
1361 RTLIL::Selection
sel(false);
1364 while (std::getline(f
, line
)) {
1365 size_t slash_pos
= line
.find('/');
1366 if (slash_pos
== string::npos
) {
1367 log_warning("Ignoring line without slash in 'select -read': %s\n", line
.c_str());
1370 IdString mod_name
= RTLIL::escape_id(line
.substr(0, slash_pos
));
1371 IdString obj_name
= RTLIL::escape_id(line
.substr(slash_pos
+1));
1372 sel
.selected_members
[mod_name
].insert(obj_name
);
1375 select_filter_active_mod(design
, sel
);
1376 sel
.optimize(design
);
1377 work_stack
.push_back(sel
);
1380 if (clear_mode
&& args
.size() != 2)
1381 log_cmd_error("Option -clear can not be combined with any other options.\n");
1383 if (none_mode
&& args
.size() != 2)
1384 log_cmd_error("Option -none can not be combined with any other options.\n");
1386 if (add_mode
+ del_mode
+ assert_none
+ assert_any
+ (assert_count
>= 0) + (assert_max
>= 0) + (assert_min
>= 0) > 1)
1387 log_cmd_error("Options -add, -del, -assert-none, -assert-any, assert-count, -assert-max or -assert-min can not be combined.\n");
1389 if ((list_mode
|| !write_file
.empty() || count_mode
) && (add_mode
|| del_mode
|| assert_none
|| assert_any
|| assert_count
>= 0 || assert_max
>= 0 || assert_min
>= 0))
1390 log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none, -assert-any, assert-count, -assert-max, or -assert-min.\n");
1392 if (!set_name
.empty() && (list_mode
|| !write_file
.empty() || count_mode
|| add_mode
|| !unset_name
.empty() || del_mode
|| assert_none
|| assert_any
|| assert_count
>= 0 || assert_max
>= 0 || assert_min
>= 0))
1393 log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -unset, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
1395 if (!unset_name
.empty() && (list_mode
|| !write_file
.empty() || count_mode
|| add_mode
|| !set_name
.empty() || del_mode
|| assert_none
|| assert_any
|| assert_count
>= 0 || assert_max
>= 0 || assert_min
>= 0))
1396 log_cmd_error("Option -unset can not be combined with -list, -write, -count, -add, -del, -set, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
1398 if (work_stack
.size() == 0 && got_module
) {
1399 RTLIL::Selection sel
;
1400 select_filter_active_mod(design
, sel
);
1401 work_stack
.push_back(sel
);
1404 while (work_stack
.size() > 1) {
1405 select_op_union(design
, work_stack
.front(), work_stack
.back());
1406 work_stack
.pop_back();
1409 log_assert(design
->selection_stack
.size() > 0);
1412 design
->selection_stack
.back() = RTLIL::Selection(true);
1413 design
->selected_active_module
= std::string();
1418 design
->selection_stack
.back() = RTLIL::Selection(false);
1422 if (list_mode
|| count_mode
|| !write_file
.empty())
1424 #define LOG_OBJECT(...) { if (list_mode) log(__VA_ARGS__); if (f != nullptr) fprintf(f, __VA_ARGS__); total_count++; }
1425 int total_count
= 0;
1427 if (!write_file
.empty()) {
1428 f
= fopen(write_file
.c_str(), "w");
1429 yosys_output_files
.insert(write_file
);
1431 log_error("Can't open '%s' for writing: %s\n", write_file
.c_str(), strerror(errno
));
1433 RTLIL::Selection
*sel
= &design
->selection_stack
.back();
1434 if (work_stack
.size() > 0)
1435 sel
= &work_stack
.back();
1436 sel
->optimize(design
);
1437 for (auto mod
: design
->modules())
1439 if (sel
->selected_whole_module(mod
->name
) && list_mode
)
1440 log("%s\n", id2cstr(mod
->name
));
1441 if (sel
->selected_module(mod
->name
)) {
1442 for (auto wire
: mod
->wires())
1443 if (sel
->selected_member(mod
->name
, wire
->name
))
1444 LOG_OBJECT("%s/%s\n", id2cstr(mod
->name
), id2cstr(wire
->name
))
1445 for (auto &it
: mod
->memories
)
1446 if (sel
->selected_member(mod
->name
, it
.first
))
1447 LOG_OBJECT("%s/%s\n", id2cstr(mod
->name
), id2cstr(it
.first
))
1448 for (auto cell
: mod
->cells())
1449 if (sel
->selected_member(mod
->name
, cell
->name
))
1450 LOG_OBJECT("%s/%s\n", id2cstr(mod
->name
), id2cstr(cell
->name
))
1451 for (auto &it
: mod
->processes
)
1452 if (sel
->selected_member(mod
->name
, it
.first
))
1453 LOG_OBJECT("%s/%s\n", id2cstr(mod
->name
), id2cstr(it
.first
))
1457 log("%d objects.\n", total_count
);
1466 if (work_stack
.size() == 0)
1467 log_cmd_error("Nothing to add to selection.\n");
1468 select_op_union(design
, design
->selection_stack
.back(), work_stack
.back());
1469 design
->selection_stack
.back().optimize(design
);
1475 if (work_stack
.size() == 0)
1476 log_cmd_error("Nothing to delete from selection.\n");
1477 select_op_diff(design
, design
->selection_stack
.back(), work_stack
.back());
1478 design
->selection_stack
.back().optimize(design
);
1484 if (work_stack
.size() == 0)
1485 log_cmd_error("No selection to check.\n");
1486 work_stack
.back().optimize(design
);
1487 if (!work_stack
.back().empty())
1489 RTLIL::Selection
*sel
= &work_stack
.back();
1490 sel
->optimize(design
);
1491 std::string desc
= describe_selection_for_assert(design
, sel
);
1492 log_error("Assertion failed: selection is not empty:%s\n%s", sel_str
.c_str(), desc
.c_str());
1499 if (work_stack
.size() == 0)
1500 log_cmd_error("No selection to check.\n");
1501 work_stack
.back().optimize(design
);
1502 if (work_stack
.back().empty())
1504 RTLIL::Selection
*sel
= &work_stack
.back();
1505 sel
->optimize(design
);
1506 std::string desc
= describe_selection_for_assert(design
, sel
);
1507 log_error("Assertion failed: selection is empty:%s\n%s", sel_str
.c_str(), desc
.c_str());
1512 if (assert_count
>= 0 || assert_max
>= 0 || assert_min
>= 0)
1514 int total_count
= 0;
1515 if (work_stack
.size() == 0)
1516 log_cmd_error("No selection to check.\n");
1517 RTLIL::Selection
*sel
= &work_stack
.back();
1518 sel
->optimize(design
);
1519 for (auto mod
: design
->modules())
1520 if (sel
->selected_module(mod
->name
)) {
1521 for (auto wire
: mod
->wires())
1522 if (sel
->selected_member(mod
->name
, wire
->name
))
1524 for (auto &it
: mod
->memories
)
1525 if (sel
->selected_member(mod
->name
, it
.first
))
1527 for (auto cell
: mod
->cells())
1528 if (sel
->selected_member(mod
->name
, cell
->name
))
1530 for (auto &it
: mod
->processes
)
1531 if (sel
->selected_member(mod
->name
, it
.first
))
1534 if (assert_count
>= 0 && assert_count
!= total_count
)
1536 std::string desc
= describe_selection_for_assert(design
, sel
);
1537 log_error("Assertion failed: selection contains %d elements instead of the asserted %d:%s\n%s",
1538 total_count
, assert_count
, sel_str
.c_str(), desc
.c_str());
1540 if (assert_max
>= 0 && assert_max
< total_count
)
1542 std::string desc
= describe_selection_for_assert(design
, sel
);
1543 log_error("Assertion failed: selection contains %d elements, more than the maximum number %d:%s\n%s",
1544 total_count
, assert_max
, sel_str
.c_str(), desc
.c_str());
1546 if (assert_min
>= 0 && assert_min
> total_count
)
1548 std::string desc
= describe_selection_for_assert(design
, sel
);
1549 log_error("Assertion failed: selection contains %d elements, less than the minimum number %d:%s\n%s",
1550 total_count
, assert_min
, sel_str
.c_str(), desc
.c_str());
1555 if (!set_name
.empty())
1557 if (work_stack
.size() == 0)
1558 design
->selection_vars
[set_name
] = RTLIL::Selection(false);
1560 design
->selection_vars
[set_name
] = work_stack
.back();
1564 if (!unset_name
.empty())
1566 if (!design
->selection_vars
.erase(unset_name
))
1567 log_error("Selection '%s' does not exist!\n", unset_name
.c_str());
1571 if (work_stack
.size() == 0) {
1572 RTLIL::Selection
&sel
= design
->selection_stack
.back();
1573 if (sel
.full_selection
)
1575 for (auto &it
: sel
.selected_modules
)
1576 log("%s\n", id2cstr(it
));
1577 for (auto &it
: sel
.selected_members
)
1578 for (auto &it2
: it
.second
)
1579 log("%s/%s\n", id2cstr(it
.first
), id2cstr(it2
));
1583 design
->selection_stack
.back() = work_stack
.back();
1584 design
->selection_stack
.back().optimize(design
);
1588 struct CdPass
: public Pass
{
1589 CdPass() : Pass("cd", "a shortcut for 'select -module <name>'") { }
1590 void help() override
1592 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1594 log(" cd <modname>\n");
1596 log("This is just a shortcut for 'select -module <modname>'.\n");
1599 log(" cd <cellname>\n");
1601 log("When no module with the specified name is found, but there is a cell\n");
1602 log("with the specified name in the current module, then this is equivalent\n");
1603 log("to 'cd <celltype>'.\n");
1607 log("Remove trailing substrings that start with '.' in current module name until\n");
1608 log("the name of a module in the current design is generated, then switch to that\n");
1609 log("module. Otherwise clear the current selection.\n");
1613 log("This is just a shortcut for 'select -clear'.\n");
1616 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) override
1618 if (args
.size() != 1 && args
.size() != 2)
1619 log_cmd_error("Invalid number of arguments.\n");
1621 if (args
.size() == 1 || args
[1] == "/") {
1622 design
->selection_stack
.back() = RTLIL::Selection(true);
1623 design
->selected_active_module
= std::string();
1627 if (args
[1] == "..")
1629 string modname
= design
->selected_active_module
;
1631 design
->selection_stack
.back() = RTLIL::Selection(true);
1632 design
->selected_active_module
= std::string();
1636 size_t pos
= modname
.rfind('.');
1638 if (pos
== string::npos
)
1641 modname
= modname
.substr(0, pos
);
1642 Module
*mod
= design
->module(modname
);
1647 design
->selected_active_module
= modname
;
1648 design
->selection_stack
.back() = RTLIL::Selection();
1649 select_filter_active_mod(design
, design
->selection_stack
.back());
1650 design
->selection_stack
.back().optimize(design
);
1657 std::string modname
= RTLIL::escape_id(args
[1]);
1659 if (design
->module(modname
) == nullptr && !design
->selected_active_module
.empty()) {
1660 RTLIL::Module
*module
= design
->module(design
->selected_active_module
);
1661 if (module
!= nullptr && module
->cell(modname
) != nullptr)
1662 modname
= module
->cell(modname
)->type
.str();
1665 if (design
->module(modname
) != nullptr) {
1666 design
->selected_active_module
= modname
;
1667 design
->selection_stack
.back() = RTLIL::Selection();
1668 select_filter_active_mod(design
, design
->selection_stack
.back());
1669 design
->selection_stack
.back().optimize(design
);
1673 log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname
).c_str());
1677 template<typename T
>
1678 static void log_matches(const char *title
, Module
*module
, const T
&list
)
1680 std::vector
<IdString
> matches
;
1682 for (auto &it
: list
)
1683 if (module
->selected(it
.second
))
1684 matches
.push_back(it
.first
);
1686 if (!matches
.empty()) {
1687 log("\n%d %s:\n", int(matches
.size()), title
);
1688 std::sort(matches
.begin(), matches
.end(), RTLIL::sort_by_id_str());
1689 for (auto id
: matches
)
1690 log(" %s\n", RTLIL::id2cstr(id
));
1694 struct LsPass
: public Pass
{
1695 LsPass() : Pass("ls", "list modules or objects in modules") { }
1696 void help() override
1698 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1700 log(" ls [selection]\n");
1702 log("When no active module is selected, this prints a list of modules.\n");
1704 log("When an active module is selected, this prints a list of objects in the module.\n");
1707 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) override
1710 extra_args(args
, argidx
, design
);
1712 if (design
->selected_active_module
.empty())
1714 std::vector
<IdString
> matches
;
1716 for (auto mod
: design
->selected_modules())
1717 matches
.push_back(mod
->name
);
1719 if (!matches
.empty()) {
1720 log("\n%d %s:\n", int(matches
.size()), "modules");
1721 std::sort(matches
.begin(), matches
.end(), RTLIL::sort_by_id_str());
1722 for (auto id
: matches
)
1723 log(" %s%s\n", log_id(id
), design
->selected_whole_module(design
->module(id
)) ? "" : "*");
1727 if (design
->module(design
->selected_active_module
) != nullptr)
1729 RTLIL::Module
*module
= design
->module(design
->selected_active_module
);
1730 log_matches("wires", module
, module
->wires_
);
1731 log_matches("memories", module
, module
->memories
);
1732 log_matches("cells", module
, module
->cells_
);
1733 log_matches("processes", module
, module
->processes
);
1738 PRIVATE_NAMESPACE_END