2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/sigtools.h"
27 PRIVATE_NAMESPACE_BEGIN
31 static std::vector
<RTLIL::Selection
> work_stack
;
33 static bool match_ids(RTLIL::IdString id
, std::string pattern
)
37 if (id
.size() > 0 && id
[0] == '\\' && id
.substr(1) == pattern
)
39 if (patmatch(pattern
.c_str(), id
.c_str()))
41 if (id
.size() > 0 && id
[0] == '\\' && patmatch(pattern
.c_str(), id
.substr(1).c_str()))
43 if (id
.size() > 0 && id
[0] == '$' && pattern
.size() > 0 && pattern
[0] == '$') {
44 const char *p
= id
.c_str();
45 const char *q
= strrchr(p
, '$');
52 static bool match_attr_val(const RTLIL::Const
&value
, std::string pattern
, char match_op
)
57 if ((value
.flags
& RTLIL::CONST_FLAG_STRING
) == 0)
59 RTLIL::SigSpec sig_value
;
61 if (!RTLIL::SigSpec::parse(sig_value
, NULL
, pattern
))
64 RTLIL::Const pattern_value
= sig_value
.as_const();
67 return value
== pattern_value
;
69 return value
!= pattern_value
;
71 return value
.as_int() < pattern_value
.as_int();
73 return value
.as_int() > pattern_value
.as_int();
75 return value
.as_int() <= pattern_value
.as_int();
77 return value
.as_int() >= pattern_value
.as_int();
81 std::string value_str
= value
.decode_string();
84 if (patmatch(pattern
.c_str(), value
.decode_string().c_str()))
88 return value_str
== pattern
;
90 return value_str
!= pattern
;
92 return value_str
< pattern
;
94 return value_str
> pattern
;
96 return value_str
<= pattern
;
98 return value_str
>= pattern
;
104 static bool match_attr(const dict
<RTLIL::IdString
, RTLIL::Const
> &attributes
, std::string name_pat
, std::string value_pat
, char match_op
)
106 if (name_pat
.find('*') != std::string::npos
|| name_pat
.find('?') != std::string::npos
|| name_pat
.find('[') != std::string::npos
) {
107 for (auto &it
: attributes
) {
108 if (patmatch(name_pat
.c_str(), it
.first
.c_str()) && match_attr_val(it
.second
, value_pat
, match_op
))
110 if (it
.first
.size() > 0 && it
.first
[0] == '\\' && patmatch(name_pat
.c_str(), it
.first
.substr(1).c_str()) && match_attr_val(it
.second
, value_pat
, match_op
))
114 if (name_pat
.size() > 0 && (name_pat
[0] == '\\' || name_pat
[0] == '$') && attributes
.count(name_pat
) && match_attr_val(attributes
.at(name_pat
), value_pat
, match_op
))
116 if (attributes
.count("\\" + name_pat
) && match_attr_val(attributes
.at("\\" + name_pat
), value_pat
, match_op
))
122 static bool match_attr(const dict
<RTLIL::IdString
, RTLIL::Const
> &attributes
, std::string match_expr
)
124 size_t pos
= match_expr
.find_first_of("<!=>");
126 if (pos
!= std::string::npos
) {
127 if (match_expr
.substr(pos
, 2) == "!=")
128 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), '!');
129 if (match_expr
.substr(pos
, 2) == "<=")
130 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), '[');
131 if (match_expr
.substr(pos
, 2) == ">=")
132 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), ']');
133 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+1), match_expr
[pos
]);
136 return match_attr(attributes
, match_expr
, std::string(), 0);
139 static void select_op_neg(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
141 if (lhs
.full_selection
) {
142 lhs
.full_selection
= false;
143 lhs
.selected_modules
.clear();
144 lhs
.selected_members
.clear();
148 if (lhs
.selected_modules
.size() == 0 && lhs
.selected_members
.size() == 0) {
149 lhs
.full_selection
= true;
153 RTLIL::Selection
new_sel(false);
155 for (auto &mod_it
: design
->modules_
)
157 if (lhs
.selected_whole_module(mod_it
.first
))
159 if (!lhs
.selected_module(mod_it
.first
)) {
160 new_sel
.selected_modules
.insert(mod_it
.first
);
164 RTLIL::Module
*mod
= mod_it
.second
;
165 for (auto &it
: mod
->wires_
)
166 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
167 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
168 for (auto &it
: mod
->memories
)
169 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
170 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
171 for (auto &it
: mod
->cells_
)
172 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
173 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
174 for (auto &it
: mod
->processes
)
175 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
176 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
179 lhs
.selected_modules
.swap(new_sel
.selected_modules
);
180 lhs
.selected_members
.swap(new_sel
.selected_members
);
183 static int my_xorshift32_rng() {
184 static uint32_t x32
= 314159265;
188 return x32
& 0x0fffffff;
191 static void select_op_random(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, int count
)
193 vector
<pair
<IdString
, IdString
>> objects
;
195 for (auto mod
: design
->modules())
197 if (!lhs
.selected_module(mod
->name
))
200 for (auto cell
: mod
->cells()) {
201 if (lhs
.selected_member(mod
->name
, cell
->name
))
202 objects
.push_back(make_pair(mod
->name
, cell
->name
));
205 for (auto wire
: mod
->wires()) {
206 if (lhs
.selected_member(mod
->name
, wire
->name
))
207 objects
.push_back(make_pair(mod
->name
, wire
->name
));
211 lhs
= RTLIL::Selection(false);
213 while (!objects
.empty() && count
-- > 0)
215 int idx
= my_xorshift32_rng() % GetSize(objects
);
216 lhs
.selected_members
[objects
[idx
].first
].insert(objects
[idx
].second
);
217 objects
[idx
] = objects
.back();
221 lhs
.optimize(design
);
224 static void select_op_submod(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
226 for (auto &mod_it
: design
->modules_
)
228 if (lhs
.selected_whole_module(mod_it
.first
))
230 for (auto &cell_it
: mod_it
.second
->cells_
)
232 if (design
->modules_
.count(cell_it
.second
->type
) == 0)
234 lhs
.selected_modules
.insert(cell_it
.second
->type
);
240 static void select_op_cells_to_modules(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
242 RTLIL::Selection
new_sel(false);
243 for (auto &mod_it
: design
->modules_
)
244 if (lhs
.selected_module(mod_it
.first
))
245 for (auto &cell_it
: mod_it
.second
->cells_
)
246 if (lhs
.selected_member(mod_it
.first
, cell_it
.first
) && design
->modules_
.count(cell_it
.second
->type
))
247 new_sel
.selected_modules
.insert(cell_it
.second
->type
);
251 static void select_op_module_to_cells(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
253 RTLIL::Selection
new_sel(false);
254 for (auto &mod_it
: design
->modules_
)
255 for (auto &cell_it
: mod_it
.second
->cells_
)
256 if (design
->modules_
.count(cell_it
.second
->type
) && lhs
.selected_whole_module(cell_it
.second
->type
))
257 new_sel
.selected_members
[mod_it
.first
].insert(cell_it
.first
);
261 static void select_op_fullmod(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
263 lhs
.optimize(design
);
264 for (auto &it
: lhs
.selected_members
)
265 lhs
.selected_modules
.insert(it
.first
);
266 lhs
.selected_members
.clear();
269 static void select_op_alias(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
271 for (auto &mod_it
: design
->modules_
)
273 if (lhs
.selected_whole_module(mod_it
.first
))
275 if (!lhs
.selected_module(mod_it
.first
))
278 SigMap
sigmap(mod_it
.second
);
279 SigPool selected_bits
;
281 for (auto &it
: mod_it
.second
->wires_
)
282 if (lhs
.selected_member(mod_it
.first
, it
.first
))
283 selected_bits
.add(sigmap(it
.second
));
285 for (auto &it
: mod_it
.second
->wires_
)
286 if (!lhs
.selected_member(mod_it
.first
, it
.first
) && selected_bits
.check_any(sigmap(it
.second
)))
287 lhs
.selected_members
[mod_it
.first
].insert(it
.first
);
291 static void select_op_union(RTLIL::Design
*, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
293 if (rhs
.full_selection
) {
294 lhs
.full_selection
= true;
295 lhs
.selected_modules
.clear();
296 lhs
.selected_members
.clear();
300 if (lhs
.full_selection
)
303 for (auto &it
: rhs
.selected_members
)
304 for (auto &it2
: it
.second
)
305 lhs
.selected_members
[it
.first
].insert(it2
);
307 for (auto &it
: rhs
.selected_modules
) {
308 lhs
.selected_modules
.insert(it
);
309 lhs
.selected_members
.erase(it
);
313 static void select_op_diff(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
315 if (rhs
.full_selection
) {
316 lhs
.full_selection
= false;
317 lhs
.selected_modules
.clear();
318 lhs
.selected_members
.clear();
322 if (lhs
.full_selection
) {
323 if (!rhs
.full_selection
&& rhs
.selected_modules
.size() == 0 && rhs
.selected_members
.size() == 0)
325 lhs
.full_selection
= false;
326 for (auto &it
: design
->modules_
)
327 lhs
.selected_modules
.insert(it
.first
);
330 for (auto &it
: rhs
.selected_modules
) {
331 lhs
.selected_modules
.erase(it
);
332 lhs
.selected_members
.erase(it
);
335 for (auto &it
: rhs
.selected_members
)
337 if (design
->modules_
.count(it
.first
) == 0)
340 RTLIL::Module
*mod
= design
->modules_
[it
.first
];
342 if (lhs
.selected_modules
.count(mod
->name
) > 0)
344 for (auto &it
: mod
->wires_
)
345 lhs
.selected_members
[mod
->name
].insert(it
.first
);
346 for (auto &it
: mod
->memories
)
347 lhs
.selected_members
[mod
->name
].insert(it
.first
);
348 for (auto &it
: mod
->cells_
)
349 lhs
.selected_members
[mod
->name
].insert(it
.first
);
350 for (auto &it
: mod
->processes
)
351 lhs
.selected_members
[mod
->name
].insert(it
.first
);
352 lhs
.selected_modules
.erase(mod
->name
);
355 if (lhs
.selected_members
.count(mod
->name
) == 0)
358 for (auto &it2
: it
.second
)
359 lhs
.selected_members
[mod
->name
].erase(it2
);
363 static void select_op_intersect(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
365 if (rhs
.full_selection
)
368 if (lhs
.full_selection
) {
369 lhs
.full_selection
= false;
370 for (auto &it
: design
->modules_
)
371 lhs
.selected_modules
.insert(it
.first
);
374 std::vector
<RTLIL::IdString
> del_list
;
376 for (auto &it
: lhs
.selected_modules
)
377 if (rhs
.selected_modules
.count(it
) == 0) {
378 if (rhs
.selected_members
.count(it
) > 0)
379 for (auto &it2
: rhs
.selected_members
.at(it
))
380 lhs
.selected_members
[it
].insert(it2
);
381 del_list
.push_back(it
);
383 for (auto &it
: del_list
)
384 lhs
.selected_modules
.erase(it
);
387 for (auto &it
: lhs
.selected_members
) {
388 if (rhs
.selected_modules
.count(it
.first
) > 0)
390 if (rhs
.selected_members
.count(it
.first
) == 0) {
391 del_list
.push_back(it
.first
);
394 std::vector
<RTLIL::IdString
> del_list2
;
395 for (auto &it2
: it
.second
)
396 if (rhs
.selected_members
.at(it
.first
).count(it2
) == 0)
397 del_list2
.push_back(it2
);
398 for (auto &it2
: del_list2
)
399 it
.second
.erase(it2
);
400 if (it
.second
.size() == 0)
401 del_list
.push_back(it
.first
);
403 for (auto &it
: del_list
)
404 lhs
.selected_members
.erase(it
);
408 struct expand_rule_t
{
410 std::set
<RTLIL::IdString
> cell_types
, port_names
;
414 static int parse_comma_list(std::set
<RTLIL::IdString
> &tokens
, std::string str
, size_t pos
, std::string stopchar
)
418 size_t endpos
= str
.find_first_of(stopchar
, pos
);
419 if (endpos
== std::string::npos
)
422 tokens
.insert(RTLIL::escape_id(str
.substr(pos
, endpos
-pos
)));
424 if (pos
== str
.size() || str
[pos
] != ',')
430 static int select_op_expand(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, std::vector
<expand_rule_t
> &rules
, std::set
<RTLIL::IdString
> &limits
, int max_objects
, char mode
, CellTypes
&ct
, bool eval_only
)
433 bool is_input
, is_output
;
434 for (auto &mod_it
: design
->modules_
)
436 if (lhs
.selected_whole_module(mod_it
.first
) || !lhs
.selected_module(mod_it
.first
))
439 RTLIL::Module
*mod
= mod_it
.second
;
440 std::set
<RTLIL::Wire
*> selected_wires
;
441 auto selected_members
= lhs
.selected_members
[mod
->name
];
443 for (auto &it
: mod
->wires_
)
444 if (lhs
.selected_member(mod_it
.first
, it
.first
) && limits
.count(it
.first
) == 0)
445 selected_wires
.insert(it
.second
);
447 for (auto &conn
: mod
->connections())
449 std::vector
<RTLIL::SigBit
> conn_lhs
= conn
.first
.to_sigbit_vector();
450 std::vector
<RTLIL::SigBit
> conn_rhs
= conn
.second
.to_sigbit_vector();
452 for (size_t i
= 0; i
< conn_lhs
.size(); i
++) {
453 if (conn_lhs
[i
].wire
== NULL
|| conn_rhs
[i
].wire
== NULL
)
455 if (mode
!= 'i' && selected_wires
.count(conn_rhs
[i
].wire
) && selected_members
.count(conn_lhs
[i
].wire
->name
) == 0)
456 lhs
.selected_members
[mod
->name
].insert(conn_lhs
[i
].wire
->name
), sel_objects
++, max_objects
--;
457 if (mode
!= 'o' && selected_wires
.count(conn_lhs
[i
].wire
) && selected_members
.count(conn_rhs
[i
].wire
->name
) == 0)
458 lhs
.selected_members
[mod
->name
].insert(conn_rhs
[i
].wire
->name
), sel_objects
++, max_objects
--;
462 for (auto &cell
: mod
->cells_
)
463 for (auto &conn
: cell
.second
->connections())
465 char last_mode
= '-';
466 if (eval_only
&& !yosys_celltypes
.cell_evaluable(cell
.second
->type
))
468 for (auto &rule
: rules
) {
469 last_mode
= rule
.mode
;
470 if (rule
.cell_types
.size() > 0 && rule
.cell_types
.count(cell
.second
->type
) == 0)
472 if (rule
.port_names
.size() > 0 && rule
.port_names
.count(conn
.first
) == 0)
474 if (rule
.mode
== '+')
479 if (last_mode
== '+')
482 is_input
= mode
== 'x' || ct
.cell_input(cell
.second
->type
, conn
.first
);
483 is_output
= mode
== 'x' || ct
.cell_output(cell
.second
->type
, conn
.first
);
484 for (auto &chunk
: conn
.second
.chunks())
485 if (chunk
.wire
!= NULL
) {
486 if (max_objects
!= 0 && selected_wires
.count(chunk
.wire
) > 0 && selected_members
.count(cell
.first
) == 0)
487 if (mode
== 'x' || (mode
== 'i' && is_output
) || (mode
== 'o' && is_input
))
488 lhs
.selected_members
[mod
->name
].insert(cell
.first
), sel_objects
++, max_objects
--;
489 if (max_objects
!= 0 && selected_members
.count(cell
.first
) > 0 && limits
.count(cell
.first
) == 0 && selected_members
.count(chunk
.wire
->name
) == 0)
490 if (mode
== 'x' || (mode
== 'i' && is_input
) || (mode
== 'o' && is_output
))
491 lhs
.selected_members
[mod
->name
].insert(chunk
.wire
->name
), sel_objects
++, max_objects
--;
500 static void select_op_expand(RTLIL::Design
*design
, std::string arg
, char mode
, bool eval_only
)
502 int pos
= (mode
== 'x' ? 2 : 3) + (eval_only
? 1 : 0);
503 int levels
= 1, rem_objects
= -1;
504 std::vector
<expand_rule_t
> rules
;
505 std::set
<RTLIL::IdString
> limits
;
512 if (pos
< int(arg
.size()) && arg
[pos
] == '*') {
516 if (pos
< int(arg
.size()) && '0' <= arg
[pos
] && arg
[pos
] <= '9') {
517 size_t endpos
= arg
.find_first_not_of("0123456789", pos
);
518 if (endpos
== std::string::npos
)
520 levels
= atoi(arg
.substr(pos
, endpos
-pos
).c_str());
524 if (pos
< int(arg
.size()) && arg
[pos
] == '.') {
525 size_t endpos
= arg
.find_first_not_of("0123456789", ++pos
);
526 if (endpos
== std::string::npos
)
528 if (int(endpos
) > pos
)
529 rem_objects
= atoi(arg
.substr(pos
, endpos
-pos
).c_str());
533 while (pos
< int(arg
.size())) {
534 if (arg
[pos
] != ':' || pos
+1 == int(arg
.size()))
535 log_cmd_error("Syntax error in expand operator '%s'.\n", arg
.c_str());
537 if (arg
[pos
] == '+' || arg
[pos
] == '-') {
539 rule
.mode
= arg
[pos
++];
540 pos
= parse_comma_list(rule
.cell_types
, arg
, pos
, "[:");
541 if (pos
< int(arg
.size()) && arg
[pos
] == '[') {
542 pos
= parse_comma_list(rule
.port_names
, arg
, pos
+1, "]:");
543 if (pos
< int(arg
.size()) && arg
[pos
] == ']')
546 rules
.push_back(rule
);
548 size_t endpos
= arg
.find(':', pos
);
549 if (endpos
== std::string::npos
)
551 if (int(endpos
) > pos
) {
552 std::string str
= arg
.substr(pos
, endpos
-pos
);
554 str
= RTLIL::escape_id(str
.substr(1));
555 if (design
->selection_vars
.count(str
) > 0) {
556 for (auto i1
: design
->selection_vars
.at(str
).selected_members
)
557 for (auto i2
: i1
.second
)
560 log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str
).c_str());
562 limits
.insert(RTLIL::escape_id(str
));
569 log("expand by %d levels (max. %d objects):\n", levels
, rem_objects
);
570 for (auto &rule
: rules
) {
571 log(" rule (%c):\n", rule
.mode
);
572 if (rule
.cell_types
.size() > 0) {
574 for (auto &it
: rule
.cell_types
)
575 log(" %s", it
.c_str());
578 if (rule
.port_names
.size() > 0) {
580 for (auto &it
: rule
.port_names
)
581 log(" %s", it
.c_str());
585 if (limits
.size() > 0) {
587 for (auto &it
: limits
)
588 log(" %s", it
.c_str());
593 while (levels
-- > 0 && rem_objects
!= 0) {
594 int num_objects
= select_op_expand(design
, work_stack
.back(), rules
, limits
, rem_objects
, mode
, ct
, eval_only
);
595 if (num_objects
== 0)
597 rem_objects
-= num_objects
;
600 if (rem_objects
== 0)
601 log_warning("reached configured limit at `%s'.\n", arg
.c_str());
604 static void select_filter_active_mod(RTLIL::Design
*design
, RTLIL::Selection
&sel
)
606 if (design
->selected_active_module
.empty())
609 if (sel
.full_selection
) {
610 sel
.full_selection
= false;
611 sel
.selected_modules
.clear();
612 sel
.selected_members
.clear();
613 sel
.selected_modules
.insert(design
->selected_active_module
);
617 std::vector
<RTLIL::IdString
> del_list
;
618 for (auto mod_name
: sel
.selected_modules
)
619 if (mod_name
!= design
->selected_active_module
)
620 del_list
.push_back(mod_name
);
621 for (auto &it
: sel
.selected_members
)
622 if (it
.first
!= design
->selected_active_module
)
623 del_list
.push_back(it
.first
);
624 for (auto mod_name
: del_list
) {
625 sel
.selected_modules
.erase(mod_name
);
626 sel
.selected_members
.erase(mod_name
);
630 static void select_stmt(RTLIL::Design
*design
, std::string arg
)
632 std::string arg_mod
, arg_memb
;
639 if (design
->selection_stack
.size() > 0)
640 work_stack
.push_back(design
->selection_stack
.back());
643 while (work_stack
.size() > 1) {
644 select_op_union(design
, work_stack
.front(), work_stack
.back());
645 work_stack
.pop_back();
649 if (work_stack
.size() < 1)
650 log_cmd_error("Must have at least one element on the stack for operator %%n.\n");
651 select_op_neg(design
, work_stack
[work_stack
.size()-1]);
654 if (work_stack
.size() < 2)
655 log_cmd_error("Must have at least two elements on the stack for operator %%u.\n");
656 select_op_union(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
657 work_stack
.pop_back();
660 if (work_stack
.size() < 2)
661 log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
662 select_op_diff(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
663 work_stack
.pop_back();
666 if (work_stack
.size() < 2)
667 log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
668 select_op_diff(design
, work_stack
[work_stack
.size()-1], work_stack
[work_stack
.size()-2]);
669 work_stack
[work_stack
.size()-2] = work_stack
[work_stack
.size()-1];
670 work_stack
.pop_back();
673 if (work_stack
.size() < 2)
674 log_cmd_error("Must have at least two elements on the stack for operator %%i.\n");
675 select_op_intersect(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
676 work_stack
.pop_back();
678 if (arg
.size() >= 2 && arg
[0] == '%' && arg
[1] == 'R') {
679 if (work_stack
.size() < 1)
680 log_cmd_error("Must have at least one element on the stack for operator %%R.\n");
681 int count
= arg
.size() > 2 ? atoi(arg
.c_str() + 2) : 1;
682 select_op_random(design
, work_stack
[work_stack
.size()-1], count
);
685 if (work_stack
.size() < 1)
686 log_cmd_error("Must have at least one element on the stack for operator %%s.\n");
687 select_op_submod(design
, work_stack
[work_stack
.size()-1]);
690 if (work_stack
.size() < 1)
691 log_cmd_error("Must have at least one element on the stack for operator %%M.\n");
692 select_op_cells_to_modules(design
, work_stack
[work_stack
.size()-1]);
695 if (work_stack
.size() < 1)
696 log_cmd_error("Must have at least one element on the stack for operator %%M.\n");
697 select_op_module_to_cells(design
, work_stack
[work_stack
.size()-1]);
700 if (work_stack
.size() < 1)
701 log_cmd_error("Must have at least one element on the stack for operator %%c.\n");
702 work_stack
.push_back(work_stack
.back());
705 if (work_stack
.size() < 1)
706 log_cmd_error("Must have at least one element on the stack for operator %%m.\n");
707 select_op_fullmod(design
, work_stack
[work_stack
.size()-1]);
710 if (work_stack
.size() < 1)
711 log_cmd_error("Must have at least one element on the stack for operator %%a.\n");
712 select_op_alias(design
, work_stack
[work_stack
.size()-1]);
714 if (arg
== "%x" || (arg
.size() > 2 && arg
.substr(0, 2) == "%x" && (arg
[2] == ':' || arg
[2] == '*' || arg
[2] == '.' || ('0' <= arg
[2] && arg
[2] <= '9')))) {
715 if (work_stack
.size() < 1)
716 log_cmd_error("Must have at least one element on the stack for operator %%x.\n");
717 select_op_expand(design
, arg
, 'x', false);
719 if (arg
== "%ci" || (arg
.size() > 3 && arg
.substr(0, 3) == "%ci" && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
720 if (work_stack
.size() < 1)
721 log_cmd_error("Must have at least one element on the stack for operator %%ci.\n");
722 select_op_expand(design
, arg
, 'i', false);
724 if (arg
== "%co" || (arg
.size() > 3 && arg
.substr(0, 3) == "%co" && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
725 if (work_stack
.size() < 1)
726 log_cmd_error("Must have at least one element on the stack for operator %%co.\n");
727 select_op_expand(design
, arg
, 'o', false);
729 if (arg
== "%xe" || (arg
.size() > 3 && arg
.substr(0, 3) == "%xe" && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
730 if (work_stack
.size() < 1)
731 log_cmd_error("Must have at least one element on the stack for operator %%xe.\n");
732 select_op_expand(design
, arg
, 'x', true);
734 if (arg
== "%cie" || (arg
.size() > 4 && arg
.substr(0, 4) == "%cie" && (arg
[4] == ':' || arg
[4] == '*' || arg
[4] == '.' || ('0' <= arg
[4] && arg
[4] <= '9')))) {
735 if (work_stack
.size() < 1)
736 log_cmd_error("Must have at least one element on the stack for operator %%cie.\n");
737 select_op_expand(design
, arg
, 'i', true);
739 if (arg
== "%coe" || (arg
.size() > 4 && arg
.substr(0, 4) == "%coe" && (arg
[4] == ':' || arg
[4] == '*' || arg
[4] == '.' || ('0' <= arg
[4] && arg
[4] <= '9')))) {
740 if (work_stack
.size() < 1)
741 log_cmd_error("Must have at least one element on the stack for operator %%coe.\n");
742 select_op_expand(design
, arg
, 'o', true);
744 log_cmd_error("Unknown selection operator '%s'.\n", arg
.c_str());
745 if (work_stack
.size() >= 1)
746 select_filter_active_mod(design
, work_stack
.back());
751 std::string set_name
= RTLIL::escape_id(arg
.substr(1));
752 if (design
->selection_vars
.count(set_name
) > 0)
753 work_stack
.push_back(design
->selection_vars
[set_name
]);
755 log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name
).c_str());
756 select_filter_active_mod(design
, work_stack
.back());
760 if (!design
->selected_active_module
.empty()) {
761 arg_mod
= design
->selected_active_module
;
764 if (GetSize(arg
) >= 2 && arg
[0] >= 'a' && arg
[0] <= 'z' && arg
[1] == ':') {
765 arg_mod
= "*", arg_memb
= arg
;
767 size_t pos
= arg
.find('/');
768 if (pos
== std::string::npos
) {
769 if (arg
.find(':') == std::string::npos
|| arg
.substr(0, 1) == "A")
772 arg_mod
= "*", arg_memb
= arg
;
774 arg_mod
= arg
.substr(0, pos
);
775 arg_memb
= arg
.substr(pos
+1);
779 work_stack
.push_back(RTLIL::Selection());
780 RTLIL::Selection
&sel
= work_stack
.back();
782 if (arg
== "*" && arg_mod
== "*") {
783 select_filter_active_mod(design
, work_stack
.back());
787 sel
.full_selection
= false;
788 for (auto &mod_it
: design
->modules_
)
790 if (arg_mod
.substr(0, 2) == "A:") {
791 if (!match_attr(mod_it
.second
->attributes
, arg_mod
.substr(2)))
794 if (!match_ids(mod_it
.first
, arg_mod
))
797 if (arg_memb
== "") {
798 sel
.selected_modules
.insert(mod_it
.first
);
802 RTLIL::Module
*mod
= mod_it
.second
;
803 if (arg_memb
.substr(0, 2) == "w:") {
804 for (auto &it
: mod
->wires_
)
805 if (match_ids(it
.first
, arg_memb
.substr(2)))
806 sel
.selected_members
[mod
->name
].insert(it
.first
);
808 if (arg_memb
.substr(0, 2) == "i:") {
809 for (auto &it
: mod
->wires_
)
810 if (it
.second
->port_input
&& match_ids(it
.first
, arg_memb
.substr(2)))
811 sel
.selected_members
[mod
->name
].insert(it
.first
);
813 if (arg_memb
.substr(0, 2) == "o:") {
814 for (auto &it
: mod
->wires_
)
815 if (it
.second
->port_output
&& match_ids(it
.first
, arg_memb
.substr(2)))
816 sel
.selected_members
[mod
->name
].insert(it
.first
);
818 if (arg_memb
.substr(0, 2) == "x:") {
819 for (auto &it
: mod
->wires_
)
820 if ((it
.second
->port_input
|| it
.second
->port_output
) && match_ids(it
.first
, arg_memb
.substr(2)))
821 sel
.selected_members
[mod
->name
].insert(it
.first
);
823 if (arg_memb
.substr(0, 2) == "s:") {
824 size_t delim
= arg_memb
.substr(2).find(':');
825 if (delim
== std::string::npos
) {
826 int width
= atoi(arg_memb
.substr(2).c_str());
827 for (auto &it
: mod
->wires_
)
828 if (it
.second
->width
== width
)
829 sel
.selected_members
[mod
->name
].insert(it
.first
);
831 std::string min_str
= arg_memb
.substr(2, delim
);
832 std::string max_str
= arg_memb
.substr(2+delim
+1);
833 int min_width
= min_str
.empty() ? 0 : atoi(min_str
.c_str());
834 int max_width
= max_str
.empty() ? -1 : atoi(max_str
.c_str());
835 for (auto &it
: mod
->wires_
)
836 if (min_width
<= it
.second
->width
&& (it
.second
->width
<= max_width
|| max_width
== -1))
837 sel
.selected_members
[mod
->name
].insert(it
.first
);
840 if (arg_memb
.substr(0, 2) == "m:") {
841 for (auto &it
: mod
->memories
)
842 if (match_ids(it
.first
, arg_memb
.substr(2)))
843 sel
.selected_members
[mod
->name
].insert(it
.first
);
845 if (arg_memb
.substr(0, 2) == "c:") {
846 for (auto &it
: mod
->cells_
)
847 if (match_ids(it
.first
, arg_memb
.substr(2)))
848 sel
.selected_members
[mod
->name
].insert(it
.first
);
850 if (arg_memb
.substr(0, 2) == "t:") {
851 for (auto &it
: mod
->cells_
)
852 if (match_ids(it
.second
->type
, arg_memb
.substr(2)))
853 sel
.selected_members
[mod
->name
].insert(it
.first
);
855 if (arg_memb
.substr(0, 2) == "p:") {
856 for (auto &it
: mod
->processes
)
857 if (match_ids(it
.first
, arg_memb
.substr(2)))
858 sel
.selected_members
[mod
->name
].insert(it
.first
);
860 if (arg_memb
.substr(0, 2) == "a:") {
861 for (auto &it
: mod
->wires_
)
862 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
863 sel
.selected_members
[mod
->name
].insert(it
.first
);
864 for (auto &it
: mod
->memories
)
865 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
866 sel
.selected_members
[mod
->name
].insert(it
.first
);
867 for (auto &it
: mod
->cells_
)
868 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
869 sel
.selected_members
[mod
->name
].insert(it
.first
);
870 for (auto &it
: mod
->processes
)
871 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
872 sel
.selected_members
[mod
->name
].insert(it
.first
);
874 if (arg_memb
.substr(0, 2) == "r:") {
875 for (auto &it
: mod
->cells_
)
876 if (match_attr(it
.second
->parameters
, arg_memb
.substr(2)))
877 sel
.selected_members
[mod
->name
].insert(it
.first
);
879 if (arg_memb
.substr(0, 2) == "n:")
880 arg_memb
= arg_memb
.substr(2);
881 for (auto &it
: mod
->wires_
)
882 if (match_ids(it
.first
, arg_memb
))
883 sel
.selected_members
[mod
->name
].insert(it
.first
);
884 for (auto &it
: mod
->memories
)
885 if (match_ids(it
.first
, arg_memb
))
886 sel
.selected_members
[mod
->name
].insert(it
.first
);
887 for (auto &it
: mod
->cells_
)
888 if (match_ids(it
.first
, arg_memb
))
889 sel
.selected_members
[mod
->name
].insert(it
.first
);
890 for (auto &it
: mod
->processes
)
891 if (match_ids(it
.first
, arg_memb
))
892 sel
.selected_members
[mod
->name
].insert(it
.first
);
896 select_filter_active_mod(design
, work_stack
.back());
899 static std::string
describe_selection_for_assert(RTLIL::Design
*design
, RTLIL::Selection
*sel
)
901 std::string desc
= "Selection contains:\n";
902 for (auto mod_it
: design
->modules_
)
904 if (sel
->selected_module(mod_it
.first
)) {
905 for (auto &it
: mod_it
.second
->wires_
)
906 if (sel
->selected_member(mod_it
.first
, it
.first
))
907 desc
+= stringf("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
));
908 for (auto &it
: mod_it
.second
->memories
)
909 if (sel
->selected_member(mod_it
.first
, it
.first
))
910 desc
+= stringf("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
));
911 for (auto &it
: mod_it
.second
->cells_
)
912 if (sel
->selected_member(mod_it
.first
, it
.first
))
913 desc
+= stringf("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
));
914 for (auto &it
: mod_it
.second
->processes
)
915 if (sel
->selected_member(mod_it
.first
, it
.first
))
916 desc
+= stringf("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
));
922 PRIVATE_NAMESPACE_END
923 YOSYS_NAMESPACE_BEGIN
925 // used in kernel/register.cc and maybe other locations, extern decl. in register.h
926 void handle_extra_select_args(Pass
*pass
, vector
<string
> args
, size_t argidx
, size_t args_size
, RTLIL::Design
*design
)
929 for (; argidx
< args_size
; argidx
++) {
930 if (args
[argidx
].substr(0, 1) == "-") {
932 pass
->cmd_error(args
, argidx
, "Unexpected option in selection arguments.");
934 log_cmd_error("Unexpected option in selection arguments.");
936 select_stmt(design
, args
[argidx
]);
938 while (work_stack
.size() > 1) {
939 select_op_union(design
, work_stack
.front(), work_stack
.back());
940 work_stack
.pop_back();
942 if (work_stack
.empty())
943 design
->selection_stack
.push_back(RTLIL::Selection(false));
945 design
->selection_stack
.push_back(work_stack
.back());
948 // extern decl. in register.h
949 RTLIL::Selection
eval_select_args(const vector
<string
> &args
, RTLIL::Design
*design
)
952 for (auto &arg
: args
)
953 select_stmt(design
, arg
);
954 while (work_stack
.size() > 1) {
955 select_op_union(design
, work_stack
.front(), work_stack
.back());
956 work_stack
.pop_back();
958 if (work_stack
.empty())
959 return RTLIL::Selection(false);
960 return work_stack
.back();
963 // extern decl. in register.h
964 void eval_select_op(vector
<RTLIL::Selection
> &work
, const string
&op
, RTLIL::Design
*design
)
966 work_stack
.swap(work
);
967 select_stmt(design
, op
);
968 work_stack
.swap(work
);
972 PRIVATE_NAMESPACE_BEGIN
974 struct SelectPass
: public Pass
{
975 SelectPass() : Pass("select", "modify and view the list of selected objects") { }
976 void help() YS_OVERRIDE
978 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
980 log(" select [ -add | -del | -set <name> ] {-read <filename> | <selection>}\n");
981 log(" select [ <assert_option> ] {-read <filename> | <selection>}\n");
982 log(" select [ -list | -write <filename> | -count | -clear ]\n");
983 log(" select -module <modname>\n");
985 log("Most commands use the list of currently selected objects to determine which part\n");
986 log("of the design to operate on. This command can be used to modify and view this\n");
987 log("list of selected objects.\n");
989 log("Note that many commands support an optional [selection] argument that can be\n");
990 log("used to override the global selection for the command. The syntax of this\n");
991 log("optional argument is identical to the syntax of the <selection> argument\n");
992 log("described here.\n");
994 log(" -add, -del\n");
995 log(" add or remove the given objects to the current selection.\n");
996 log(" without this options the current selection is replaced.\n");
998 log(" -set <name>\n");
999 log(" do not modify the current selection. instead save the new selection\n");
1000 log(" under the given name (see @<name> below). to save the current selection,\n");
1001 log(" use \"select -set <name> %%\"\n");
1003 log(" -assert-none\n");
1004 log(" do not modify the current selection. instead assert that the given\n");
1005 log(" selection is empty. i.e. produce an error if any object matching the\n");
1006 log(" selection is found.\n");
1008 log(" -assert-any\n");
1009 log(" do not modify the current selection. instead assert that the given\n");
1010 log(" selection is non-empty. i.e. produce an error if no object matching\n");
1011 log(" the selection is found.\n");
1013 log(" -assert-count N\n");
1014 log(" do not modify the current selection. instead assert that the given\n");
1015 log(" selection contains exactly N objects.\n");
1017 log(" -assert-max N\n");
1018 log(" do not modify the current selection. instead assert that the given\n");
1019 log(" selection contains less than or exactly N objects.\n");
1021 log(" -assert-min N\n");
1022 log(" do not modify the current selection. instead assert that the given\n");
1023 log(" selection contains at least N objects.\n");
1026 log(" list all objects in the current selection\n");
1028 log(" -write <filename>\n");
1029 log(" like -list but write the output to the specified file\n");
1031 log(" -read <filename>\n");
1032 log(" read the specified file (written by -write)\n");
1035 log(" count all objects in the current selection\n");
1038 log(" clear the current selection. this effectively selects the whole\n");
1039 log(" design. it also resets the selected module (see -module). use the\n");
1040 log(" command 'select *' to select everything but stay in the current module.\n");
1043 log(" create an empty selection. the current module is unchanged.\n");
1045 log(" -module <modname>\n");
1046 log(" limit the current scope to the specified module.\n");
1047 log(" the difference between this and simply selecting the module\n");
1048 log(" is that all object names are interpreted relative to this\n");
1049 log(" module after this command until the selection is cleared again.\n");
1051 log("When this command is called without an argument, the current selection\n");
1052 log("is displayed in a compact form (i.e. only the module name when a whole module\n");
1053 log("is selected).\n");
1055 log("The <selection> argument itself is a series of commands for a simple stack\n");
1056 log("machine. Each element on the stack represents a set of selected objects.\n");
1057 log("After this commands have been executed, the union of all remaining sets\n");
1058 log("on the stack is computed and used as selection for the command.\n");
1060 log("Pushing (selecting) object when not in -module mode:\n");
1062 log(" <mod_pattern>\n");
1063 log(" select the specified module(s)\n");
1065 log(" <mod_pattern>/<obj_pattern>\n");
1066 log(" select the specified object(s) from the module(s)\n");
1068 log("Pushing (selecting) object when in -module mode:\n");
1070 log(" <obj_pattern>\n");
1071 log(" select the specified object(s) from the current module\n");
1073 log("A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])\n");
1074 log("matching module names, or one of the following:\n");
1076 log(" A:<pattern>, A:<pattern>=<pattern>\n");
1077 log(" all modules with an attribute matching the given pattern\n");
1078 log(" in addition to = also <, <=, >=, and > are supported\n");
1080 log("An <obj_pattern> can be an object name, wildcard expression, or one of\n");
1081 log("the following:\n");
1083 log(" w:<pattern>\n");
1084 log(" all wires with a name matching the given wildcard pattern\n");
1086 log(" i:<pattern>, o:<pattern>, x:<pattern>\n");
1087 log(" all inputs (i:), outputs (o:) or any ports (x:) with matching names\n");
1089 log(" s:<size>, s:<min>:<max>\n");
1090 log(" all wires with a matching width\n");
1092 log(" m:<pattern>\n");
1093 log(" all memories with a name matching the given pattern\n");
1095 log(" c:<pattern>\n");
1096 log(" all cells with a name matching the given pattern\n");
1098 log(" t:<pattern>\n");
1099 log(" all cells with a type matching the given pattern\n");
1101 log(" p:<pattern>\n");
1102 log(" all processes with a name matching the given pattern\n");
1104 log(" a:<pattern>\n");
1105 log(" all objects with an attribute name matching the given pattern\n");
1107 log(" a:<pattern>=<pattern>\n");
1108 log(" all objects with a matching attribute name-value-pair.\n");
1109 log(" in addition to = also <, <=, >=, and > are supported\n");
1111 log(" r:<pattern>, r:<pattern>=<pattern>\n");
1112 log(" cells with matching parameters. also with <, <=, >= and >.\n");
1114 log(" n:<pattern>\n");
1115 log(" all objects with a name matching the given pattern\n");
1116 log(" (i.e. 'n:' is optional as it is the default matching rule)\n");
1119 log(" push the selection saved prior with 'select -set <name> ...'\n");
1121 log("The following actions can be performed on the top sets on the stack:\n");
1124 log(" push a copy of the current selection to the stack\n");
1127 log(" replace the stack with a union of all elements on it\n");
1130 log(" replace top set with its invert\n");
1133 log(" replace the two top sets on the stack with their union\n");
1136 log(" replace the two top sets on the stack with their intersection\n");
1139 log(" pop the top set from the stack and subtract it from the new top\n");
1142 log(" like %%d but swap the roles of two top sets on the stack\n");
1145 log(" create a copy of the top set from the stack and push it\n");
1147 log(" %%x[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
1148 log(" expand top set <num1> num times according to the specified rules.\n");
1149 log(" (i.e. select all cells connected to selected wires and select all\n");
1150 log(" wires connected to selected cells) The rules specify which cell\n");
1151 log(" ports to use for this. the syntax for a rule is a '-' for exclusion\n");
1152 log(" and a '+' for inclusion, followed by an optional comma separated\n");
1153 log(" list of cell types followed by an optional comma separated list of\n");
1154 log(" cell ports in square brackets. a rule can also be just a cell or wire\n");
1155 log(" name that limits the expansion (is included but does not go beyond).\n");
1156 log(" select at most <num2> objects. a warning message is printed when this\n");
1157 log(" limit is reached. When '*' is used instead of <num1> then the process\n");
1158 log(" is repeated until no further object are selected.\n");
1160 log(" %%ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
1161 log(" %%co[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
1162 log(" similar to %%x, but only select input (%%ci) or output cones (%%co)\n");
1164 log(" %%xe[...] %%cie[...] %%coe\n");
1165 log(" like %%x, %%ci, and %%co but only consider combinatorial cells\n");
1168 log(" expand top set by selecting all wires that are (at least in part)\n");
1169 log(" aliases for selected wires.\n");
1172 log(" expand top set by adding all modules that implement cells in selected\n");
1176 log(" expand top set by selecting all modules that contain selected objects\n");
1179 log(" select modules that implement selected cells\n");
1182 log(" select cells that implement selected modules\n");
1184 log(" %%R[<num>]\n");
1185 log(" select <num> random objects from top selection (default 1)\n");
1187 log("Example: the following command selects all wires that are connected to a\n");
1188 log("'GATE' input of a 'SWITCH' cell:\n");
1190 log(" select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n");
1193 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1195 bool add_mode
= false;
1196 bool del_mode
= false;
1197 bool clear_mode
= false;
1198 bool none_mode
= false;
1199 bool list_mode
= false;
1200 bool count_mode
= false;
1201 bool got_module
= false;
1202 bool assert_none
= false;
1203 bool assert_any
= false;
1204 int assert_count
= -1;
1205 int assert_max
= -1;
1206 int assert_min
= -1;
1207 std::string write_file
, read_file
;
1208 std::string set_name
, sel_str
;
1213 for (argidx
= 1; argidx
< args
.size(); argidx
++)
1215 std::string arg
= args
[argidx
];
1216 if (arg
== "-add") {
1220 if (arg
== "-del") {
1224 if (arg
== "-assert-none") {
1228 if (arg
== "-assert-any") {
1232 if (arg
== "-assert-count" && argidx
+1 < args
.size()) {
1233 assert_count
= atoi(args
[++argidx
].c_str());
1236 if (arg
== "-assert-max" && argidx
+1 < args
.size()) {
1237 assert_max
= atoi(args
[++argidx
].c_str());
1240 if (arg
== "-assert-min" && argidx
+1 < args
.size()) {
1241 assert_min
= atoi(args
[++argidx
].c_str());
1244 if (arg
== "-clear") {
1248 if (arg
== "-none") {
1252 if (arg
== "-list") {
1256 if (arg
== "-write" && argidx
+1 < args
.size()) {
1257 write_file
= args
[++argidx
];
1260 if (arg
== "-read" && argidx
+1 < args
.size()) {
1261 read_file
= args
[++argidx
];
1264 if (arg
== "-count") {
1268 if (arg
== "-module" && argidx
+1 < args
.size()) {
1269 RTLIL::IdString mod_name
= RTLIL::escape_id(args
[++argidx
]);
1270 if (design
->modules_
.count(mod_name
) == 0)
1271 log_cmd_error("No such module: %s\n", id2cstr(mod_name
));
1272 design
->selected_active_module
= mod_name
.str();
1276 if (arg
== "-set" && argidx
+1 < args
.size()) {
1277 set_name
= RTLIL::escape_id(args
[++argidx
]);
1280 if (arg
.size() > 0 && arg
[0] == '-')
1281 log_cmd_error("Unknown option %s.\n", arg
.c_str());
1282 select_stmt(design
, arg
);
1283 sel_str
+= " " + arg
;
1286 if (!read_file
.empty())
1288 if (!sel_str
.empty())
1289 log_cmd_error("Option -read can not be combined with a selection expression.\n");
1291 std::ifstream
f(read_file
);
1292 yosys_input_files
.insert(read_file
);
1294 log_error("Can't open '%s' for reading: %s\n", read_file
.c_str(), strerror(errno
));
1296 RTLIL::Selection
sel(false);
1299 while (std::getline(f
, line
)) {
1300 size_t slash_pos
= line
.find('/');
1301 if (slash_pos
== string::npos
) {
1302 log_warning("Ignoring line without slash in 'select -read': %s\n", line
.c_str());
1305 IdString mod_name
= RTLIL::escape_id(line
.substr(0, slash_pos
));
1306 IdString obj_name
= RTLIL::escape_id(line
.substr(slash_pos
+1));
1307 sel
.selected_members
[mod_name
].insert(obj_name
);
1310 select_filter_active_mod(design
, sel
);
1311 sel
.optimize(design
);
1312 work_stack
.push_back(sel
);
1315 if (clear_mode
&& args
.size() != 2)
1316 log_cmd_error("Option -clear can not be combined with any other options.\n");
1318 if (none_mode
&& args
.size() != 2)
1319 log_cmd_error("Option -none can not be combined with any other options.\n");
1321 if (add_mode
+ del_mode
+ assert_none
+ assert_any
+ (assert_count
>= 0) + (assert_max
>= 0) + (assert_min
>= 0) > 1)
1322 log_cmd_error("Options -add, -del, -assert-none, -assert-any, assert-count, -assert-max or -assert-min can not be combined.\n");
1324 if ((list_mode
|| !write_file
.empty() || count_mode
) && (add_mode
|| del_mode
|| assert_none
|| assert_any
|| assert_count
>= 0 || assert_max
>= 0 || assert_min
>= 0))
1325 log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none, -assert-any, assert-count, -assert-max, or -assert-min.\n");
1327 if (!set_name
.empty() && (list_mode
|| !write_file
.empty() || count_mode
|| add_mode
|| del_mode
|| assert_none
|| assert_any
|| assert_count
>= 0 || assert_max
>= 0 || assert_min
>= 0))
1328 log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
1330 if (work_stack
.size() == 0 && got_module
) {
1331 RTLIL::Selection sel
;
1332 select_filter_active_mod(design
, sel
);
1333 work_stack
.push_back(sel
);
1336 while (work_stack
.size() > 1) {
1337 select_op_union(design
, work_stack
.front(), work_stack
.back());
1338 work_stack
.pop_back();
1341 log_assert(design
->selection_stack
.size() > 0);
1344 design
->selection_stack
.back() = RTLIL::Selection(true);
1345 design
->selected_active_module
= std::string();
1350 design
->selection_stack
.back() = RTLIL::Selection(false);
1354 if (list_mode
|| count_mode
|| !write_file
.empty())
1356 #define LOG_OBJECT(...) { if (list_mode) log(__VA_ARGS__); if (f != NULL) fprintf(f, __VA_ARGS__); total_count++; }
1357 int total_count
= 0;
1359 if (!write_file
.empty()) {
1360 f
= fopen(write_file
.c_str(), "w");
1361 yosys_output_files
.insert(write_file
);
1363 log_error("Can't open '%s' for writing: %s\n", write_file
.c_str(), strerror(errno
));
1365 RTLIL::Selection
*sel
= &design
->selection_stack
.back();
1366 if (work_stack
.size() > 0)
1367 sel
= &work_stack
.back();
1368 sel
->optimize(design
);
1369 for (auto mod_it
: design
->modules_
)
1371 if (sel
->selected_whole_module(mod_it
.first
) && list_mode
)
1372 log("%s\n", id2cstr(mod_it
.first
));
1373 if (sel
->selected_module(mod_it
.first
)) {
1374 for (auto &it
: mod_it
.second
->wires_
)
1375 if (sel
->selected_member(mod_it
.first
, it
.first
))
1376 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
))
1377 for (auto &it
: mod_it
.second
->memories
)
1378 if (sel
->selected_member(mod_it
.first
, it
.first
))
1379 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
))
1380 for (auto &it
: mod_it
.second
->cells_
)
1381 if (sel
->selected_member(mod_it
.first
, it
.first
))
1382 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
))
1383 for (auto &it
: mod_it
.second
->processes
)
1384 if (sel
->selected_member(mod_it
.first
, it
.first
))
1385 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
))
1389 log("%d objects.\n", total_count
);
1398 if (work_stack
.size() == 0)
1399 log_cmd_error("Nothing to add to selection.\n");
1400 select_op_union(design
, design
->selection_stack
.back(), work_stack
.back());
1401 design
->selection_stack
.back().optimize(design
);
1407 if (work_stack
.size() == 0)
1408 log_cmd_error("Nothing to delete from selection.\n");
1409 select_op_diff(design
, design
->selection_stack
.back(), work_stack
.back());
1410 design
->selection_stack
.back().optimize(design
);
1416 if (work_stack
.size() == 0)
1417 log_cmd_error("No selection to check.\n");
1418 work_stack
.back().optimize(design
);
1419 if (!work_stack
.back().empty())
1421 RTLIL::Selection
*sel
= &work_stack
.back();
1422 sel
->optimize(design
);
1423 std::string desc
= describe_selection_for_assert(design
, sel
);
1424 log_error("Assertion failed: selection is not empty:%s\n%s", sel_str
.c_str(), desc
.c_str());
1431 if (work_stack
.size() == 0)
1432 log_cmd_error("No selection to check.\n");
1433 work_stack
.back().optimize(design
);
1434 if (work_stack
.back().empty())
1436 RTLIL::Selection
*sel
= &work_stack
.back();
1437 sel
->optimize(design
);
1438 std::string desc
= describe_selection_for_assert(design
, sel
);
1439 log_error("Assertion failed: selection is empty:%s\n%s", sel_str
.c_str(), desc
.c_str());
1444 if (assert_count
>= 0 || assert_max
>= 0 || assert_min
>= 0)
1446 int total_count
= 0;
1447 if (work_stack
.size() == 0)
1448 log_cmd_error("No selection to check.\n");
1449 RTLIL::Selection
*sel
= &work_stack
.back();
1450 sel
->optimize(design
);
1451 for (auto mod_it
: design
->modules_
)
1452 if (sel
->selected_module(mod_it
.first
)) {
1453 for (auto &it
: mod_it
.second
->wires_
)
1454 if (sel
->selected_member(mod_it
.first
, it
.first
))
1456 for (auto &it
: mod_it
.second
->memories
)
1457 if (sel
->selected_member(mod_it
.first
, it
.first
))
1459 for (auto &it
: mod_it
.second
->cells_
)
1460 if (sel
->selected_member(mod_it
.first
, it
.first
))
1462 for (auto &it
: mod_it
.second
->processes
)
1463 if (sel
->selected_member(mod_it
.first
, it
.first
))
1466 if (assert_count
>= 0 && assert_count
!= total_count
)
1468 std::string desc
= describe_selection_for_assert(design
, sel
);
1469 log_error("Assertion failed: selection contains %d elements instead of the asserted %d:%s\n%s",
1470 total_count
, assert_count
, sel_str
.c_str(), desc
.c_str());
1472 if (assert_max
>= 0 && assert_max
< total_count
)
1474 std::string desc
= describe_selection_for_assert(design
, sel
);
1475 log_error("Assertion failed: selection contains %d elements, more than the maximum number %d:%s\n%s",
1476 total_count
, assert_max
, sel_str
.c_str(), desc
.c_str());
1478 if (assert_min
>= 0 && assert_min
> total_count
)
1480 std::string desc
= describe_selection_for_assert(design
, sel
);
1481 log_error("Assertion failed: selection contains %d elements, less than the minimum number %d:%s\n%s",
1482 total_count
, assert_min
, sel_str
.c_str(), desc
.c_str());
1487 if (!set_name
.empty())
1489 if (work_stack
.size() == 0)
1490 design
->selection_vars
[set_name
] = RTLIL::Selection(false);
1492 design
->selection_vars
[set_name
] = work_stack
.back();
1496 if (work_stack
.size() == 0) {
1497 RTLIL::Selection
&sel
= design
->selection_stack
.back();
1498 if (sel
.full_selection
)
1500 for (auto &it
: sel
.selected_modules
)
1501 log("%s\n", id2cstr(it
));
1502 for (auto &it
: sel
.selected_members
)
1503 for (auto &it2
: it
.second
)
1504 log("%s/%s\n", id2cstr(it
.first
), id2cstr(it2
));
1508 design
->selection_stack
.back() = work_stack
.back();
1509 design
->selection_stack
.back().optimize(design
);
1513 struct CdPass
: public Pass
{
1514 CdPass() : Pass("cd", "a shortcut for 'select -module <name>'") { }
1515 void help() YS_OVERRIDE
1517 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1519 log(" cd <modname>\n");
1521 log("This is just a shortcut for 'select -module <modname>'.\n");
1524 log(" cd <cellname>\n");
1526 log("When no module with the specified name is found, but there is a cell\n");
1527 log("with the specified name in the current module, then this is equivalent\n");
1528 log("to 'cd <celltype>'.\n");
1532 log("Remove trailing substrings that start with '.' in current module name until\n");
1533 log("the name of a module in the current design is generated, then switch to that\n");
1534 log("module. Otherwise clear the current selection.\n");
1538 log("This is just a shortcut for 'select -clear'.\n");
1541 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1543 if (args
.size() != 1 && args
.size() != 2)
1544 log_cmd_error("Invalid number of arguments.\n");
1546 if (args
.size() == 1 || args
[1] == "/") {
1547 design
->selection_stack
.back() = RTLIL::Selection(true);
1548 design
->selected_active_module
= std::string();
1552 if (args
[1] == "..")
1554 string modname
= design
->selected_active_module
;
1556 design
->selection_stack
.back() = RTLIL::Selection(true);
1557 design
->selected_active_module
= std::string();
1561 size_t pos
= modname
.rfind('.');
1563 if (pos
== string::npos
)
1566 modname
= modname
.substr(0, pos
);
1567 Module
*mod
= design
->module(modname
);
1572 design
->selected_active_module
= modname
;
1573 design
->selection_stack
.back() = RTLIL::Selection();
1574 select_filter_active_mod(design
, design
->selection_stack
.back());
1575 design
->selection_stack
.back().optimize(design
);
1582 std::string modname
= RTLIL::escape_id(args
[1]);
1584 if (design
->modules_
.count(modname
) == 0 && !design
->selected_active_module
.empty()) {
1585 RTLIL::Module
*module
= NULL
;
1586 if (design
->modules_
.count(design
->selected_active_module
) > 0)
1587 module
= design
->modules_
.at(design
->selected_active_module
);
1588 if (module
!= NULL
&& module
->cells_
.count(modname
) > 0)
1589 modname
= module
->cells_
.at(modname
)->type
.str();
1592 if (design
->modules_
.count(modname
) > 0) {
1593 design
->selected_active_module
= modname
;
1594 design
->selection_stack
.back() = RTLIL::Selection();
1595 select_filter_active_mod(design
, design
->selection_stack
.back());
1596 design
->selection_stack
.back().optimize(design
);
1600 log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname
).c_str());
1604 template<typename T
>
1605 static void log_matches(const char *title
, Module
*module
, T list
)
1607 std::vector
<IdString
> matches
;
1609 for (auto &it
: list
)
1610 if (module
->selected(it
.second
))
1611 matches
.push_back(it
.first
);
1613 if (!matches
.empty()) {
1614 log("\n%d %s:\n", int(matches
.size()), title
);
1615 std::sort(matches
.begin(), matches
.end(), RTLIL::sort_by_id_str());
1616 for (auto id
: matches
)
1617 log(" %s\n", RTLIL::id2cstr(id
));
1621 struct LsPass
: public Pass
{
1622 LsPass() : Pass("ls", "list modules or objects in modules") { }
1623 void help() YS_OVERRIDE
1625 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1627 log(" ls [selection]\n");
1629 log("When no active module is selected, this prints a list of modules.\n");
1631 log("When an active module is selected, this prints a list of objects in the module.\n");
1634 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1637 extra_args(args
, argidx
, design
);
1639 if (design
->selected_active_module
.empty())
1641 std::vector
<IdString
> matches
;
1643 for (auto mod
: design
->selected_modules())
1644 matches
.push_back(mod
->name
);
1646 if (!matches
.empty()) {
1647 log("\n%d %s:\n", int(matches
.size()), "modules");
1648 std::sort(matches
.begin(), matches
.end(), RTLIL::sort_by_id_str());
1649 for (auto id
: matches
)
1650 log(" %s%s\n", log_id(id
), design
->selected_whole_module(design
->module(id
)) ? "" : "*");
1654 if (design
->module(design
->selected_active_module
) != nullptr)
1656 RTLIL::Module
*module
= design
->module(design
->selected_active_module
);
1657 log_matches("wires", module
, module
->wires_
);
1658 log_matches("memories", module
, module
->memories
);
1659 log_matches("cells", module
, module
->cells_
);
1660 log_matches("processes", module
, module
->processes
);
1665 PRIVATE_NAMESPACE_END