b64b077e4ca191633874444610e09374d71cc32a
2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/sigtools.h"
27 PRIVATE_NAMESPACE_BEGIN
31 static std::vector
<RTLIL::Selection
> work_stack
;
33 static bool match_ids(RTLIL::IdString id
, std::string pattern
)
37 if (id
.size() > 0 && id
[0] == '\\' && id
.compare(1, std::string::npos
, pattern
.c_str()) == 0)
39 if (patmatch(pattern
.c_str(), id
.c_str()))
41 if (id
.size() > 0 && id
[0] == '\\' && patmatch(pattern
.c_str(), id
.substr(1).c_str()))
43 if (id
.size() > 0 && id
[0] == '$' && pattern
.size() > 0 && pattern
[0] == '$') {
44 const char *p
= id
.c_str();
45 const char *q
= strrchr(p
, '$');
52 static bool match_attr_val(const RTLIL::Const
&value
, std::string pattern
, char match_op
)
57 if ((value
.flags
& RTLIL::CONST_FLAG_STRING
) == 0)
59 RTLIL::SigSpec sig_value
;
61 if (!RTLIL::SigSpec::parse(sig_value
, nullptr, pattern
))
64 RTLIL::Const pattern_value
= sig_value
.as_const();
67 return value
== pattern_value
;
69 return value
!= pattern_value
;
71 return value
.as_int() < pattern_value
.as_int();
73 return value
.as_int() > pattern_value
.as_int();
75 return value
.as_int() <= pattern_value
.as_int();
77 return value
.as_int() >= pattern_value
.as_int();
81 std::string value_str
= value
.decode_string();
84 if (patmatch(pattern
.c_str(), value
.decode_string().c_str()))
88 return value_str
== pattern
;
90 return value_str
!= pattern
;
92 return value_str
< pattern
;
94 return value_str
> pattern
;
96 return value_str
<= pattern
;
98 return value_str
>= pattern
;
104 static bool match_attr(const dict
<RTLIL::IdString
, RTLIL::Const
> &attributes
, std::string name_pat
, std::string value_pat
, char match_op
)
106 if (name_pat
.find('*') != std::string::npos
|| name_pat
.find('?') != std::string::npos
|| name_pat
.find('[') != std::string::npos
) {
107 for (auto &it
: attributes
) {
108 if (patmatch(name_pat
.c_str(), it
.first
.c_str()) && match_attr_val(it
.second
, value_pat
, match_op
))
110 if (it
.first
.size() > 0 && it
.first
[0] == '\\' && patmatch(name_pat
.c_str(), it
.first
.substr(1).c_str()) && match_attr_val(it
.second
, value_pat
, match_op
))
114 if (name_pat
.size() > 0 && (name_pat
[0] == '\\' || name_pat
[0] == '$') && attributes
.count(name_pat
) && match_attr_val(attributes
.at(name_pat
), value_pat
, match_op
))
116 if (attributes
.count("\\" + name_pat
) && match_attr_val(attributes
.at("\\" + name_pat
), value_pat
, match_op
))
122 static bool match_attr(const dict
<RTLIL::IdString
, RTLIL::Const
> &attributes
, std::string match_expr
)
124 size_t pos
= match_expr
.find_first_of("<!=>");
126 if (pos
!= std::string::npos
) {
127 if (match_expr
.compare(pos
, 2, "!=") == 0)
128 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), '!');
129 if (match_expr
.compare(pos
, 2, "<=") == 0)
130 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), '[');
131 if (match_expr
.compare(pos
, 2, ">=") == 0)
132 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), ']');
133 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+1), match_expr
[pos
]);
136 return match_attr(attributes
, match_expr
, std::string(), 0);
139 static void select_op_neg(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
141 if (lhs
.full_selection
) {
142 lhs
.full_selection
= false;
143 lhs
.selected_modules
.clear();
144 lhs
.selected_members
.clear();
148 if (lhs
.selected_modules
.size() == 0 && lhs
.selected_members
.size() == 0) {
149 lhs
.full_selection
= true;
153 RTLIL::Selection
new_sel(false);
155 for (auto mod
: design
->modules())
157 if (lhs
.selected_whole_module(mod
->name
))
159 if (!lhs
.selected_module(mod
->name
)) {
160 new_sel
.selected_modules
.insert(mod
->name
);
164 for (auto wire
: mod
->wires())
165 if (!lhs
.selected_member(mod
->name
, wire
->name
))
166 new_sel
.selected_members
[mod
->name
].insert(wire
->name
);
167 for (auto &it
: mod
->memories
)
168 if (!lhs
.selected_member(mod
->name
, it
.first
))
169 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
170 for (auto cell
: mod
->cells())
171 if (!lhs
.selected_member(mod
->name
, cell
->name
))
172 new_sel
.selected_members
[mod
->name
].insert(cell
->name
);
173 for (auto &it
: mod
->processes
)
174 if (!lhs
.selected_member(mod
->name
, it
.first
))
175 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
178 lhs
.selected_modules
.swap(new_sel
.selected_modules
);
179 lhs
.selected_members
.swap(new_sel
.selected_members
);
182 static int my_xorshift32_rng() {
183 static uint32_t x32
= 314159265;
187 return x32
& 0x0fffffff;
190 static void select_op_random(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, int count
)
192 vector
<pair
<IdString
, IdString
>> objects
;
194 for (auto mod
: design
->modules())
196 if (!lhs
.selected_module(mod
->name
))
199 for (auto cell
: mod
->cells()) {
200 if (lhs
.selected_member(mod
->name
, cell
->name
))
201 objects
.push_back(make_pair(mod
->name
, cell
->name
));
204 for (auto wire
: mod
->wires()) {
205 if (lhs
.selected_member(mod
->name
, wire
->name
))
206 objects
.push_back(make_pair(mod
->name
, wire
->name
));
210 lhs
= RTLIL::Selection(false);
212 while (!objects
.empty() && count
-- > 0)
214 int idx
= my_xorshift32_rng() % GetSize(objects
);
215 lhs
.selected_members
[objects
[idx
].first
].insert(objects
[idx
].second
);
216 objects
[idx
] = objects
.back();
220 lhs
.optimize(design
);
223 static void select_op_submod(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
225 for (auto mod
: design
->modules())
227 if (lhs
.selected_whole_module(mod
->name
))
229 for (auto cell
: mod
->cells())
231 if (design
->module(cell
->type
) == nullptr)
233 lhs
.selected_modules
.insert(cell
->type
);
239 static void select_op_cells_to_modules(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
241 RTLIL::Selection
new_sel(false);
242 for (auto mod
: design
->modules())
243 if (lhs
.selected_module(mod
->name
))
244 for (auto cell
: mod
->cells())
245 if (lhs
.selected_member(mod
->name
, cell
->name
) && (design
->module(cell
->type
) != nullptr))
246 new_sel
.selected_modules
.insert(cell
->type
);
250 static void select_op_module_to_cells(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
252 RTLIL::Selection
new_sel(false);
253 for (auto mod
: design
->modules())
254 for (auto cell
: mod
->cells())
255 if ((design
->module(cell
->type
) != nullptr) && lhs
.selected_whole_module(cell
->type
))
256 new_sel
.selected_members
[mod
->name
].insert(cell
->name
);
260 static void select_op_fullmod(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
262 lhs
.optimize(design
);
263 for (auto &it
: lhs
.selected_members
)
264 lhs
.selected_modules
.insert(it
.first
);
265 lhs
.selected_members
.clear();
268 static void select_op_alias(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
270 for (auto mod
: design
->modules())
272 if (lhs
.selected_whole_module(mod
->name
))
274 if (!lhs
.selected_module(mod
->name
))
278 SigPool selected_bits
;
280 for (auto wire
: mod
->wires())
281 if (lhs
.selected_member(mod
->name
, wire
->name
))
282 selected_bits
.add(sigmap(wire
));
284 for (auto wire
: mod
->wires())
285 if (!lhs
.selected_member(mod
->name
, wire
->name
) && selected_bits
.check_any(sigmap(wire
)))
286 lhs
.selected_members
[mod
->name
].insert(wire
->name
);
290 static void select_op_union(RTLIL::Design
*, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
292 if (rhs
.full_selection
) {
293 lhs
.full_selection
= true;
294 lhs
.selected_modules
.clear();
295 lhs
.selected_members
.clear();
299 if (lhs
.full_selection
)
302 for (auto &it
: rhs
.selected_members
)
303 for (auto &it2
: it
.second
)
304 lhs
.selected_members
[it
.first
].insert(it2
);
306 for (auto &it
: rhs
.selected_modules
) {
307 lhs
.selected_modules
.insert(it
);
308 lhs
.selected_members
.erase(it
);
312 static void select_op_diff(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
314 if (rhs
.full_selection
) {
315 lhs
.full_selection
= false;
316 lhs
.selected_modules
.clear();
317 lhs
.selected_members
.clear();
321 if (lhs
.full_selection
) {
322 if (!rhs
.full_selection
&& rhs
.selected_modules
.size() == 0 && rhs
.selected_members
.size() == 0)
324 lhs
.full_selection
= false;
325 for (auto mod
: design
->modules())
326 lhs
.selected_modules
.insert(mod
->name
);
329 for (auto &it
: rhs
.selected_modules
) {
330 lhs
.selected_modules
.erase(it
);
331 lhs
.selected_members
.erase(it
);
334 for (auto &it
: rhs
.selected_members
)
336 if (design
->module(it
.first
) == nullptr)
339 RTLIL::Module
*mod
= design
->module(it
.first
);
341 if (lhs
.selected_modules
.count(mod
->name
) > 0)
343 for (auto wire
: mod
->wires())
344 lhs
.selected_members
[mod
->name
].insert(wire
->name
);
345 for (auto &it
: mod
->memories
)
346 lhs
.selected_members
[mod
->name
].insert(it
.first
);
347 for (auto cell
: mod
->cells())
348 lhs
.selected_members
[mod
->name
].insert(cell
->name
);
349 for (auto &it
: mod
->processes
)
350 lhs
.selected_members
[mod
->name
].insert(it
.first
);
351 lhs
.selected_modules
.erase(mod
->name
);
354 if (lhs
.selected_members
.count(mod
->name
) == 0)
357 for (auto &it2
: it
.second
)
358 lhs
.selected_members
[mod
->name
].erase(it2
);
362 static void select_op_intersect(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
364 if (rhs
.full_selection
)
367 if (lhs
.full_selection
) {
368 lhs
.full_selection
= false;
369 for (auto mod
: design
->modules())
370 lhs
.selected_modules
.insert(mod
->name
);
373 std::vector
<RTLIL::IdString
> del_list
;
375 for (auto &it
: lhs
.selected_modules
)
376 if (rhs
.selected_modules
.count(it
) == 0) {
377 if (rhs
.selected_members
.count(it
) > 0)
378 for (auto &it2
: rhs
.selected_members
.at(it
))
379 lhs
.selected_members
[it
].insert(it2
);
380 del_list
.push_back(it
);
382 for (auto &it
: del_list
)
383 lhs
.selected_modules
.erase(it
);
386 for (auto &it
: lhs
.selected_members
) {
387 if (rhs
.selected_modules
.count(it
.first
) > 0)
389 if (rhs
.selected_members
.count(it
.first
) == 0) {
390 del_list
.push_back(it
.first
);
393 std::vector
<RTLIL::IdString
> del_list2
;
394 for (auto &it2
: it
.second
)
395 if (rhs
.selected_members
.at(it
.first
).count(it2
) == 0)
396 del_list2
.push_back(it2
);
397 for (auto &it2
: del_list2
)
398 it
.second
.erase(it2
);
399 if (it
.second
.size() == 0)
400 del_list
.push_back(it
.first
);
402 for (auto &it
: del_list
)
403 lhs
.selected_members
.erase(it
);
407 struct expand_rule_t
{
409 std::set
<RTLIL::IdString
> cell_types
, port_names
;
413 static int parse_comma_list(std::set
<RTLIL::IdString
> &tokens
, std::string str
, size_t pos
, std::string stopchar
)
417 size_t endpos
= str
.find_first_of(stopchar
, pos
);
418 if (endpos
== std::string::npos
)
421 tokens
.insert(RTLIL::escape_id(str
.substr(pos
, endpos
-pos
)));
423 if (pos
== str
.size() || str
[pos
] != ',')
429 static int select_op_expand(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, std::vector
<expand_rule_t
> &rules
, std::set
<RTLIL::IdString
> &limits
, int max_objects
, char mode
, CellTypes
&ct
, bool eval_only
)
432 bool is_input
, is_output
;
433 for (auto mod
: design
->modules())
435 if (lhs
.selected_whole_module(mod
->name
) || !lhs
.selected_module(mod
->name
))
438 std::set
<RTLIL::Wire
*> selected_wires
;
439 auto selected_members
= lhs
.selected_members
[mod
->name
];
441 for (auto wire
: mod
->wires())
442 if (lhs
.selected_member(mod
->name
, wire
->name
) && limits
.count(wire
->name
) == 0)
443 selected_wires
.insert(wire
);
445 for (auto &conn
: mod
->connections())
447 std::vector
<RTLIL::SigBit
> conn_lhs
= conn
.first
.to_sigbit_vector();
448 std::vector
<RTLIL::SigBit
> conn_rhs
= conn
.second
.to_sigbit_vector();
450 for (size_t i
= 0; i
< conn_lhs
.size(); i
++) {
451 if (conn_lhs
[i
].wire
== nullptr || conn_rhs
[i
].wire
== nullptr)
453 if (mode
!= 'i' && selected_wires
.count(conn_rhs
[i
].wire
) && selected_members
.count(conn_lhs
[i
].wire
->name
) == 0)
454 lhs
.selected_members
[mod
->name
].insert(conn_lhs
[i
].wire
->name
), sel_objects
++, max_objects
--;
455 if (mode
!= 'o' && selected_wires
.count(conn_lhs
[i
].wire
) && selected_members
.count(conn_rhs
[i
].wire
->name
) == 0)
456 lhs
.selected_members
[mod
->name
].insert(conn_rhs
[i
].wire
->name
), sel_objects
++, max_objects
--;
460 for (auto cell
: mod
->cells())
461 for (auto &conn
: cell
->connections())
463 char last_mode
= '-';
464 if (eval_only
&& !yosys_celltypes
.cell_evaluable(cell
->type
))
466 for (auto &rule
: rules
) {
467 last_mode
= rule
.mode
;
468 if (rule
.cell_types
.size() > 0 && rule
.cell_types
.count(cell
->type
) == 0)
470 if (rule
.port_names
.size() > 0 && rule
.port_names
.count(conn
.first
) == 0)
472 if (rule
.mode
== '+')
477 if (last_mode
== '+')
480 is_input
= mode
== 'x' || ct
.cell_input(cell
->type
, conn
.first
);
481 is_output
= mode
== 'x' || ct
.cell_output(cell
->type
, conn
.first
);
482 for (auto &chunk
: conn
.second
.chunks())
483 if (chunk
.wire
!= nullptr) {
484 if (max_objects
!= 0 && selected_wires
.count(chunk
.wire
) > 0 && selected_members
.count(cell
->name
) == 0)
485 if (mode
== 'x' || (mode
== 'i' && is_output
) || (mode
== 'o' && is_input
))
486 lhs
.selected_members
[mod
->name
].insert(cell
->name
), sel_objects
++, max_objects
--;
487 if (max_objects
!= 0 && selected_members
.count(cell
->name
) > 0 && limits
.count(cell
->name
) == 0 && selected_members
.count(chunk
.wire
->name
) == 0)
488 if (mode
== 'x' || (mode
== 'i' && is_input
) || (mode
== 'o' && is_output
))
489 lhs
.selected_members
[mod
->name
].insert(chunk
.wire
->name
), sel_objects
++, max_objects
--;
498 static void select_op_expand(RTLIL::Design
*design
, std::string arg
, char mode
, bool eval_only
)
500 int pos
= (mode
== 'x' ? 2 : 3) + (eval_only
? 1 : 0);
501 int levels
= 1, rem_objects
= -1;
502 std::vector
<expand_rule_t
> rules
;
503 std::set
<RTLIL::IdString
> limits
;
510 if (pos
< int(arg
.size()) && arg
[pos
] == '*') {
514 if (pos
< int(arg
.size()) && '0' <= arg
[pos
] && arg
[pos
] <= '9') {
515 size_t endpos
= arg
.find_first_not_of("0123456789", pos
);
516 if (endpos
== std::string::npos
)
518 levels
= atoi(arg
.substr(pos
, endpos
-pos
).c_str());
522 if (pos
< int(arg
.size()) && arg
[pos
] == '.') {
523 size_t endpos
= arg
.find_first_not_of("0123456789", ++pos
);
524 if (endpos
== std::string::npos
)
526 if (int(endpos
) > pos
)
527 rem_objects
= atoi(arg
.substr(pos
, endpos
-pos
).c_str());
531 while (pos
< int(arg
.size())) {
532 if (arg
[pos
] != ':' || pos
+1 == int(arg
.size()))
533 log_cmd_error("Syntax error in expand operator '%s'.\n", arg
.c_str());
535 if (arg
[pos
] == '+' || arg
[pos
] == '-') {
537 rule
.mode
= arg
[pos
++];
538 pos
= parse_comma_list(rule
.cell_types
, arg
, pos
, "[:");
539 if (pos
< int(arg
.size()) && arg
[pos
] == '[') {
540 pos
= parse_comma_list(rule
.port_names
, arg
, pos
+1, "]:");
541 if (pos
< int(arg
.size()) && arg
[pos
] == ']')
544 rules
.push_back(rule
);
546 size_t endpos
= arg
.find(':', pos
);
547 if (endpos
== std::string::npos
)
549 if (int(endpos
) > pos
) {
550 std::string str
= arg
.substr(pos
, endpos
-pos
);
552 str
= RTLIL::escape_id(str
.substr(1));
553 if (design
->selection_vars
.count(str
) > 0) {
554 for (auto i1
: design
->selection_vars
.at(str
).selected_members
)
555 for (auto i2
: i1
.second
)
558 log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str
).c_str());
560 limits
.insert(RTLIL::escape_id(str
));
567 log("expand by %d levels (max. %d objects):\n", levels
, rem_objects
);
568 for (auto &rule
: rules
) {
569 log(" rule (%c):\n", rule
.mode
);
570 if (rule
.cell_types
.size() > 0) {
572 for (auto &it
: rule
.cell_types
)
573 log(" %s", it
.c_str());
576 if (rule
.port_names
.size() > 0) {
578 for (auto &it
: rule
.port_names
)
579 log(" %s", it
.c_str());
583 if (limits
.size() > 0) {
585 for (auto &it
: limits
)
586 log(" %s", it
.c_str());
591 while (levels
-- > 0 && rem_objects
!= 0) {
592 int num_objects
= select_op_expand(design
, work_stack
.back(), rules
, limits
, rem_objects
, mode
, ct
, eval_only
);
593 if (num_objects
== 0)
595 rem_objects
-= num_objects
;
598 if (rem_objects
== 0)
599 log_warning("reached configured limit at `%s'.\n", arg
.c_str());
602 static void select_filter_active_mod(RTLIL::Design
*design
, RTLIL::Selection
&sel
)
604 if (design
->selected_active_module
.empty())
607 if (sel
.full_selection
) {
608 sel
.full_selection
= false;
609 sel
.selected_modules
.clear();
610 sel
.selected_members
.clear();
611 sel
.selected_modules
.insert(design
->selected_active_module
);
615 std::vector
<RTLIL::IdString
> del_list
;
616 for (auto mod_name
: sel
.selected_modules
)
617 if (mod_name
!= design
->selected_active_module
)
618 del_list
.push_back(mod_name
);
619 for (auto &it
: sel
.selected_members
)
620 if (it
.first
!= design
->selected_active_module
)
621 del_list
.push_back(it
.first
);
622 for (auto mod_name
: del_list
) {
623 sel
.selected_modules
.erase(mod_name
);
624 sel
.selected_members
.erase(mod_name
);
628 static void select_stmt(RTLIL::Design
*design
, std::string arg
, bool disable_empty_warning
= false)
630 std::string arg_mod
, arg_memb
;
631 std::unordered_map
<std::string
, bool> arg_mod_found
;
632 std::unordered_map
<std::string
, bool> arg_memb_found
;
633 auto isalpha
= [](const char &x
) { return ((x
>= 'a' && x
<= 'z') || (x
>= 'A' && x
<= 'Z')); };
634 bool prefixed
= GetSize(arg
) >= 2 && isalpha(arg
[0]) && arg
[1] == ':';
641 if (design
->selection_stack
.size() > 0)
642 work_stack
.push_back(design
->selection_stack
.back());
645 while (work_stack
.size() > 1) {
646 select_op_union(design
, work_stack
.front(), work_stack
.back());
647 work_stack
.pop_back();
651 if (work_stack
.size() < 1)
652 log_cmd_error("Must have at least one element on the stack for operator %%n.\n");
653 select_op_neg(design
, work_stack
[work_stack
.size()-1]);
656 if (work_stack
.size() < 2)
657 log_cmd_error("Must have at least two elements on the stack for operator %%u.\n");
658 select_op_union(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
659 work_stack
.pop_back();
662 if (work_stack
.size() < 2)
663 log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
664 select_op_diff(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
665 work_stack
.pop_back();
668 if (work_stack
.size() < 2)
669 log_cmd_error("Must have at least two elements on the stack for operator %%D.\n");
670 select_op_diff(design
, work_stack
[work_stack
.size()-1], work_stack
[work_stack
.size()-2]);
671 work_stack
[work_stack
.size()-2] = work_stack
[work_stack
.size()-1];
672 work_stack
.pop_back();
675 if (work_stack
.size() < 2)
676 log_cmd_error("Must have at least two elements on the stack for operator %%i.\n");
677 select_op_intersect(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
678 work_stack
.pop_back();
680 if (arg
.size() >= 2 && arg
[0] == '%' && arg
[1] == 'R') {
681 if (work_stack
.size() < 1)
682 log_cmd_error("Must have at least one element on the stack for operator %%R.\n");
683 int count
= arg
.size() > 2 ? atoi(arg
.c_str() + 2) : 1;
684 select_op_random(design
, work_stack
[work_stack
.size()-1], count
);
687 if (work_stack
.size() < 1)
688 log_cmd_error("Must have at least one element on the stack for operator %%s.\n");
689 select_op_submod(design
, work_stack
[work_stack
.size()-1]);
692 if (work_stack
.size() < 1)
693 log_cmd_error("Must have at least one element on the stack for operator %%M.\n");
694 select_op_cells_to_modules(design
, work_stack
[work_stack
.size()-1]);
697 if (work_stack
.size() < 1)
698 log_cmd_error("Must have at least one element on the stack for operator %%C.\n");
699 select_op_module_to_cells(design
, work_stack
[work_stack
.size()-1]);
702 if (work_stack
.size() < 1)
703 log_cmd_error("Must have at least one element on the stack for operator %%c.\n");
704 work_stack
.push_back(work_stack
.back());
707 if (work_stack
.size() < 1)
708 log_cmd_error("Must have at least one element on the stack for operator %%m.\n");
709 select_op_fullmod(design
, work_stack
[work_stack
.size()-1]);
712 if (work_stack
.size() < 1)
713 log_cmd_error("Must have at least one element on the stack for operator %%a.\n");
714 select_op_alias(design
, work_stack
[work_stack
.size()-1]);
716 if (arg
== "%x" || (arg
.size() > 2 && arg
.compare(0, 2, "%x") == 0 && (arg
[2] == ':' || arg
[2] == '*' || arg
[2] == '.' || ('0' <= arg
[2] && arg
[2] <= '9')))) {
717 if (work_stack
.size() < 1)
718 log_cmd_error("Must have at least one element on the stack for operator %%x.\n");
719 select_op_expand(design
, arg
, 'x', false);
721 if (arg
== "%ci" || (arg
.size() > 3 && arg
.compare(0, 3, "%ci") == 0 && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
722 if (work_stack
.size() < 1)
723 log_cmd_error("Must have at least one element on the stack for operator %%ci.\n");
724 select_op_expand(design
, arg
, 'i', false);
726 if (arg
== "%co" || (arg
.size() > 3 && arg
.compare(0, 3, "%co") == 0 && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
727 if (work_stack
.size() < 1)
728 log_cmd_error("Must have at least one element on the stack for operator %%co.\n");
729 select_op_expand(design
, arg
, 'o', false);
731 if (arg
== "%xe" || (arg
.size() > 3 && arg
.compare(0, 3, "%xe") == 0 && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
732 if (work_stack
.size() < 1)
733 log_cmd_error("Must have at least one element on the stack for operator %%xe.\n");
734 select_op_expand(design
, arg
, 'x', true);
736 if (arg
== "%cie" || (arg
.size() > 4 && arg
.compare(0, 4, "%cie") == 0 && (arg
[4] == ':' || arg
[4] == '*' || arg
[4] == '.' || ('0' <= arg
[4] && arg
[4] <= '9')))) {
737 if (work_stack
.size() < 1)
738 log_cmd_error("Must have at least one element on the stack for operator %%cie.\n");
739 select_op_expand(design
, arg
, 'i', true);
741 if (arg
== "%coe" || (arg
.size() > 4 && arg
.compare(0, 4, "%coe") == 0 && (arg
[4] == ':' || arg
[4] == '*' || arg
[4] == '.' || ('0' <= arg
[4] && arg
[4] <= '9')))) {
742 if (work_stack
.size() < 1)
743 log_cmd_error("Must have at least one element on the stack for operator %%coe.\n");
744 select_op_expand(design
, arg
, 'o', true);
746 log_cmd_error("Unknown selection operator '%s'.\n", arg
.c_str());
747 if (work_stack
.size() >= 1)
748 select_filter_active_mod(design
, work_stack
.back());
753 std::string set_name
= RTLIL::escape_id(arg
.substr(1));
754 if (design
->selection_vars
.count(set_name
) > 0)
755 work_stack
.push_back(design
->selection_vars
[set_name
]);
757 log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name
).c_str());
758 select_filter_active_mod(design
, work_stack
.back());
762 if (!design
->selected_active_module
.empty()) {
763 arg_mod
= design
->selected_active_module
;
765 if (!prefixed
) arg_memb_found
[arg_memb
] = false;
767 if (prefixed
&& arg
[0] >= 'a' && arg
[0] <= 'z') {
768 arg_mod
= "*", arg_memb
= arg
;
770 size_t pos
= arg
.find('/');
771 if (pos
== std::string::npos
) {
773 if (!prefixed
) arg_mod_found
[arg_mod
] = false;
775 arg_mod
= arg
.substr(0, pos
);
776 if (!prefixed
) arg_mod_found
[arg_mod
] = false;
777 arg_memb
= arg
.substr(pos
+1);
778 bool arg_memb_prefixed
= GetSize(arg_memb
) >= 2 && isalpha(arg_memb
[0]) && arg_memb
[1] == ':';
779 if (!arg_memb_prefixed
) arg_memb_found
[arg_memb
] = false;
783 work_stack
.push_back(RTLIL::Selection());
784 RTLIL::Selection
&sel
= work_stack
.back();
786 if (arg
== "*" && arg_mod
== "*") {
787 select_filter_active_mod(design
, work_stack
.back());
791 sel
.full_selection
= false;
792 for (auto mod
: design
->modules())
794 if (arg_mod
.compare(0, 2, "A:") == 0) {
795 if (!match_attr(mod
->attributes
, arg_mod
.substr(2)))
798 if (arg_mod
.compare(0, 2, "N:") == 0) {
799 if (!match_ids(mod
->name
, arg_mod
.substr(2)))
802 if (!match_ids(mod
->name
, arg_mod
))
805 arg_mod_found
[arg_mod
] = true;
807 if (arg_memb
== "") {
808 sel
.selected_modules
.insert(mod
->name
);
812 if (arg_memb
.compare(0, 2, "w:") == 0) {
813 for (auto wire
: mod
->wires())
814 if (match_ids(wire
->name
, arg_memb
.substr(2)))
815 sel
.selected_members
[mod
->name
].insert(wire
->name
);
817 if (arg_memb
.compare(0, 2, "i:") == 0) {
818 for (auto wire
: mod
->wires())
819 if (wire
->port_input
&& match_ids(wire
->name
, arg_memb
.substr(2)))
820 sel
.selected_members
[mod
->name
].insert(wire
->name
);
822 if (arg_memb
.compare(0, 2, "o:") == 0) {
823 for (auto wire
: mod
->wires())
824 if (wire
->port_output
&& match_ids(wire
->name
, arg_memb
.substr(2)))
825 sel
.selected_members
[mod
->name
].insert(wire
->name
);
827 if (arg_memb
.compare(0, 2, "x:") == 0) {
828 for (auto wire
: mod
->wires())
829 if ((wire
->port_input
|| wire
->port_output
) && match_ids(wire
->name
, arg_memb
.substr(2)))
830 sel
.selected_members
[mod
->name
].insert(wire
->name
);
832 if (arg_memb
.compare(0, 2, "s:") == 0) {
833 size_t delim
= arg_memb
.substr(2).find(':');
834 if (delim
== std::string::npos
) {
835 int width
= atoi(arg_memb
.substr(2).c_str());
836 for (auto wire
: mod
->wires())
837 if (wire
->width
== width
)
838 sel
.selected_members
[mod
->name
].insert(wire
->name
);
840 std::string min_str
= arg_memb
.substr(2, delim
);
841 std::string max_str
= arg_memb
.substr(2+delim
+1);
842 int min_width
= min_str
.empty() ? 0 : atoi(min_str
.c_str());
843 int max_width
= max_str
.empty() ? -1 : atoi(max_str
.c_str());
844 for (auto wire
: mod
->wires())
845 if (min_width
<= wire
->width
&& (wire
->width
<= max_width
|| max_width
== -1))
846 sel
.selected_members
[mod
->name
].insert(wire
->name
);
849 if (arg_memb
.compare(0, 2, "m:") == 0) {
850 for (auto &it
: mod
->memories
)
851 if (match_ids(it
.first
, arg_memb
.substr(2)))
852 sel
.selected_members
[mod
->name
].insert(it
.first
);
854 if (arg_memb
.compare(0, 2, "c:") == 0) {
855 for (auto cell
: mod
->cells())
856 if (match_ids(cell
->name
, arg_memb
.substr(2)))
857 sel
.selected_members
[mod
->name
].insert(cell
->name
);
859 if (arg_memb
.compare(0, 2, "t:") == 0) {
860 for (auto cell
: mod
->cells())
861 if (match_ids(cell
->type
, arg_memb
.substr(2)))
862 sel
.selected_members
[mod
->name
].insert(cell
->name
);
864 if (arg_memb
.compare(0, 2, "p:") == 0) {
865 for (auto &it
: mod
->processes
)
866 if (match_ids(it
.first
, arg_memb
.substr(2)))
867 sel
.selected_members
[mod
->name
].insert(it
.first
);
869 if (arg_memb
.compare(0, 2, "a:") == 0) {
870 for (auto wire
: mod
->wires())
871 if (match_attr(wire
->attributes
, arg_memb
.substr(2)))
872 sel
.selected_members
[mod
->name
].insert(wire
->name
);
873 for (auto &it
: mod
->memories
)
874 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
875 sel
.selected_members
[mod
->name
].insert(it
.first
);
876 for (auto cell
: mod
->cells())
877 if (match_attr(cell
->attributes
, arg_memb
.substr(2)))
878 sel
.selected_members
[mod
->name
].insert(cell
->name
);
879 for (auto &it
: mod
->processes
)
880 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
881 sel
.selected_members
[mod
->name
].insert(it
.first
);
883 if (arg_memb
.compare(0, 2, "r:") == 0) {
884 for (auto cell
: mod
->cells())
885 if (match_attr(cell
->parameters
, arg_memb
.substr(2)))
886 sel
.selected_members
[mod
->name
].insert(cell
->name
);
888 std::string orig_arg_memb
= arg_memb
;
889 if (arg_memb
.compare(0, 2, "n:") == 0)
890 arg_memb
= arg_memb
.substr(2);
891 for (auto wire
: mod
->wires())
892 if (match_ids(wire
->name
, arg_memb
)) {
893 sel
.selected_members
[mod
->name
].insert(wire
->name
);
894 arg_memb_found
[orig_arg_memb
] = true;
896 for (auto &it
: mod
->memories
)
897 if (match_ids(it
.first
, arg_memb
)) {
898 sel
.selected_members
[mod
->name
].insert(it
.first
);
899 arg_memb_found
[orig_arg_memb
] = true;
901 for (auto cell
: mod
->cells())
902 if (match_ids(cell
->name
, arg_memb
)) {
903 sel
.selected_members
[mod
->name
].insert(cell
->name
);
904 arg_memb_found
[orig_arg_memb
] = true;
906 for (auto &it
: mod
->processes
)
907 if (match_ids(it
.first
, arg_memb
)) {
908 sel
.selected_members
[mod
->name
].insert(it
.first
);
909 arg_memb_found
[orig_arg_memb
] = true;
914 select_filter_active_mod(design
, work_stack
.back());
916 for (auto &it
: arg_mod_found
) {
917 if (it
.second
== false && !disable_empty_warning
) {
918 log_warning("Selection \"%s\" did not match any module.\n", it
.first
.c_str());
921 for (auto &it
: arg_memb_found
) {
922 if (it
.second
== false && !disable_empty_warning
) {
923 log_warning("Selection \"%s\" did not match any object.\n", it
.first
.c_str());
928 static std::string
describe_selection_for_assert(RTLIL::Design
*design
, RTLIL::Selection
*sel
)
930 std::string desc
= "Selection contains:\n";
931 for (auto mod
: design
->modules())
933 if (sel
->selected_module(mod
->name
)) {
934 for (auto wire
: mod
->wires())
935 if (sel
->selected_member(mod
->name
, wire
->name
))
936 desc
+= stringf("%s/%s\n", id2cstr(mod
->name
), id2cstr(wire
->name
));
937 for (auto &it
: mod
->memories
)
938 if (sel
->selected_member(mod
->name
, it
.first
))
939 desc
+= stringf("%s/%s\n", id2cstr(mod
->name
), id2cstr(it
.first
));
940 for (auto cell
: mod
->cells())
941 if (sel
->selected_member(mod
->name
, cell
->name
))
942 desc
+= stringf("%s/%s\n", id2cstr(mod
->name
), id2cstr(cell
->name
));
943 for (auto &it
: mod
->processes
)
944 if (sel
->selected_member(mod
->name
, it
.first
))
945 desc
+= stringf("%s/%s\n", id2cstr(mod
->name
), id2cstr(it
.first
));
951 PRIVATE_NAMESPACE_END
952 YOSYS_NAMESPACE_BEGIN
954 // used in kernel/register.cc and maybe other locations, extern decl. in register.h
955 void handle_extra_select_args(Pass
*pass
, vector
<string
> args
, size_t argidx
, size_t args_size
, RTLIL::Design
*design
)
958 for (; argidx
< args_size
; argidx
++) {
959 if (args
[argidx
].compare(0, 1, "-") == 0) {
961 pass
->cmd_error(args
, argidx
, "Unexpected option in selection arguments.");
963 log_cmd_error("Unexpected option in selection arguments.");
965 select_stmt(design
, args
[argidx
]);
967 while (work_stack
.size() > 1) {
968 select_op_union(design
, work_stack
.front(), work_stack
.back());
969 work_stack
.pop_back();
971 if (work_stack
.empty())
972 design
->selection_stack
.push_back(RTLIL::Selection(false));
974 design
->selection_stack
.push_back(work_stack
.back());
977 // extern decl. in register.h
978 RTLIL::Selection
eval_select_args(const vector
<string
> &args
, RTLIL::Design
*design
)
981 for (auto &arg
: args
)
982 select_stmt(design
, arg
);
983 while (work_stack
.size() > 1) {
984 select_op_union(design
, work_stack
.front(), work_stack
.back());
985 work_stack
.pop_back();
987 if (work_stack
.empty())
988 return RTLIL::Selection(false);
989 return work_stack
.back();
992 // extern decl. in register.h
993 void eval_select_op(vector
<RTLIL::Selection
> &work
, const string
&op
, RTLIL::Design
*design
)
995 work_stack
.swap(work
);
996 select_stmt(design
, op
);
997 work_stack
.swap(work
);
1001 PRIVATE_NAMESPACE_BEGIN
1003 struct SelectPass
: public Pass
{
1004 SelectPass() : Pass("select", "modify and view the list of selected objects") { }
1005 void help() YS_OVERRIDE
1007 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1009 log(" select [ -add | -del | -set <name> ] {-read <filename> | <selection>}\n");
1010 log(" select [ <assert_option> ] {-read <filename> | <selection>}\n");
1011 log(" select [ -list | -write <filename> | -count | -clear ]\n");
1012 log(" select -module <modname>\n");
1014 log("Most commands use the list of currently selected objects to determine which part\n");
1015 log("of the design to operate on. This command can be used to modify and view this\n");
1016 log("list of selected objects.\n");
1018 log("Note that many commands support an optional [selection] argument that can be\n");
1019 log("used to override the global selection for the command. The syntax of this\n");
1020 log("optional argument is identical to the syntax of the <selection> argument\n");
1021 log("described here.\n");
1023 log(" -add, -del\n");
1024 log(" add or remove the given objects to the current selection.\n");
1025 log(" without this options the current selection is replaced.\n");
1027 log(" -set <name>\n");
1028 log(" do not modify the current selection. instead save the new selection\n");
1029 log(" under the given name (see @<name> below). to save the current selection,\n");
1030 log(" use \"select -set <name> %%\"\n");
1032 log(" -assert-none\n");
1033 log(" do not modify the current selection. instead assert that the given\n");
1034 log(" selection is empty. i.e. produce an error if any object matching the\n");
1035 log(" selection is found.\n");
1037 log(" -assert-any\n");
1038 log(" do not modify the current selection. instead assert that the given\n");
1039 log(" selection is non-empty. i.e. produce an error if no object matching\n");
1040 log(" the selection is found.\n");
1042 log(" -assert-count N\n");
1043 log(" do not modify the current selection. instead assert that the given\n");
1044 log(" selection contains exactly N objects.\n");
1046 log(" -assert-max N\n");
1047 log(" do not modify the current selection. instead assert that the given\n");
1048 log(" selection contains less than or exactly N objects.\n");
1050 log(" -assert-min N\n");
1051 log(" do not modify the current selection. instead assert that the given\n");
1052 log(" selection contains at least N objects.\n");
1055 log(" list all objects in the current selection\n");
1057 log(" -write <filename>\n");
1058 log(" like -list but write the output to the specified file\n");
1060 log(" -read <filename>\n");
1061 log(" read the specified file (written by -write)\n");
1064 log(" count all objects in the current selection\n");
1067 log(" clear the current selection. this effectively selects the whole\n");
1068 log(" design. it also resets the selected module (see -module). use the\n");
1069 log(" command 'select *' to select everything but stay in the current module.\n");
1072 log(" create an empty selection. the current module is unchanged.\n");
1074 log(" -module <modname>\n");
1075 log(" limit the current scope to the specified module.\n");
1076 log(" the difference between this and simply selecting the module\n");
1077 log(" is that all object names are interpreted relative to this\n");
1078 log(" module after this command until the selection is cleared again.\n");
1080 log("When this command is called without an argument, the current selection\n");
1081 log("is displayed in a compact form (i.e. only the module name when a whole module\n");
1082 log("is selected).\n");
1084 log("The <selection> argument itself is a series of commands for a simple stack\n");
1085 log("machine. Each element on the stack represents a set of selected objects.\n");
1086 log("After this commands have been executed, the union of all remaining sets\n");
1087 log("on the stack is computed and used as selection for the command.\n");
1089 log("Pushing (selecting) object when not in -module mode:\n");
1091 log(" <mod_pattern>\n");
1092 log(" select the specified module(s)\n");
1094 log(" <mod_pattern>/<obj_pattern>\n");
1095 log(" select the specified object(s) from the module(s)\n");
1097 log("Pushing (selecting) object when in -module mode:\n");
1099 log(" <obj_pattern>\n");
1100 log(" select the specified object(s) from the current module\n");
1102 log("A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])\n");
1103 log("matching module names, or one of the following:\n");
1105 log(" A:<pattern>, A:<pattern>=<pattern>\n");
1106 log(" all modules with an attribute matching the given pattern\n");
1107 log(" in addition to = also <, <=, >=, and > are supported\n");
1109 log(" N:<pattern>\n");
1110 log(" all modules with a name matching the given pattern\n");
1111 log(" (i.e. 'N:' is optional as it is the default matching rule)\n");
1113 log("An <obj_pattern> can be an object name, wildcard expression, or one of\n");
1114 log("the following:\n");
1116 log(" w:<pattern>\n");
1117 log(" all wires with a name matching the given wildcard pattern\n");
1119 log(" i:<pattern>, o:<pattern>, x:<pattern>\n");
1120 log(" all inputs (i:), outputs (o:) or any ports (x:) with matching names\n");
1122 log(" s:<size>, s:<min>:<max>\n");
1123 log(" all wires with a matching width\n");
1125 log(" m:<pattern>\n");
1126 log(" all memories with a name matching the given pattern\n");
1128 log(" c:<pattern>\n");
1129 log(" all cells with a name matching the given pattern\n");
1131 log(" t:<pattern>\n");
1132 log(" all cells with a type matching the given pattern\n");
1134 log(" p:<pattern>\n");
1135 log(" all processes with a name matching the given pattern\n");
1137 log(" a:<pattern>\n");
1138 log(" all objects with an attribute name matching the given pattern\n");
1140 log(" a:<pattern>=<pattern>\n");
1141 log(" all objects with a matching attribute name-value-pair.\n");
1142 log(" in addition to = also <, <=, >=, and > are supported\n");
1144 log(" r:<pattern>, r:<pattern>=<pattern>\n");
1145 log(" cells with matching parameters. also with <, <=, >= and >.\n");
1147 log(" n:<pattern>\n");
1148 log(" all objects with a name matching the given pattern\n");
1149 log(" (i.e. 'n:' is optional as it is the default matching rule)\n");
1152 log(" push the selection saved prior with 'select -set <name> ...'\n");
1154 log("The following actions can be performed on the top sets on the stack:\n");
1157 log(" push a copy of the current selection to the stack\n");
1160 log(" replace the stack with a union of all elements on it\n");
1163 log(" replace top set with its invert\n");
1166 log(" replace the two top sets on the stack with their union\n");
1169 log(" replace the two top sets on the stack with their intersection\n");
1172 log(" pop the top set from the stack and subtract it from the new top\n");
1175 log(" like %%d but swap the roles of two top sets on the stack\n");
1178 log(" create a copy of the top set from the stack and push it\n");
1180 log(" %%x[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
1181 log(" expand top set <num1> num times according to the specified rules.\n");
1182 log(" (i.e. select all cells connected to selected wires and select all\n");
1183 log(" wires connected to selected cells) The rules specify which cell\n");
1184 log(" ports to use for this. the syntax for a rule is a '-' for exclusion\n");
1185 log(" and a '+' for inclusion, followed by an optional comma separated\n");
1186 log(" list of cell types followed by an optional comma separated list of\n");
1187 log(" cell ports in square brackets. a rule can also be just a cell or wire\n");
1188 log(" name that limits the expansion (is included but does not go beyond).\n");
1189 log(" select at most <num2> objects. a warning message is printed when this\n");
1190 log(" limit is reached. When '*' is used instead of <num1> then the process\n");
1191 log(" is repeated until no further object are selected.\n");
1193 log(" %%ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
1194 log(" %%co[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
1195 log(" similar to %%x, but only select input (%%ci) or output cones (%%co)\n");
1197 log(" %%xe[...] %%cie[...] %%coe\n");
1198 log(" like %%x, %%ci, and %%co but only consider combinatorial cells\n");
1201 log(" expand top set by selecting all wires that are (at least in part)\n");
1202 log(" aliases for selected wires.\n");
1205 log(" expand top set by adding all modules that implement cells in selected\n");
1209 log(" expand top set by selecting all modules that contain selected objects\n");
1212 log(" select modules that implement selected cells\n");
1215 log(" select cells that implement selected modules\n");
1217 log(" %%R[<num>]\n");
1218 log(" select <num> random objects from top selection (default 1)\n");
1220 log("Example: the following command selects all wires that are connected to a\n");
1221 log("'GATE' input of a 'SWITCH' cell:\n");
1223 log(" select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n");
1226 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1228 bool add_mode
= false;
1229 bool del_mode
= false;
1230 bool clear_mode
= false;
1231 bool none_mode
= false;
1232 bool list_mode
= false;
1233 bool count_mode
= false;
1234 bool got_module
= false;
1235 bool assert_none
= false;
1236 bool assert_any
= false;
1237 int assert_count
= -1;
1238 int assert_max
= -1;
1239 int assert_min
= -1;
1240 std::string write_file
, read_file
;
1241 std::string set_name
, sel_str
;
1246 for (argidx
= 1; argidx
< args
.size(); argidx
++)
1248 std::string arg
= args
[argidx
];
1249 if (arg
== "-add") {
1253 if (arg
== "-del") {
1257 if (arg
== "-assert-none") {
1261 if (arg
== "-assert-any") {
1265 if (arg
== "-assert-count" && argidx
+1 < args
.size()) {
1266 assert_count
= atoi(args
[++argidx
].c_str());
1269 if (arg
== "-assert-max" && argidx
+1 < args
.size()) {
1270 assert_max
= atoi(args
[++argidx
].c_str());
1273 if (arg
== "-assert-min" && argidx
+1 < args
.size()) {
1274 assert_min
= atoi(args
[++argidx
].c_str());
1277 if (arg
== "-clear") {
1281 if (arg
== "-none") {
1285 if (arg
== "-list") {
1289 if (arg
== "-write" && argidx
+1 < args
.size()) {
1290 write_file
= args
[++argidx
];
1293 if (arg
== "-read" && argidx
+1 < args
.size()) {
1294 read_file
= args
[++argidx
];
1297 if (arg
== "-count") {
1301 if (arg
== "-module" && argidx
+1 < args
.size()) {
1302 RTLIL::IdString mod_name
= RTLIL::escape_id(args
[++argidx
]);
1303 if (design
->module(mod_name
) == nullptr)
1304 log_cmd_error("No such module: %s\n", id2cstr(mod_name
));
1305 design
->selected_active_module
= mod_name
.str();
1309 if (arg
== "-set" && argidx
+1 < args
.size()) {
1310 set_name
= RTLIL::escape_id(args
[++argidx
]);
1313 if (arg
.size() > 0 && arg
[0] == '-')
1314 log_cmd_error("Unknown option %s.\n", arg
.c_str());
1315 bool disable_empty_warning
= count_mode
|| assert_none
|| assert_any
|| (assert_count
!= -1) || (assert_max
!= -1) || (assert_min
!= -1);
1316 select_stmt(design
, arg
, disable_empty_warning
);
1317 sel_str
+= " " + arg
;
1320 if (!read_file
.empty())
1322 if (!sel_str
.empty())
1323 log_cmd_error("Option -read can not be combined with a selection expression.\n");
1325 std::ifstream
f(read_file
);
1326 yosys_input_files
.insert(read_file
);
1328 log_error("Can't open '%s' for reading: %s\n", read_file
.c_str(), strerror(errno
));
1330 RTLIL::Selection
sel(false);
1333 while (std::getline(f
, line
)) {
1334 size_t slash_pos
= line
.find('/');
1335 if (slash_pos
== string::npos
) {
1336 log_warning("Ignoring line without slash in 'select -read': %s\n", line
.c_str());
1339 IdString mod_name
= RTLIL::escape_id(line
.substr(0, slash_pos
));
1340 IdString obj_name
= RTLIL::escape_id(line
.substr(slash_pos
+1));
1341 sel
.selected_members
[mod_name
].insert(obj_name
);
1344 select_filter_active_mod(design
, sel
);
1345 sel
.optimize(design
);
1346 work_stack
.push_back(sel
);
1349 if (clear_mode
&& args
.size() != 2)
1350 log_cmd_error("Option -clear can not be combined with any other options.\n");
1352 if (none_mode
&& args
.size() != 2)
1353 log_cmd_error("Option -none can not be combined with any other options.\n");
1355 if (add_mode
+ del_mode
+ assert_none
+ assert_any
+ (assert_count
>= 0) + (assert_max
>= 0) + (assert_min
>= 0) > 1)
1356 log_cmd_error("Options -add, -del, -assert-none, -assert-any, assert-count, -assert-max or -assert-min can not be combined.\n");
1358 if ((list_mode
|| !write_file
.empty() || count_mode
) && (add_mode
|| del_mode
|| assert_none
|| assert_any
|| assert_count
>= 0 || assert_max
>= 0 || assert_min
>= 0))
1359 log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none, -assert-any, assert-count, -assert-max, or -assert-min.\n");
1361 if (!set_name
.empty() && (list_mode
|| !write_file
.empty() || count_mode
|| add_mode
|| del_mode
|| assert_none
|| assert_any
|| assert_count
>= 0 || assert_max
>= 0 || assert_min
>= 0))
1362 log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
1364 if (work_stack
.size() == 0 && got_module
) {
1365 RTLIL::Selection sel
;
1366 select_filter_active_mod(design
, sel
);
1367 work_stack
.push_back(sel
);
1370 while (work_stack
.size() > 1) {
1371 select_op_union(design
, work_stack
.front(), work_stack
.back());
1372 work_stack
.pop_back();
1375 log_assert(design
->selection_stack
.size() > 0);
1378 design
->selection_stack
.back() = RTLIL::Selection(true);
1379 design
->selected_active_module
= std::string();
1384 design
->selection_stack
.back() = RTLIL::Selection(false);
1388 if (list_mode
|| count_mode
|| !write_file
.empty())
1390 #define LOG_OBJECT(...) { if (list_mode) log(__VA_ARGS__); if (f != nullptr) fprintf(f, __VA_ARGS__); total_count++; }
1391 int total_count
= 0;
1393 if (!write_file
.empty()) {
1394 f
= fopen(write_file
.c_str(), "w");
1395 yosys_output_files
.insert(write_file
);
1397 log_error("Can't open '%s' for writing: %s\n", write_file
.c_str(), strerror(errno
));
1399 RTLIL::Selection
*sel
= &design
->selection_stack
.back();
1400 if (work_stack
.size() > 0)
1401 sel
= &work_stack
.back();
1402 sel
->optimize(design
);
1403 for (auto mod
: design
->modules())
1405 if (sel
->selected_whole_module(mod
->name
) && list_mode
)
1406 log("%s\n", id2cstr(mod
->name
));
1407 if (sel
->selected_module(mod
->name
)) {
1408 for (auto wire
: mod
->wires())
1409 if (sel
->selected_member(mod
->name
, wire
->name
))
1410 LOG_OBJECT("%s/%s\n", id2cstr(mod
->name
), id2cstr(wire
->name
))
1411 for (auto &it
: mod
->memories
)
1412 if (sel
->selected_member(mod
->name
, it
.first
))
1413 LOG_OBJECT("%s/%s\n", id2cstr(mod
->name
), id2cstr(it
.first
))
1414 for (auto cell
: mod
->cells())
1415 if (sel
->selected_member(mod
->name
, cell
->name
))
1416 LOG_OBJECT("%s/%s\n", id2cstr(mod
->name
), id2cstr(cell
->name
))
1417 for (auto &it
: mod
->processes
)
1418 if (sel
->selected_member(mod
->name
, it
.first
))
1419 LOG_OBJECT("%s/%s\n", id2cstr(mod
->name
), id2cstr(it
.first
))
1423 log("%d objects.\n", total_count
);
1432 if (work_stack
.size() == 0)
1433 log_cmd_error("Nothing to add to selection.\n");
1434 select_op_union(design
, design
->selection_stack
.back(), work_stack
.back());
1435 design
->selection_stack
.back().optimize(design
);
1441 if (work_stack
.size() == 0)
1442 log_cmd_error("Nothing to delete from selection.\n");
1443 select_op_diff(design
, design
->selection_stack
.back(), work_stack
.back());
1444 design
->selection_stack
.back().optimize(design
);
1450 if (work_stack
.size() == 0)
1451 log_cmd_error("No selection to check.\n");
1452 work_stack
.back().optimize(design
);
1453 if (!work_stack
.back().empty())
1455 RTLIL::Selection
*sel
= &work_stack
.back();
1456 sel
->optimize(design
);
1457 std::string desc
= describe_selection_for_assert(design
, sel
);
1458 log_error("Assertion failed: selection is not empty:%s\n%s", sel_str
.c_str(), desc
.c_str());
1465 if (work_stack
.size() == 0)
1466 log_cmd_error("No selection to check.\n");
1467 work_stack
.back().optimize(design
);
1468 if (work_stack
.back().empty())
1470 RTLIL::Selection
*sel
= &work_stack
.back();
1471 sel
->optimize(design
);
1472 std::string desc
= describe_selection_for_assert(design
, sel
);
1473 log_error("Assertion failed: selection is empty:%s\n%s", sel_str
.c_str(), desc
.c_str());
1478 if (assert_count
>= 0 || assert_max
>= 0 || assert_min
>= 0)
1480 int total_count
= 0;
1481 if (work_stack
.size() == 0)
1482 log_cmd_error("No selection to check.\n");
1483 RTLIL::Selection
*sel
= &work_stack
.back();
1484 sel
->optimize(design
);
1485 for (auto mod
: design
->modules())
1486 if (sel
->selected_module(mod
->name
)) {
1487 for (auto wire
: mod
->wires())
1488 if (sel
->selected_member(mod
->name
, wire
->name
))
1490 for (auto &it
: mod
->memories
)
1491 if (sel
->selected_member(mod
->name
, it
.first
))
1493 for (auto cell
: mod
->cells())
1494 if (sel
->selected_member(mod
->name
, cell
->name
))
1496 for (auto &it
: mod
->processes
)
1497 if (sel
->selected_member(mod
->name
, it
.first
))
1500 if (assert_count
>= 0 && assert_count
!= total_count
)
1502 std::string desc
= describe_selection_for_assert(design
, sel
);
1503 log_error("Assertion failed: selection contains %d elements instead of the asserted %d:%s\n%s",
1504 total_count
, assert_count
, sel_str
.c_str(), desc
.c_str());
1506 if (assert_max
>= 0 && assert_max
< total_count
)
1508 std::string desc
= describe_selection_for_assert(design
, sel
);
1509 log_error("Assertion failed: selection contains %d elements, more than the maximum number %d:%s\n%s",
1510 total_count
, assert_max
, sel_str
.c_str(), desc
.c_str());
1512 if (assert_min
>= 0 && assert_min
> total_count
)
1514 std::string desc
= describe_selection_for_assert(design
, sel
);
1515 log_error("Assertion failed: selection contains %d elements, less than the minimum number %d:%s\n%s",
1516 total_count
, assert_min
, sel_str
.c_str(), desc
.c_str());
1521 if (!set_name
.empty())
1523 if (work_stack
.size() == 0)
1524 design
->selection_vars
[set_name
] = RTLIL::Selection(false);
1526 design
->selection_vars
[set_name
] = work_stack
.back();
1530 if (work_stack
.size() == 0) {
1531 RTLIL::Selection
&sel
= design
->selection_stack
.back();
1532 if (sel
.full_selection
)
1534 for (auto &it
: sel
.selected_modules
)
1535 log("%s\n", id2cstr(it
));
1536 for (auto &it
: sel
.selected_members
)
1537 for (auto &it2
: it
.second
)
1538 log("%s/%s\n", id2cstr(it
.first
), id2cstr(it2
));
1542 design
->selection_stack
.back() = work_stack
.back();
1543 design
->selection_stack
.back().optimize(design
);
1547 struct CdPass
: public Pass
{
1548 CdPass() : Pass("cd", "a shortcut for 'select -module <name>'") { }
1549 void help() YS_OVERRIDE
1551 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1553 log(" cd <modname>\n");
1555 log("This is just a shortcut for 'select -module <modname>'.\n");
1558 log(" cd <cellname>\n");
1560 log("When no module with the specified name is found, but there is a cell\n");
1561 log("with the specified name in the current module, then this is equivalent\n");
1562 log("to 'cd <celltype>'.\n");
1566 log("Remove trailing substrings that start with '.' in current module name until\n");
1567 log("the name of a module in the current design is generated, then switch to that\n");
1568 log("module. Otherwise clear the current selection.\n");
1572 log("This is just a shortcut for 'select -clear'.\n");
1575 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1577 if (args
.size() != 1 && args
.size() != 2)
1578 log_cmd_error("Invalid number of arguments.\n");
1580 if (args
.size() == 1 || args
[1] == "/") {
1581 design
->selection_stack
.back() = RTLIL::Selection(true);
1582 design
->selected_active_module
= std::string();
1586 if (args
[1] == "..")
1588 string modname
= design
->selected_active_module
;
1590 design
->selection_stack
.back() = RTLIL::Selection(true);
1591 design
->selected_active_module
= std::string();
1595 size_t pos
= modname
.rfind('.');
1597 if (pos
== string::npos
)
1600 modname
= modname
.substr(0, pos
);
1601 Module
*mod
= design
->module(modname
);
1606 design
->selected_active_module
= modname
;
1607 design
->selection_stack
.back() = RTLIL::Selection();
1608 select_filter_active_mod(design
, design
->selection_stack
.back());
1609 design
->selection_stack
.back().optimize(design
);
1616 std::string modname
= RTLIL::escape_id(args
[1]);
1618 if (design
->module(modname
) == nullptr && !design
->selected_active_module
.empty()) {
1619 RTLIL::Module
*module
= design
->module(design
->selected_active_module
);
1620 if (module
!= nullptr && module
->cell(modname
) != nullptr)
1621 modname
= module
->cell(modname
)->type
.str();
1624 if (design
->module(modname
) != nullptr) {
1625 design
->selected_active_module
= modname
;
1626 design
->selection_stack
.back() = RTLIL::Selection();
1627 select_filter_active_mod(design
, design
->selection_stack
.back());
1628 design
->selection_stack
.back().optimize(design
);
1632 log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname
).c_str());
1636 template<typename T
>
1637 static void log_matches(const char *title
, Module
*module
, T list
)
1639 std::vector
<IdString
> matches
;
1641 for (auto &it
: list
)
1642 if (module
->selected(it
.second
))
1643 matches
.push_back(it
.first
);
1645 if (!matches
.empty()) {
1646 log("\n%d %s:\n", int(matches
.size()), title
);
1647 std::sort(matches
.begin(), matches
.end(), RTLIL::sort_by_id_str());
1648 for (auto id
: matches
)
1649 log(" %s\n", RTLIL::id2cstr(id
));
1653 struct LsPass
: public Pass
{
1654 LsPass() : Pass("ls", "list modules or objects in modules") { }
1655 void help() YS_OVERRIDE
1657 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1659 log(" ls [selection]\n");
1661 log("When no active module is selected, this prints a list of modules.\n");
1663 log("When an active module is selected, this prints a list of objects in the module.\n");
1666 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1669 extra_args(args
, argidx
, design
);
1671 if (design
->selected_active_module
.empty())
1673 std::vector
<IdString
> matches
;
1675 for (auto mod
: design
->selected_modules())
1676 matches
.push_back(mod
->name
);
1678 if (!matches
.empty()) {
1679 log("\n%d %s:\n", int(matches
.size()), "modules");
1680 std::sort(matches
.begin(), matches
.end(), RTLIL::sort_by_id_str());
1681 for (auto id
: matches
)
1682 log(" %s%s\n", log_id(id
), design
->selected_whole_module(design
->module(id
)) ? "" : "*");
1686 if (design
->module(design
->selected_active_module
) != nullptr)
1688 RTLIL::Module
*module
= design
->module(design
->selected_active_module
);
1689 log_matches("wires", module
, module
->wires_
);
1690 log_matches("memories", module
, module
->memories
);
1691 log_matches("cells", module
, module
->cells_
);
1692 log_matches("processes", module
, module
->processes
);
1697 PRIVATE_NAMESPACE_END