2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/log.h"
30 static std::vector
<RTLIL::Selection
> work_stack
;
32 static bool match_ids(RTLIL::IdString id
, std::string pattern
)
36 if (id
.size() > 0 && id
[0] == '\\' && id
.substr(1) == pattern
)
38 if (!fnmatch(pattern
.c_str(), id
.c_str(), 0))
40 if (id
.size() > 0 && id
[0] == '\\' && !fnmatch(pattern
.c_str(), id
.substr(1).c_str(), 0))
42 if (id
.size() > 0 && id
[0] == '$' && pattern
.size() > 0 && pattern
[0] == '$') {
43 const char *p
= id
.c_str();
44 const char *q
= strrchr(p
, '$');
51 static bool match_attr_val(const RTLIL::Const
&value
, std::string pattern
, char match_op
)
56 if ((value
.flags
& RTLIL::CONST_FLAG_STRING
) == 0)
58 RTLIL::SigSpec sig_value
;
60 if (!RTLIL::SigSpec::parse(sig_value
, NULL
, pattern
))
63 RTLIL::Const pattern_value
= sig_value
.as_const();
66 return value
== pattern_value
;
68 return value
!= pattern_value
;
70 return value
.as_int() < pattern_value
.as_int();
72 return value
.as_int() > pattern_value
.as_int();
74 return value
.as_int() <= pattern_value
.as_int();
76 return value
.as_int() >= pattern_value
.as_int();
80 std::string value_str
= value
.decode_string();
83 if (!fnmatch(pattern
.c_str(), value
.decode_string().c_str(), FNM_NOESCAPE
))
87 return value_str
== pattern
;
89 return value_str
!= pattern
;
91 return value_str
< pattern
;
93 return value_str
> pattern
;
95 return value_str
<= pattern
;
97 return value_str
>= pattern
;
103 static bool match_attr(const std::map
<RTLIL::IdString
, RTLIL::Const
> &attributes
, std::string name_pat
, std::string value_pat
, char match_op
)
105 if (name_pat
.find('*') != std::string::npos
|| name_pat
.find('?') != std::string::npos
|| name_pat
.find('[') != std::string::npos
) {
106 for (auto &it
: attributes
) {
107 if (!fnmatch(name_pat
.c_str(), it
.first
.c_str(), FNM_NOESCAPE
) && match_attr_val(it
.second
, value_pat
, match_op
))
109 if (it
.first
.size() > 0 && it
.first
[0] == '\\' && !fnmatch(name_pat
.c_str(), it
.first
.substr(1).c_str(), FNM_NOESCAPE
) && match_attr_val(it
.second
, value_pat
, match_op
))
113 if (name_pat
.size() > 0 && (name_pat
[0] == '\\' || name_pat
[0] == '$') && attributes
.count(name_pat
) && match_attr_val(attributes
.at(name_pat
), value_pat
, match_op
))
115 if (attributes
.count("\\" + name_pat
) && match_attr_val(attributes
.at("\\" + name_pat
), value_pat
, match_op
))
121 static bool match_attr(const std::map
<RTLIL::IdString
, RTLIL::Const
> &attributes
, std::string match_expr
)
123 size_t pos
= match_expr
.find_first_of("<!=>");
125 if (pos
!= std::string::npos
) {
126 if (match_expr
.substr(pos
, 2) == "!=")
127 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), '!');
128 if (match_expr
.substr(pos
, 2) == "<=")
129 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), '[');
130 if (match_expr
.substr(pos
, 2) == ">=")
131 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), ']');
132 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+1), match_expr
[pos
]);
135 return match_attr(attributes
, match_expr
, std::string(), 0);
138 static void select_op_neg(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
140 if (lhs
.full_selection
) {
141 lhs
.full_selection
= false;
142 lhs
.selected_modules
.clear();
143 lhs
.selected_members
.clear();
147 if (lhs
.selected_modules
.size() == 0 && lhs
.selected_members
.size() == 0) {
148 lhs
.full_selection
= true;
152 RTLIL::Selection
new_sel(false);
154 for (auto &mod_it
: design
->modules
)
156 if (lhs
.selected_whole_module(mod_it
.first
))
158 if (!lhs
.selected_module(mod_it
.first
)) {
159 new_sel
.selected_modules
.insert(mod_it
.first
);
163 RTLIL::Module
*mod
= mod_it
.second
;
164 for (auto &it
: mod
->wires
)
165 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
166 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
167 for (auto &it
: mod
->memories
)
168 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
169 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
170 for (auto &it
: mod
->cells
)
171 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
172 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
173 for (auto &it
: mod
->processes
)
174 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
175 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
178 lhs
.selected_modules
.swap(new_sel
.selected_modules
);
179 lhs
.selected_members
.swap(new_sel
.selected_members
);
182 static void select_op_submod(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
184 for (auto &mod_it
: design
->modules
)
186 if (lhs
.selected_whole_module(mod_it
.first
))
188 for (auto &cell_it
: mod_it
.second
->cells
)
190 if (design
->modules
.count(cell_it
.second
->type
) == 0)
192 lhs
.selected_modules
.insert(cell_it
.second
->type
);
198 static void select_op_fullmod(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
200 lhs
.optimize(design
);
201 for (auto &it
: lhs
.selected_members
)
202 lhs
.selected_modules
.insert(it
.first
);
203 lhs
.selected_members
.clear();
206 static void select_op_alias(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
208 for (auto &mod_it
: design
->modules
)
210 if (lhs
.selected_whole_module(mod_it
.first
))
212 if (!lhs
.selected_module(mod_it
.first
))
215 SigMap
sigmap(mod_it
.second
);
216 SigPool selected_bits
;
218 for (auto &it
: mod_it
.second
->wires
)
219 if (lhs
.selected_member(mod_it
.first
, it
.first
))
220 selected_bits
.add(sigmap(it
.second
));
222 for (auto &it
: mod_it
.second
->wires
)
223 if (!lhs
.selected_member(mod_it
.first
, it
.first
) && selected_bits
.check_any(sigmap(it
.second
)))
224 lhs
.selected_members
[mod_it
.first
].insert(it
.first
);
228 static void select_op_union(RTLIL::Design
*, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
230 if (rhs
.full_selection
) {
231 lhs
.full_selection
= true;
232 lhs
.selected_modules
.clear();
233 lhs
.selected_members
.clear();
237 if (lhs
.full_selection
)
240 for (auto &it
: rhs
.selected_members
)
241 for (auto &it2
: it
.second
)
242 lhs
.selected_members
[it
.first
].insert(it2
);
244 for (auto &it
: rhs
.selected_modules
) {
245 lhs
.selected_modules
.insert(it
);
246 lhs
.selected_members
.erase(it
);
250 static void select_op_diff(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
252 if (rhs
.full_selection
) {
253 lhs
.full_selection
= false;
254 lhs
.selected_modules
.clear();
255 lhs
.selected_members
.clear();
259 if (lhs
.full_selection
) {
260 if (!rhs
.full_selection
&& rhs
.selected_modules
.size() == 0 && rhs
.selected_members
.size() == 0)
262 lhs
.full_selection
= false;
263 for (auto &it
: design
->modules
)
264 lhs
.selected_modules
.insert(it
.first
);
267 for (auto &it
: rhs
.selected_modules
) {
268 lhs
.selected_modules
.erase(it
);
269 lhs
.selected_members
.erase(it
);
272 for (auto &it
: rhs
.selected_members
)
274 if (design
->modules
.count(it
.first
) == 0)
277 RTLIL::Module
*mod
= design
->modules
[it
.first
];
279 if (lhs
.selected_modules
.count(mod
->name
) > 0)
281 for (auto &it
: mod
->wires
)
282 lhs
.selected_members
[mod
->name
].insert(it
.first
);
283 for (auto &it
: mod
->memories
)
284 lhs
.selected_members
[mod
->name
].insert(it
.first
);
285 for (auto &it
: mod
->cells
)
286 lhs
.selected_members
[mod
->name
].insert(it
.first
);
287 for (auto &it
: mod
->processes
)
288 lhs
.selected_members
[mod
->name
].insert(it
.first
);
289 lhs
.selected_modules
.erase(mod
->name
);
292 if (lhs
.selected_members
.count(mod
->name
) == 0)
295 for (auto &it2
: it
.second
)
296 lhs
.selected_members
[mod
->name
].erase(it2
);
300 static void select_op_intersect(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
302 if (rhs
.full_selection
)
305 if (lhs
.full_selection
) {
306 lhs
.full_selection
= false;
307 for (auto &it
: design
->modules
)
308 lhs
.selected_modules
.insert(it
.first
);
311 std::vector
<RTLIL::IdString
> del_list
;
313 for (auto &it
: lhs
.selected_modules
)
314 if (rhs
.selected_modules
.count(it
) == 0) {
315 if (rhs
.selected_members
.count(it
) > 0)
316 for (auto &it2
: rhs
.selected_members
.at(it
))
317 lhs
.selected_members
[it
].insert(it2
);
318 del_list
.push_back(it
);
320 for (auto &it
: del_list
)
321 lhs
.selected_modules
.erase(it
);
324 for (auto &it
: lhs
.selected_members
) {
325 if (rhs
.selected_modules
.count(it
.first
) > 0)
327 if (rhs
.selected_members
.count(it
.first
) == 0) {
328 del_list
.push_back(it
.first
);
331 std::vector
<RTLIL::IdString
> del_list2
;
332 for (auto &it2
: it
.second
)
333 if (rhs
.selected_members
.at(it
.first
).count(it2
) == 0)
334 del_list2
.push_back(it2
);
335 for (auto &it2
: del_list2
)
336 it
.second
.erase(it2
);
337 if (it
.second
.size() == 0)
338 del_list
.push_back(it
.first
);
340 for (auto &it
: del_list
)
341 lhs
.selected_members
.erase(it
);
345 struct expand_rule_t
{
347 std::set
<RTLIL::IdString
> cell_types
, port_names
;
351 static int parse_comma_list(std::set
<RTLIL::IdString
> &tokens
, std::string str
, size_t pos
, std::string stopchar
)
355 size_t endpos
= str
.find_first_of(stopchar
, pos
);
356 if (endpos
== std::string::npos
)
359 tokens
.insert(RTLIL::escape_id(str
.substr(pos
, endpos
-pos
)));
361 if (pos
== str
.size() || str
[pos
] != ',')
367 static int select_op_expand(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, std::vector
<expand_rule_t
> &rules
, std::set
<RTLIL::IdString
> &limits
, int max_objects
, char mode
, CellTypes
&ct
)
370 bool is_input
, is_output
;
371 for (auto &mod_it
: design
->modules
)
373 if (lhs
.selected_whole_module(mod_it
.first
) || !lhs
.selected_module(mod_it
.first
))
376 RTLIL::Module
*mod
= mod_it
.second
;
377 std::set
<RTLIL::Wire
*> selected_wires
;
379 for (auto &it
: mod
->wires
)
380 if (lhs
.selected_member(mod_it
.first
, it
.first
) && limits
.count(it
.first
) == 0)
381 selected_wires
.insert(it
.second
);
383 for (auto &conn
: mod
->connections
)
385 std::vector
<RTLIL::SigBit
> conn_lhs
= conn
.first
.to_sigbit_vector();
386 std::vector
<RTLIL::SigBit
> conn_rhs
= conn
.second
.to_sigbit_vector();
388 for (size_t i
= 0; i
< conn_lhs
.size(); i
++) {
389 if (conn_lhs
[i
].wire
== NULL
|| conn_rhs
[i
].wire
== NULL
)
391 if (mode
!= 'i' && selected_wires
.count(conn_rhs
[i
].wire
) && lhs
.selected_members
[mod
->name
].count(conn_lhs
[i
].wire
->name
) == 0)
392 lhs
.selected_members
[mod
->name
].insert(conn_lhs
[i
].wire
->name
), sel_objects
++, max_objects
--;
393 if (mode
!= 'o' && selected_wires
.count(conn_lhs
[i
].wire
) && lhs
.selected_members
[mod
->name
].count(conn_rhs
[i
].wire
->name
) == 0)
394 lhs
.selected_members
[mod
->name
].insert(conn_rhs
[i
].wire
->name
), sel_objects
++, max_objects
--;
398 for (auto &cell
: mod
->cells
)
399 for (auto &conn
: cell
.second
->connections
)
401 char last_mode
= '-';
402 for (auto &rule
: rules
) {
403 last_mode
= rule
.mode
;
404 if (rule
.cell_types
.size() > 0 && rule
.cell_types
.count(cell
.second
->type
) == 0)
406 if (rule
.port_names
.size() > 0 && rule
.port_names
.count(conn
.first
) == 0)
408 if (rule
.mode
== '+')
413 if (last_mode
== '+')
416 is_input
= mode
== 'x' || ct
.cell_input(cell
.second
->type
, conn
.first
);
417 is_output
= mode
== 'x' || ct
.cell_output(cell
.second
->type
, conn
.first
);
418 for (auto &chunk
: conn
.second
.chunks
)
419 if (chunk
.wire
!= NULL
) {
420 if (max_objects
!= 0 && selected_wires
.count(chunk
.wire
) > 0 && lhs
.selected_members
[mod
->name
].count(cell
.first
) == 0)
421 if (mode
== 'x' || (mode
== 'i' && is_output
) || (mode
== 'o' && is_input
))
422 lhs
.selected_members
[mod
->name
].insert(cell
.first
), sel_objects
++, max_objects
--;
423 if (max_objects
!= 0 && lhs
.selected_members
[mod
->name
].count(cell
.first
) > 0 && limits
.count(cell
.first
) == 0 && lhs
.selected_members
[mod
->name
].count(chunk
.wire
->name
) == 0)
424 if (mode
== 'x' || (mode
== 'i' && is_input
) || (mode
== 'o' && is_output
))
425 lhs
.selected_members
[mod
->name
].insert(chunk
.wire
->name
), sel_objects
++, max_objects
--;
434 static void select_op_expand(RTLIL::Design
*design
, std::string arg
, char mode
)
436 int pos
= mode
== 'x' ? 2 : 3, levels
= 1, rem_objects
= -1;
437 std::vector
<expand_rule_t
> rules
;
438 std::set
<RTLIL::IdString
> limits
;
445 if (pos
< int(arg
.size()) && arg
[pos
] == '*') {
449 if (pos
< int(arg
.size()) && '0' <= arg
[pos
] && arg
[pos
] <= '9') {
450 size_t endpos
= arg
.find_first_not_of("0123456789", pos
);
451 if (endpos
== std::string::npos
)
453 levels
= atoi(arg
.substr(pos
, endpos
-pos
).c_str());
457 if (pos
< int(arg
.size()) && arg
[pos
] == '.') {
458 size_t endpos
= arg
.find_first_not_of("0123456789", ++pos
);
459 if (endpos
== std::string::npos
)
461 if (int(endpos
) > pos
)
462 rem_objects
= atoi(arg
.substr(pos
, endpos
-pos
).c_str());
466 while (pos
< int(arg
.size())) {
467 if (arg
[pos
] != ':' || pos
+1 == int(arg
.size()))
468 log_cmd_error("Syntax error in expand operator '%s'.\n", arg
.c_str());
470 if (arg
[pos
] == '+' || arg
[pos
] == '-') {
472 rule
.mode
= arg
[pos
++];
473 pos
= parse_comma_list(rule
.cell_types
, arg
, pos
, "[:");
474 if (pos
< int(arg
.size()) && arg
[pos
] == '[') {
475 pos
= parse_comma_list(rule
.port_names
, arg
, pos
+1, "]:");
476 if (pos
< int(arg
.size()) && arg
[pos
] == ']')
479 rules
.push_back(rule
);
481 size_t endpos
= arg
.find(':', pos
);
482 if (endpos
== std::string::npos
)
484 if (int(endpos
) > pos
) {
485 std::string str
= arg
.substr(pos
, endpos
-pos
);
487 str
= RTLIL::escape_id(str
.substr(1));
488 if (design
->selection_vars
.count(str
) > 0) {
489 for (auto i1
: design
->selection_vars
.at(str
).selected_members
)
490 for (auto i2
: i1
.second
)
493 log_cmd_error("Selection %s is not defined!\n", RTLIL::id2cstr(str
));
495 limits
.insert(RTLIL::escape_id(str
));
502 log("expand by %d levels (max. %d objects):\n", levels
, rem_objects
);
503 for (auto &rule
: rules
) {
504 log(" rule (%c):\n", rule
.mode
);
505 if (rule
.cell_types
.size() > 0) {
507 for (auto &it
: rule
.cell_types
)
508 log(" %s", it
.c_str());
511 if (rule
.port_names
.size() > 0) {
513 for (auto &it
: rule
.port_names
)
514 log(" %s", it
.c_str());
518 if (limits
.size() > 0) {
520 for (auto &it
: limits
)
521 log(" %s", it
.c_str());
526 while (levels
-- > 0 && rem_objects
!= 0) {
527 int num_objects
= select_op_expand(design
, work_stack
.back(), rules
, limits
, rem_objects
, mode
, ct
);
528 if (num_objects
== 0)
530 rem_objects
-= num_objects
;
533 if (rem_objects
== 0)
534 log("Warning: reached configured limit at `%s'.\n", arg
.c_str());
537 static void select_filter_active_mod(RTLIL::Design
*design
, RTLIL::Selection
&sel
)
539 if (design
->selected_active_module
.empty())
542 if (sel
.full_selection
) {
543 sel
.full_selection
= false;
544 sel
.selected_modules
.clear();
545 sel
.selected_members
.clear();
546 sel
.selected_modules
.insert(design
->selected_active_module
);
550 std::vector
<std::string
> del_list
;
551 for (auto mod_name
: sel
.selected_modules
)
552 if (mod_name
!= design
->selected_active_module
)
553 del_list
.push_back(mod_name
);
554 for (auto &it
: sel
.selected_members
)
555 if (it
.first
!= design
->selected_active_module
)
556 del_list
.push_back(it
.first
);
557 for (auto mod_name
: del_list
) {
558 sel
.selected_modules
.erase(mod_name
);
559 sel
.selected_members
.erase(mod_name
);
563 static void select_stmt(RTLIL::Design
*design
, std::string arg
)
565 std::string arg_mod
, arg_memb
;
572 if (design
->selection_stack
.size() > 0)
573 work_stack
.push_back(design
->selection_stack
.back());
576 while (work_stack
.size() > 1) {
577 select_op_union(design
, work_stack
.front(), work_stack
.back());
578 work_stack
.pop_back();
582 if (work_stack
.size() < 1)
583 log_cmd_error("Must have at least one element on the stack for operator %%n.\n");
584 select_op_neg(design
, work_stack
[work_stack
.size()-1]);
587 if (work_stack
.size() < 2)
588 log_cmd_error("Must have at least two elements on the stack for operator %%u.\n");
589 select_op_union(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
590 work_stack
.pop_back();
593 if (work_stack
.size() < 2)
594 log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
595 select_op_diff(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
596 work_stack
.pop_back();
599 if (work_stack
.size() < 2)
600 log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
601 select_op_diff(design
, work_stack
[work_stack
.size()-1], work_stack
[work_stack
.size()-2]);
602 work_stack
[work_stack
.size()-2] = work_stack
[work_stack
.size()-1];
603 work_stack
.pop_back();
606 if (work_stack
.size() < 2)
607 log_cmd_error("Must have at least two elements on the stack for operator %%i.\n");
608 select_op_intersect(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
609 work_stack
.pop_back();
612 if (work_stack
.size() < 1)
613 log_cmd_error("Must have at least one element on the stack for operator %%s.\n");
614 select_op_submod(design
, work_stack
[work_stack
.size()-1]);
617 if (work_stack
.size() < 1)
618 log_cmd_error("Must have at least one element on the stack for operator %%c.\n");
619 work_stack
.push_back(work_stack
.back());
622 if (work_stack
.size() < 1)
623 log_cmd_error("Must have at least one element on the stack for operator %%m.\n");
624 select_op_fullmod(design
, work_stack
[work_stack
.size()-1]);
627 if (work_stack
.size() < 1)
628 log_cmd_error("Must have at least one element on the stack for operator %%a.\n");
629 select_op_alias(design
, work_stack
[work_stack
.size()-1]);
631 if (arg
== "%x" || (arg
.size() > 2 && arg
.substr(0, 2) == "%x" && (arg
[2] == ':' || arg
[2] == '*' || arg
[2] == '.' || ('0' <= arg
[2] && arg
[2] <= '9')))) {
632 if (work_stack
.size() < 1)
633 log_cmd_error("Must have at least one element on the stack for operator %%x.\n");
634 select_op_expand(design
, arg
, 'x');
636 if (arg
== "%ci" || (arg
.size() > 3 && arg
.substr(0, 3) == "%ci" && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
637 if (work_stack
.size() < 1)
638 log_cmd_error("Must have at least one element on the stack for operator %%ci.\n");
639 select_op_expand(design
, arg
, 'i');
641 if (arg
== "%co" || (arg
.size() > 3 && arg
.substr(0, 3) == "%co" && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
642 if (work_stack
.size() < 1)
643 log_cmd_error("Must have at least one element on the stack for operator %%co.\n");
644 select_op_expand(design
, arg
, 'o');
646 log_cmd_error("Unknown selection operator '%s'.\n", arg
.c_str());
647 if (work_stack
.size() >= 1)
648 select_filter_active_mod(design
, work_stack
.back());
653 std::string set_name
= RTLIL::escape_id(arg
.substr(1));
654 if (design
->selection_vars
.count(set_name
) > 0)
655 work_stack
.push_back(design
->selection_vars
[set_name
]);
657 log_cmd_error("Selection @%s is not defined!\n", RTLIL::id2cstr(set_name
));
658 select_filter_active_mod(design
, work_stack
.back());
662 if (!design
->selected_active_module
.empty()) {
663 arg_mod
= design
->selected_active_module
;
666 size_t pos
= arg
.find('/');
667 if (pos
== std::string::npos
) {
668 if (arg
.find(':') == std::string::npos
|| arg
.substr(0, 1) == "A")
671 arg_mod
= "*", arg_memb
= arg
;
673 arg_mod
= arg
.substr(0, pos
);
674 arg_memb
= arg
.substr(pos
+1);
678 work_stack
.push_back(RTLIL::Selection());
679 RTLIL::Selection
&sel
= work_stack
.back();
681 if (arg
== "*" && arg_mod
== "*") {
682 select_filter_active_mod(design
, work_stack
.back());
686 sel
.full_selection
= false;
687 for (auto &mod_it
: design
->modules
)
689 if (arg_mod
.substr(0, 2) == "A:") {
690 if (!match_attr(mod_it
.second
->attributes
, arg_mod
.substr(2)))
693 if (!match_ids(mod_it
.first
, arg_mod
))
696 if (arg_memb
== "") {
697 sel
.selected_modules
.insert(mod_it
.first
);
701 RTLIL::Module
*mod
= mod_it
.second
;
702 if (arg_memb
.substr(0, 2) == "w:") {
703 for (auto &it
: mod
->wires
)
704 if (match_ids(it
.first
, arg_memb
.substr(2)))
705 sel
.selected_members
[mod
->name
].insert(it
.first
);
707 if (arg_memb
.substr(0, 2) == "i:") {
708 for (auto &it
: mod
->wires
)
709 if (it
.second
->port_input
&& match_ids(it
.first
, arg_memb
.substr(2)))
710 sel
.selected_members
[mod
->name
].insert(it
.first
);
712 if (arg_memb
.substr(0, 2) == "o:") {
713 for (auto &it
: mod
->wires
)
714 if (it
.second
->port_output
&& match_ids(it
.first
, arg_memb
.substr(2)))
715 sel
.selected_members
[mod
->name
].insert(it
.first
);
717 if (arg_memb
.substr(0, 2) == "x:") {
718 for (auto &it
: mod
->wires
)
719 if ((it
.second
->port_input
|| it
.second
->port_output
) && match_ids(it
.first
, arg_memb
.substr(2)))
720 sel
.selected_members
[mod
->name
].insert(it
.first
);
722 if (arg_memb
.substr(0, 2) == "s:") {
723 size_t delim
= arg_memb
.substr(2).find(':');
724 if (delim
== std::string::npos
) {
725 int width
= atoi(arg_memb
.substr(2).c_str());
726 for (auto &it
: mod
->wires
)
727 if (it
.second
->width
== width
)
728 sel
.selected_members
[mod
->name
].insert(it
.first
);
730 std::string min_str
= arg_memb
.substr(2, delim
);
731 std::string max_str
= arg_memb
.substr(2+delim
+1);
732 int min_width
= min_str
.empty() ? 0 : atoi(min_str
.c_str());
733 int max_width
= max_str
.empty() ? -1 : atoi(max_str
.c_str());
734 for (auto &it
: mod
->wires
)
735 if (min_width
<= it
.second
->width
&& (it
.second
->width
<= max_width
|| max_width
== -1))
736 sel
.selected_members
[mod
->name
].insert(it
.first
);
739 if (arg_memb
.substr(0, 2) == "m:") {
740 for (auto &it
: mod
->memories
)
741 if (match_ids(it
.first
, arg_memb
.substr(2)))
742 sel
.selected_members
[mod
->name
].insert(it
.first
);
744 if (arg_memb
.substr(0, 2) == "c:") {
745 for (auto &it
: mod
->cells
)
746 if (match_ids(it
.first
, arg_memb
.substr(2)))
747 sel
.selected_members
[mod
->name
].insert(it
.first
);
749 if (arg_memb
.substr(0, 2) == "t:") {
750 for (auto &it
: mod
->cells
)
751 if (match_ids(it
.second
->type
, arg_memb
.substr(2)))
752 sel
.selected_members
[mod
->name
].insert(it
.first
);
754 if (arg_memb
.substr(0, 2) == "p:") {
755 for (auto &it
: mod
->processes
)
756 if (match_ids(it
.first
, arg_memb
.substr(2)))
757 sel
.selected_members
[mod
->name
].insert(it
.first
);
759 if (arg_memb
.substr(0, 2) == "a:") {
760 for (auto &it
: mod
->wires
)
761 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
762 sel
.selected_members
[mod
->name
].insert(it
.first
);
763 for (auto &it
: mod
->memories
)
764 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
765 sel
.selected_members
[mod
->name
].insert(it
.first
);
766 for (auto &it
: mod
->cells
)
767 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
768 sel
.selected_members
[mod
->name
].insert(it
.first
);
769 for (auto &it
: mod
->processes
)
770 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
771 sel
.selected_members
[mod
->name
].insert(it
.first
);
773 if (arg_memb
.substr(0, 2) == "r:") {
774 for (auto &it
: mod
->cells
)
775 if (match_attr(it
.second
->parameters
, arg_memb
.substr(2)))
776 sel
.selected_members
[mod
->name
].insert(it
.first
);
778 if (arg_memb
.substr(0, 2) == "n:")
779 arg_memb
= arg_memb
.substr(2);
780 for (auto &it
: mod
->wires
)
781 if (match_ids(it
.first
, arg_memb
))
782 sel
.selected_members
[mod
->name
].insert(it
.first
);
783 for (auto &it
: mod
->memories
)
784 if (match_ids(it
.first
, arg_memb
))
785 sel
.selected_members
[mod
->name
].insert(it
.first
);
786 for (auto &it
: mod
->cells
)
787 if (match_ids(it
.first
, arg_memb
))
788 sel
.selected_members
[mod
->name
].insert(it
.first
);
789 for (auto &it
: mod
->processes
)
790 if (match_ids(it
.first
, arg_memb
))
791 sel
.selected_members
[mod
->name
].insert(it
.first
);
795 select_filter_active_mod(design
, work_stack
.back());
798 // used in kernel/register.cc and maybe other locations, extern decl. in register.h
799 void handle_extra_select_args(Pass
*pass
, std::vector
<std::string
> args
, size_t argidx
, size_t args_size
, RTLIL::Design
*design
)
802 for (; argidx
< args_size
; argidx
++) {
803 if (args
[argidx
].substr(0, 1) == "-") {
805 pass
->cmd_error(args
, argidx
, "Unexpected option in selection arguments.");
807 log_cmd_error("Unexpected option in selection arguments.");
809 select_stmt(design
, args
[argidx
]);
811 while (work_stack
.size() > 1) {
812 select_op_union(design
, work_stack
.front(), work_stack
.back());
813 work_stack
.pop_back();
815 if (work_stack
.size() > 0)
816 design
->selection_stack
.push_back(work_stack
.back());
818 design
->selection_stack
.push_back(RTLIL::Selection(false));
821 struct SelectPass
: public Pass
{
822 SelectPass() : Pass("select", "modify and view the list of selected objects") { }
825 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
827 log(" select [ -add | -del | -set <name> ] <selection>\n");
828 log(" select [ -assert-none | -assert-any ] <selection>\n");
829 log(" select [ -list | -write <filename> | -count | -clear ]\n");
830 log(" select -module <modname>\n");
832 log("Most commands use the list of currently selected objects to determine which part\n");
833 log("of the design to operate on. This command can be used to modify and view this\n");
834 log("list of selected objects.\n");
836 log("Note that many commands support an optional [selection] argument that can be\n");
837 log("used to override the global selection for the command. The syntax of this\n");
838 log("optional argument is identical to the syntax of the <selection> argument\n");
839 log("described here.\n");
841 log(" -add, -del\n");
842 log(" add or remove the given objects to the current selection.\n");
843 log(" without this options the current selection is replaced.\n");
845 log(" -set <name>\n");
846 log(" do not modify the current selection. instead save the new selection\n");
847 log(" under the given name (see @<name> below). to save the current selection,\n");
848 log(" use \"select -set <name> %%\"\n");
850 log(" -assert-none\n");
851 log(" do not modify the current selection. instead assert that the given\n");
852 log(" selection is empty. i.e. produce an error if any object matching the\n");
853 log(" selection is found.\n");
855 log(" -assert-any\n");
856 log(" do not modify the current selection. instead assert that the given\n");
857 log(" selection is non-empty. i.e. produce an error if no object matching\n");
858 log(" the selection is found.\n");
860 log(" -assert-count N\n");
861 log(" do not modify the current selection. instead assert that the given\n");
862 log(" selection contains exactly N objects.\n");
865 log(" list all objects in the current selection\n");
867 log(" -write <filename>\n");
868 log(" like -list but write the output to the specified file\n");
871 log(" count all objects in the current selection\n");
874 log(" clear the current selection. this effectively selects the whole\n");
875 log(" design. it also resets the selected module (see -module). use the\n");
876 log(" command 'select *' to select everything but stay in the current module.\n");
879 log(" create an empty selection. the current module is unchanged.\n");
881 log(" -module <modname>\n");
882 log(" limit the current scope to the specified module.\n");
883 log(" the difference between this and simply selecting the module\n");
884 log(" is that all object names are interpreted relative to this\n");
885 log(" module after this command until the selection is cleared again.\n");
887 log("When this command is called without an argument, the current selection\n");
888 log("is displayed in a compact form (i.e. only the module name when a whole module\n");
889 log("is selected).\n");
891 log("The <selection> argument itself is a series of commands for a simple stack\n");
892 log("machine. Each element on the stack represents a set of selected objects.\n");
893 log("After this commands have been executed, the union of all remaining sets\n");
894 log("on the stack is computed and used as selection for the command.\n");
896 log("Pushing (selecting) object when not in -module mode:\n");
898 log(" <mod_pattern>\n");
899 log(" select the specified module(s)\n");
901 log(" <mod_pattern>/<obj_pattern>\n");
902 log(" select the specified object(s) from the module(s)\n");
904 log("Pushing (selecting) object when in -module mode:\n");
906 log(" <obj_pattern>\n");
907 log(" select the specified object(s) from the current module\n");
909 log("A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])\n");
910 log("matching module names, or one of the following:\n");
912 log(" A:<pattern>, A:<pattern>=<pattern>\n");
913 log(" all modules with an attribute matching the given pattern\n");
914 log(" in addition to = also <, <=, >=, and > are supported\n");
916 log("An <obj_pattern> can be an object name, wildcard expression, or one of\n");
917 log("the following:\n");
919 log(" w:<pattern>\n");
920 log(" all wires with a name matching the given wildcard pattern\n");
922 log(" i:<pattern>, o:<pattern>, x:<pattern>\n");
923 log(" all inputs (i:), outputs (o:) or any ports (x:) with matching names\n");
925 log(" s:<size>, s:<min>:<max>\n");
926 log(" all wires with a matching width\n");
928 log(" m:<pattern>\n");
929 log(" all memories with a name matching the given pattern\n");
931 log(" c:<pattern>\n");
932 log(" all cells with a name matching the given pattern\n");
934 log(" t:<pattern>\n");
935 log(" all cells with a type matching the given pattern\n");
937 log(" p:<pattern>\n");
938 log(" all processes with a name matching the given pattern\n");
940 log(" a:<pattern>\n");
941 log(" all objects with an attribute name matching the given pattern\n");
943 log(" a:<pattern>=<pattern>\n");
944 log(" all objects with a matching attribute name-value-pair.\n");
945 log(" in addition to = also <, <=, >=, and > are supported\n");
947 log(" r:<pattern>, r:<pattern>=<pattern>\n");
948 log(" cells with matching parameters. also with <, <=, >= and >.\n");
950 log(" n:<pattern>\n");
951 log(" all objects with a name matching the given pattern\n");
952 log(" (i.e. 'n:' is optional as it is the default matching rule)\n");
955 log(" push the selection saved prior with 'select -set <name> ...'\n");
957 log("The following actions can be performed on the top sets on the stack:\n");
960 log(" push a copy of the current selection to the stack\n");
963 log(" replace the stack with a union of all elements on it\n");
966 log(" replace top set with its invert\n");
969 log(" replace the two top sets on the stack with their union\n");
972 log(" replace the two top sets on the stack with their intersection\n");
975 log(" pop the top set from the stack and subtract it from the new top\n");
978 log(" like %%d but swap the roles of two top sets on the stack\n");
981 log(" create a copy of the top set rom the stack and push it\n");
983 log(" %%x[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
984 log(" expand top set <num1> num times according to the specified rules.\n");
985 log(" (i.e. select all cells connected to selected wires and select all\n");
986 log(" wires connected to selected cells) The rules specify which cell\n");
987 log(" ports to use for this. the syntax for a rule is a '-' for exclusion\n");
988 log(" and a '+' for inclusion, followed by an optional comma seperated\n");
989 log(" list of cell types followed by an optional comma separated list of\n");
990 log(" cell ports in square brackets. a rule can also be just a cell or wire\n");
991 log(" name that limits the expansion (is included but does not go beyond).\n");
992 log(" select at most <num2> objects. a warning message is printed when this\n");
993 log(" limit is reached. When '*' is used instead of <num1> then the process\n");
994 log(" is repeated until no further object are selected.\n");
996 log(" %%ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
997 log(" %%co[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
998 log(" simmilar to %%x, but only select input (%%ci) or output cones (%%co)\n");
1001 log(" expand top set by selecting all wires that are (at least in part)\n");
1002 log(" aliases for selected wires.\n");
1005 log(" expand top set by adding all modules of instantiated cells in selected\n");
1009 log(" expand top set by selecting all modules that contain selected objects\n");
1011 log("Example: the following command selects all wires that are connected to a\n");
1012 log("'GATE' input of a 'SWITCH' cell:\n");
1014 log(" select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n");
1017 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
1019 bool add_mode
= false;
1020 bool del_mode
= false;
1021 bool clear_mode
= false;
1022 bool none_mode
= false;
1023 bool list_mode
= false;
1024 bool count_mode
= false;
1025 bool got_module
= false;
1026 bool assert_none
= false;
1027 bool assert_any
= false;
1028 int assert_count
= -1;
1029 std::string write_file
;
1030 std::string set_name
;
1031 std::string sel_str
;
1036 for (argidx
= 1; argidx
< args
.size(); argidx
++)
1038 std::string arg
= args
[argidx
];
1039 if (arg
== "-add") {
1043 if (arg
== "-del") {
1047 if (arg
== "-assert-none") {
1051 if (arg
== "-assert-any") {
1055 if (arg
== "-assert-count" && argidx
+1 < args
.size()) {
1056 assert_count
= atoi(args
[++argidx
].c_str());
1059 if (arg
== "-clear") {
1063 if (arg
== "-none") {
1067 if (arg
== "-list") {
1071 if (arg
== "-write" && argidx
+1 < args
.size()) {
1072 write_file
= args
[++argidx
];
1075 if (arg
== "-count") {
1079 if (arg
== "-module" && argidx
+1 < args
.size()) {
1080 RTLIL::IdString mod_name
= RTLIL::escape_id(args
[++argidx
]);
1081 if (design
->modules
.count(mod_name
) == 0)
1082 log_cmd_error("No such module: %s\n", id2cstr(mod_name
));
1083 design
->selected_active_module
= mod_name
;
1087 if (arg
== "-set" && argidx
+1 < args
.size()) {
1088 set_name
= RTLIL::escape_id(args
[++argidx
]);
1091 if (arg
.size() > 0 && arg
[0] == '-')
1092 log_cmd_error("Unkown option %s.\n", arg
.c_str());
1093 select_stmt(design
, arg
);
1094 sel_str
+= " " + arg
;
1097 if (clear_mode
&& args
.size() != 2)
1098 log_cmd_error("Option -clear can not be combined with any other options.\n");
1100 if (none_mode
&& args
.size() != 2)
1101 log_cmd_error("Option -none can not be combined with any other options.\n");
1103 if (add_mode
+ del_mode
+ assert_none
+ assert_any
+ (assert_count
>= 0) > 1)
1104 log_cmd_error("Options -add, -del, -assert-none, -assert-any or -assert-count can not be combined.\n");
1106 if ((list_mode
|| !write_file
.empty() || count_mode
) && (add_mode
|| del_mode
|| assert_none
|| assert_any
|| assert_count
>= 0))
1107 log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none, -assert-any or -assert-count.\n");
1109 if (!set_name
.empty() && (list_mode
|| !write_file
.empty() || count_mode
|| add_mode
|| del_mode
|| assert_none
|| assert_any
|| assert_count
>= 0))
1110 log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any or -assert-count.\n");
1112 if (work_stack
.size() == 0 && got_module
) {
1113 RTLIL::Selection sel
;
1114 select_filter_active_mod(design
, sel
);
1115 work_stack
.push_back(sel
);
1118 while (work_stack
.size() > 1) {
1119 select_op_union(design
, work_stack
.front(), work_stack
.back());
1120 work_stack
.pop_back();
1123 assert(design
->selection_stack
.size() > 0);
1126 design
->selection_stack
.back() = RTLIL::Selection(true);
1127 design
->selected_active_module
= std::string();
1132 design
->selection_stack
.back() = RTLIL::Selection(false);
1136 if (list_mode
|| count_mode
|| !write_file
.empty())
1138 #define LOG_OBJECT(...) do { if (list_mode) log(__VA_ARGS__); if (f != NULL) fprintf(f, __VA_ARGS__); total_count++; } while (0)
1139 int total_count
= 0;
1141 if (!write_file
.empty()) {
1142 f
= fopen(write_file
.c_str(), "w");
1144 log_error("Can't open '%s' for writing: %s\n", write_file
.c_str(), strerror(errno
));
1146 RTLIL::Selection
*sel
= &design
->selection_stack
.back();
1147 if (work_stack
.size() > 0)
1148 sel
= &work_stack
.back();
1149 sel
->optimize(design
);
1150 for (auto mod_it
: design
->modules
)
1152 if (sel
->selected_whole_module(mod_it
.first
) && list_mode
)
1153 log("%s\n", id2cstr(mod_it
.first
));
1154 if (sel
->selected_module(mod_it
.first
)) {
1155 for (auto &it
: mod_it
.second
->wires
)
1156 if (sel
->selected_member(mod_it
.first
, it
.first
))
1157 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
));
1158 for (auto &it
: mod_it
.second
->memories
)
1159 if (sel
->selected_member(mod_it
.first
, it
.first
))
1160 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
));
1161 for (auto &it
: mod_it
.second
->cells
)
1162 if (sel
->selected_member(mod_it
.first
, it
.first
))
1163 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
));
1164 for (auto &it
: mod_it
.second
->processes
)
1165 if (sel
->selected_member(mod_it
.first
, it
.first
))
1166 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
));
1170 log("%d objects.\n", total_count
);
1179 if (work_stack
.size() == 0)
1180 log_cmd_error("Nothing to add to selection.\n");
1181 select_op_union(design
, design
->selection_stack
.back(), work_stack
.back());
1182 design
->selection_stack
.back().optimize(design
);
1188 if (work_stack
.size() == 0)
1189 log_cmd_error("Nothing to delete from selection.\n");
1190 select_op_diff(design
, design
->selection_stack
.back(), work_stack
.back());
1191 design
->selection_stack
.back().optimize(design
);
1197 if (work_stack
.size() == 0)
1198 log_cmd_error("No selection to check.\n");
1199 if (!work_stack
.back().empty())
1200 log_error("Assertation failed: selection is not empty:%s\n", sel_str
.c_str());
1206 if (work_stack
.size() == 0)
1207 log_cmd_error("No selection to check.\n");
1208 if (work_stack
.back().empty())
1209 log_error("Assertation failed: selection is empty:%s\n", sel_str
.c_str());
1213 if (assert_count
>= 0)
1215 int total_count
= 0;
1216 if (work_stack
.size() == 0)
1217 log_cmd_error("No selection to check.\n");
1218 RTLIL::Selection
*sel
= &work_stack
.back();
1219 sel
->optimize(design
);
1220 for (auto mod_it
: design
->modules
)
1221 if (sel
->selected_module(mod_it
.first
)) {
1222 for (auto &it
: mod_it
.second
->wires
)
1223 if (sel
->selected_member(mod_it
.first
, it
.first
))
1225 for (auto &it
: mod_it
.second
->memories
)
1226 if (sel
->selected_member(mod_it
.first
, it
.first
))
1228 for (auto &it
: mod_it
.second
->cells
)
1229 if (sel
->selected_member(mod_it
.first
, it
.first
))
1231 for (auto &it
: mod_it
.second
->processes
)
1232 if (sel
->selected_member(mod_it
.first
, it
.first
))
1235 if (assert_count
!= total_count
)
1236 log_error("Assertation failed: selection contains %d elements instead of the asserted %d:%s\n",
1237 total_count
, assert_count
, sel_str
.c_str());
1241 if (!set_name
.empty())
1243 if (work_stack
.size() == 0)
1244 design
->selection_vars
[set_name
] = RTLIL::Selection(false);
1246 design
->selection_vars
[set_name
] = work_stack
.back();
1250 if (work_stack
.size() == 0) {
1251 RTLIL::Selection
&sel
= design
->selection_stack
.back();
1252 if (sel
.full_selection
)
1254 for (auto &it
: sel
.selected_modules
)
1255 log("%s\n", id2cstr(it
));
1256 for (auto &it
: sel
.selected_members
)
1257 for (auto &it2
: it
.second
)
1258 log("%s/%s\n", id2cstr(it
.first
), id2cstr(it2
));
1262 design
->selection_stack
.back() = work_stack
.back();
1263 design
->selection_stack
.back().optimize(design
);
1267 struct CdPass
: public Pass
{
1268 CdPass() : Pass("cd", "a shortcut for 'select -module <name>'") { }
1271 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1273 log(" cd <modname>\n");
1275 log("This is just a shortcut for 'select -module <modname>'.\n");
1278 log(" cd <cellname>\n");
1280 log("When no module with the specified name is found, but there is a cell\n");
1281 log("with the specified name in the current module, then this is equivialent\n");
1282 log("to 'cd <celltype>'.\n");
1286 log("This is just a shortcut for 'select -clear'.\n");
1289 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
1291 if (args
.size() != 2)
1292 log_cmd_error("Invalid number of arguments.\n");
1294 if (args
[1] == "..") {
1295 design
->selection_stack
.back() = RTLIL::Selection(true);
1296 design
->selected_active_module
= std::string();
1300 std::string modname
= RTLIL::escape_id(args
[1]);
1302 if (design
->modules
.count(modname
) == 0 && !design
->selected_active_module
.empty()) {
1303 RTLIL::Module
*module
= NULL
;
1304 if (design
->modules
.count(design
->selected_active_module
) > 0)
1305 module
= design
->modules
.at(design
->selected_active_module
);
1306 if (module
!= NULL
&& module
->cells
.count(modname
) > 0)
1307 modname
= module
->cells
.at(modname
)->type
;
1310 if (design
->modules
.count(modname
) > 0) {
1311 design
->selected_active_module
= modname
;
1312 design
->selection_stack
.back() = RTLIL::Selection();
1313 select_filter_active_mod(design
, design
->selection_stack
.back());
1314 design
->selection_stack
.back().optimize(design
);
1318 log_cmd_error("No such module `%s' found!\n", RTLIL::id2cstr(modname
));
1322 template<typename T
>
1323 static int log_matches(const char *title
, std::string pattern
, T list
)
1325 std::vector
<std::string
> matches
;
1327 for (auto &it
: list
)
1328 if (pattern
.empty() || match_ids(it
.first
, pattern
))
1329 matches
.push_back(it
.first
);
1331 if (matches
.empty())
1334 log("\n%d %s:\n", int(matches
.size()), title
);
1335 for (auto &id
: matches
)
1336 log(" %s\n", RTLIL::id2cstr(id
));
1337 return matches
.size();
1340 struct LsPass
: public Pass
{
1341 LsPass() : Pass("ls", "list modules or objects in modules") { }
1344 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1346 log(" ls [pattern]\n");
1348 log("When no active module is selected, this prints a list of all modules.\n");
1350 log("When an active module is selected, this prints a list of objects in the module.\n");
1352 log("If a pattern is given, the objects matching the pattern are printed\n");
1354 log("Note that this command does not use the selection mechanism and always operates\n");
1355 log("on the whole design or whole active module. Use 'select -list' to show a list\n");
1356 log("of currently selected objects.\n");
1359 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
1361 std::string pattern
;
1364 if (args
.size() != 1 && args
.size() != 2)
1365 log_cmd_error("Invalid number of arguments.\n");
1366 if (args
.size() == 2)
1367 pattern
= args
.at(1);
1369 if (design
->selected_active_module
.empty())
1371 counter
+= log_matches("modules", pattern
, design
->modules
);
1374 if (design
->modules
.count(design
->selected_active_module
) > 0)
1376 RTLIL::Module
*module
= design
->modules
.at(design
->selected_active_module
);
1377 counter
+= log_matches("wires", pattern
, module
->wires
);
1378 counter
+= log_matches("memories", pattern
, module
->memories
);
1379 counter
+= log_matches("cells", pattern
, module
->cells
);
1380 counter
+= log_matches("processes", pattern
, module
->processes
);
1383 // log("\nfound %d item%s.\n", counter, counter == 1 ? "" : "s");