2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/log.h"
28 static std::vector
<RTLIL::Selection
> work_stack
;
30 static bool match_ids(RTLIL::IdString id
, std::string pattern
)
34 if (id
.size() > 0 && id
[0] == '\\' && id
.substr(1) == pattern
)
36 if (!fnmatch(pattern
.c_str(), id
.c_str(), 0))
38 if (id
.size() > 0 && id
[0] == '\\' && !fnmatch(pattern
.c_str(), id
.substr(1).c_str(), 0))
40 if (id
.size() > 0 && id
[0] == '$' && pattern
.size() > 0 && pattern
[0] == '$') {
41 const char *p
= id
.c_str();
42 const char *q
= strrchr(p
, '$');
49 static bool match_attr_val(const RTLIL::Const
&value
, std::string pattern
, char match_op
)
54 if ((value
.flags
& RTLIL::CONST_FLAG_STRING
) == 0)
56 RTLIL::SigSpec sig_value
;
58 if (!RTLIL::SigSpec::parse(sig_value
, NULL
, pattern
))
61 RTLIL::Const pattern_value
= sig_value
.as_const();
64 return value
== pattern_value
;
66 return value
.as_int() < pattern_value
.as_int();
68 return value
.as_int() > pattern_value
.as_int();
70 return value
.as_int() <= pattern_value
.as_int();
72 return value
.as_int() >= pattern_value
.as_int();
76 std::string value_str
= value
.decode_string();
79 if (!fnmatch(pattern
.c_str(), value
.decode_string().c_str(), FNM_NOESCAPE
))
83 return value_str
== pattern
;
85 return value_str
< pattern
;
87 return value_str
> pattern
;
89 return value_str
<= pattern
;
91 return value_str
>= pattern
;
97 static bool match_attr(const std::map
<RTLIL::IdString
, RTLIL::Const
> &attributes
, std::string name_pat
, std::string value_pat
, char match_op
)
99 if (name_pat
.find('*') != std::string::npos
|| name_pat
.find('?') != std::string::npos
|| name_pat
.find('[') != std::string::npos
) {
100 for (auto &it
: attributes
) {
101 if (!fnmatch(name_pat
.c_str(), it
.first
.c_str(), FNM_NOESCAPE
) && match_attr_val(it
.second
, value_pat
, match_op
))
103 if (it
.first
.size() > 0 && it
.first
[0] == '\\' && !fnmatch(name_pat
.c_str(), it
.first
.substr(1).c_str(), FNM_NOESCAPE
) && match_attr_val(it
.second
, value_pat
, match_op
))
107 if (name_pat
.size() > 0 && (name_pat
[0] == '\\' || name_pat
[0] == '$') && attributes
.count(name_pat
) && match_attr_val(attributes
.at(name_pat
), value_pat
, match_op
))
109 if (attributes
.count("\\" + name_pat
) && match_attr_val(attributes
.at("\\" + name_pat
), value_pat
, match_op
))
115 static bool match_attr(const std::map
<RTLIL::IdString
, RTLIL::Const
> &attributes
, std::string match_expr
)
117 size_t pos
= match_expr
.find_first_of("<=>");
119 if (pos
!= std::string::npos
) {
120 if (match_expr
.substr(pos
, 2) == "<=")
121 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), '[');
122 if (match_expr
.substr(pos
, 2) == ">=")
123 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), ']');
124 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+1), match_expr
[pos
]);
127 return match_attr(attributes
, match_expr
, std::string(), 0);
130 static void select_op_neg(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
132 if (lhs
.full_selection
) {
133 lhs
.full_selection
= false;
134 lhs
.selected_modules
.clear();
135 lhs
.selected_members
.clear();
139 if (lhs
.selected_modules
.size() == 0 && lhs
.selected_members
.size() == 0) {
140 lhs
.full_selection
= true;
144 RTLIL::Selection
new_sel(false);
146 for (auto &mod_it
: design
->modules
)
148 if (lhs
.selected_whole_module(mod_it
.first
))
150 if (!lhs
.selected_module(mod_it
.first
)) {
151 new_sel
.selected_modules
.insert(mod_it
.first
);
155 RTLIL::Module
*mod
= mod_it
.second
;
156 for (auto &it
: mod
->wires
)
157 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
158 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
159 for (auto &it
: mod
->memories
)
160 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
161 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
162 for (auto &it
: mod
->cells
)
163 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
164 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
165 for (auto &it
: mod
->processes
)
166 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
167 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
170 lhs
.selected_modules
.swap(new_sel
.selected_modules
);
171 lhs
.selected_members
.swap(new_sel
.selected_members
);
174 static void select_op_submod(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
176 for (auto &mod_it
: design
->modules
)
178 if (lhs
.selected_whole_module(mod_it
.first
))
180 for (auto &cell_it
: mod_it
.second
->cells
)
182 if (design
->modules
.count(cell_it
.second
->type
) == 0)
184 lhs
.selected_modules
.insert(cell_it
.second
->type
);
190 static void select_op_union(RTLIL::Design
*, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
192 if (rhs
.full_selection
) {
193 lhs
.full_selection
= true;
194 lhs
.selected_modules
.clear();
195 lhs
.selected_members
.clear();
199 if (lhs
.full_selection
)
202 for (auto &it
: rhs
.selected_members
)
203 for (auto &it2
: it
.second
)
204 lhs
.selected_members
[it
.first
].insert(it2
);
206 for (auto &it
: rhs
.selected_modules
) {
207 lhs
.selected_modules
.insert(it
);
208 lhs
.selected_members
.erase(it
);
212 static void select_op_diff(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
214 if (rhs
.full_selection
) {
215 lhs
.full_selection
= false;
216 lhs
.selected_modules
.clear();
217 lhs
.selected_members
.clear();
221 if (lhs
.full_selection
) {
222 if (!rhs
.full_selection
&& rhs
.selected_modules
.size() == 0 && rhs
.selected_members
.size() == 0)
224 lhs
.full_selection
= false;
225 for (auto &it
: design
->modules
)
226 lhs
.selected_modules
.insert(it
.first
);
229 for (auto &it
: rhs
.selected_modules
) {
230 lhs
.selected_modules
.erase(it
);
231 lhs
.selected_members
.erase(it
);
234 for (auto &it
: rhs
.selected_members
)
236 if (design
->modules
.count(it
.first
) == 0)
239 RTLIL::Module
*mod
= design
->modules
[it
.first
];
241 if (lhs
.selected_modules
.count(mod
->name
) > 0)
243 for (auto &it
: mod
->wires
)
244 lhs
.selected_members
[mod
->name
].insert(it
.first
);
245 for (auto &it
: mod
->memories
)
246 lhs
.selected_members
[mod
->name
].insert(it
.first
);
247 for (auto &it
: mod
->cells
)
248 lhs
.selected_members
[mod
->name
].insert(it
.first
);
249 for (auto &it
: mod
->processes
)
250 lhs
.selected_members
[mod
->name
].insert(it
.first
);
251 lhs
.selected_modules
.erase(mod
->name
);
254 if (lhs
.selected_members
.count(mod
->name
) == 0)
257 for (auto &it2
: it
.second
)
258 lhs
.selected_members
[mod
->name
].erase(it2
);
262 static void select_op_intersect(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
264 if (rhs
.full_selection
)
267 if (lhs
.full_selection
) {
268 lhs
.full_selection
= false;
269 for (auto &it
: design
->modules
)
270 lhs
.selected_modules
.insert(it
.first
);
273 std::vector
<RTLIL::IdString
> del_list
;
275 for (auto &it
: lhs
.selected_modules
)
276 if (rhs
.selected_modules
.count(it
) == 0) {
277 if (rhs
.selected_members
.count(it
) > 0)
278 for (auto &it2
: rhs
.selected_members
.at(it
))
279 lhs
.selected_members
[it
].insert(it2
);
280 del_list
.push_back(it
);
282 for (auto &it
: del_list
)
283 lhs
.selected_modules
.erase(it
);
286 for (auto &it
: lhs
.selected_members
) {
287 if (rhs
.selected_modules
.count(it
.first
) > 0)
289 if (rhs
.selected_members
.count(it
.first
) == 0) {
290 del_list
.push_back(it
.first
);
293 std::vector
<RTLIL::IdString
> del_list2
;
294 for (auto &it2
: it
.second
)
295 if (rhs
.selected_members
.at(it
.first
).count(it2
) == 0)
296 del_list2
.push_back(it2
);
297 for (auto &it2
: del_list2
)
298 it
.second
.erase(it2
);
299 if (it
.second
.size() == 0)
300 del_list
.push_back(it
.first
);
302 for (auto &it
: del_list
)
303 lhs
.selected_members
.erase(it
);
307 struct expand_rule_t
{
309 std::set
<RTLIL::IdString
> cell_types
, port_names
;
313 static int parse_comma_list(std::set
<RTLIL::IdString
> &tokens
, std::string str
, size_t pos
, std::string stopchar
)
317 size_t endpos
= str
.find_first_of(stopchar
, pos
);
318 if (endpos
== std::string::npos
)
321 tokens
.insert(RTLIL::escape_id(str
.substr(pos
, endpos
-pos
)));
323 if (pos
== str
.size() || str
[pos
] != ',')
329 static int select_op_expand(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, std::vector
<expand_rule_t
> &rules
, std::set
<RTLIL::IdString
> &limits
, int max_objects
, char mode
, CellTypes
&ct
)
332 bool is_input
, is_output
;
333 for (auto &mod_it
: design
->modules
)
335 if (lhs
.selected_whole_module(mod_it
.first
) || !lhs
.selected_module(mod_it
.first
))
338 RTLIL::Module
*mod
= mod_it
.second
;
339 std::set
<RTLIL::Wire
*> selected_wires
;
341 for (auto &it
: mod
->wires
)
342 if (lhs
.selected_member(mod_it
.first
, it
.first
) && limits
.count(it
.first
) == 0)
343 selected_wires
.insert(it
.second
);
345 for (auto &conn
: mod
->connections
)
347 std::vector
<RTLIL::SigBit
> conn_lhs
= conn
.first
.to_sigbit_vector();
348 std::vector
<RTLIL::SigBit
> conn_rhs
= conn
.second
.to_sigbit_vector();
350 for (size_t i
= 0; i
< conn_lhs
.size(); i
++) {
351 if (conn_lhs
[i
].wire
== NULL
|| conn_rhs
[i
].wire
== NULL
)
353 if (mode
!= 'i' && selected_wires
.count(conn_rhs
[i
].wire
) && lhs
.selected_members
[mod
->name
].count(conn_lhs
[i
].wire
->name
) == 0)
354 lhs
.selected_members
[mod
->name
].insert(conn_lhs
[i
].wire
->name
), sel_objects
++, max_objects
--;
355 if (mode
!= 'o' && selected_wires
.count(conn_lhs
[i
].wire
) && lhs
.selected_members
[mod
->name
].count(conn_rhs
[i
].wire
->name
) == 0)
356 lhs
.selected_members
[mod
->name
].insert(conn_rhs
[i
].wire
->name
), sel_objects
++, max_objects
--;
360 for (auto &cell
: mod
->cells
)
361 for (auto &conn
: cell
.second
->connections
)
363 char last_mode
= '-';
364 for (auto &rule
: rules
) {
365 last_mode
= rule
.mode
;
366 if (rule
.cell_types
.size() > 0 && rule
.cell_types
.count(cell
.second
->type
) == 0)
368 if (rule
.port_names
.size() > 0 && rule
.port_names
.count(conn
.first
) == 0)
370 if (rule
.mode
== '+')
375 if (last_mode
== '+')
378 is_input
= mode
== 'x' || ct
.cell_input(cell
.second
->type
, conn
.first
);
379 is_output
= mode
== 'x' || ct
.cell_output(cell
.second
->type
, conn
.first
);
380 for (auto &chunk
: conn
.second
.chunks
)
381 if (chunk
.wire
!= NULL
) {
382 if (max_objects
!= 0 && selected_wires
.count(chunk
.wire
) > 0 && lhs
.selected_members
[mod
->name
].count(cell
.first
) == 0)
383 if (mode
== 'x' || (mode
== 'i' && is_output
) || (mode
== 'o' && is_input
))
384 lhs
.selected_members
[mod
->name
].insert(cell
.first
), sel_objects
++, max_objects
--;
385 if (max_objects
!= 0 && lhs
.selected_members
[mod
->name
].count(cell
.first
) > 0 && limits
.count(cell
.first
) == 0 && lhs
.selected_members
[mod
->name
].count(chunk
.wire
->name
) == 0)
386 if (mode
== 'x' || (mode
== 'i' && is_input
) || (mode
== 'o' && is_output
))
387 lhs
.selected_members
[mod
->name
].insert(chunk
.wire
->name
), sel_objects
++, max_objects
--;
396 static void select_op_expand(RTLIL::Design
*design
, std::string arg
, char mode
)
398 int pos
= mode
== 'x' ? 2 : 3, levels
= 1, rem_objects
= -1;
399 std::vector
<expand_rule_t
> rules
;
400 std::set
<RTLIL::IdString
> limits
;
407 if (pos
< int(arg
.size()) && arg
[pos
] == '*') {
411 if (pos
< int(arg
.size()) && '0' <= arg
[pos
] && arg
[pos
] <= '9') {
412 size_t endpos
= arg
.find_first_not_of("0123456789", pos
);
413 if (endpos
== std::string::npos
)
415 levels
= atoi(arg
.substr(pos
, endpos
-pos
).c_str());
419 if (pos
< int(arg
.size()) && arg
[pos
] == '.') {
420 size_t endpos
= arg
.find_first_not_of("0123456789", ++pos
);
421 if (endpos
== std::string::npos
)
423 if (int(endpos
) > pos
)
424 rem_objects
= atoi(arg
.substr(pos
, endpos
-pos
).c_str());
428 while (pos
< int(arg
.size())) {
429 if (arg
[pos
] != ':' || pos
+1 == int(arg
.size()))
430 log_cmd_error("Syntax error in expand operator '%s'.\n", arg
.c_str());
432 if (arg
[pos
] == '+' || arg
[pos
] == '-') {
434 rule
.mode
= arg
[pos
++];
435 pos
= parse_comma_list(rule
.cell_types
, arg
, pos
, "[:");
436 if (pos
< int(arg
.size()) && arg
[pos
] == '[') {
437 pos
= parse_comma_list(rule
.port_names
, arg
, pos
+1, "]:");
438 if (pos
< int(arg
.size()) && arg
[pos
] == ']')
441 rules
.push_back(rule
);
443 size_t endpos
= arg
.find(':', pos
);
444 if (endpos
== std::string::npos
)
446 if (int(endpos
) > pos
) {
447 std::string str
= arg
.substr(pos
, endpos
-pos
);
449 str
= RTLIL::escape_id(str
.substr(1));
450 if (design
->selection_vars
.count(str
) > 0) {
451 for (auto i1
: design
->selection_vars
.at(str
).selected_members
)
452 for (auto i2
: i1
.second
)
455 log_cmd_error("Selection %s is not defined!\n", RTLIL::id2cstr(str
));
457 limits
.insert(RTLIL::escape_id(str
));
464 log("expand by %d levels (max. %d objects):\n", levels
, rem_objects
);
465 for (auto &rule
: rules
) {
466 log(" rule (%c):\n", rule
.mode
);
467 if (rule
.cell_types
.size() > 0) {
469 for (auto &it
: rule
.cell_types
)
470 log(" %s", it
.c_str());
473 if (rule
.port_names
.size() > 0) {
475 for (auto &it
: rule
.port_names
)
476 log(" %s", it
.c_str());
480 if (limits
.size() > 0) {
482 for (auto &it
: limits
)
483 log(" %s", it
.c_str());
488 while (levels
-- > 0 && rem_objects
!= 0) {
489 int num_objects
= select_op_expand(design
, work_stack
.back(), rules
, limits
, rem_objects
, mode
, ct
);
490 if (num_objects
== 0)
492 rem_objects
-= num_objects
;
495 if (rem_objects
== 0)
496 log("Warning: reached configured limit at `%s'.\n", arg
.c_str());
499 static void select_filter_active_mod(RTLIL::Design
*design
, RTLIL::Selection
&sel
)
501 if (design
->selected_active_module
.empty())
504 if (sel
.full_selection
) {
505 sel
.full_selection
= false;
506 sel
.selected_modules
.clear();
507 sel
.selected_members
.clear();
508 sel
.selected_modules
.insert(design
->selected_active_module
);
512 std::vector
<std::string
> del_list
;
513 for (auto mod_name
: sel
.selected_modules
)
514 if (mod_name
!= design
->selected_active_module
)
515 del_list
.push_back(mod_name
);
516 for (auto &it
: sel
.selected_members
)
517 if (it
.first
!= design
->selected_active_module
)
518 del_list
.push_back(it
.first
);
519 for (auto mod_name
: del_list
) {
520 sel
.selected_modules
.erase(mod_name
);
521 sel
.selected_members
.erase(mod_name
);
525 static void select_stmt(RTLIL::Design
*design
, std::string arg
)
527 std::string arg_mod
, arg_memb
;
534 if (design
->selection_stack
.size() > 0)
535 work_stack
.push_back(design
->selection_stack
.back());
538 while (work_stack
.size() > 1) {
539 select_op_union(design
, work_stack
.front(), work_stack
.back());
540 work_stack
.pop_back();
544 if (work_stack
.size() < 1)
545 log_cmd_error("Must have at least one element on the stack for operator %%n.\n");
546 select_op_neg(design
, work_stack
[work_stack
.size()-1]);
549 if (work_stack
.size() < 2)
550 log_cmd_error("Must have at least two elements on the stack for operator %%u.\n");
551 select_op_union(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
552 work_stack
.pop_back();
555 if (work_stack
.size() < 2)
556 log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
557 select_op_diff(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
558 work_stack
.pop_back();
561 if (work_stack
.size() < 2)
562 log_cmd_error("Must have at least two elements on the stack for operator %%i.\n");
563 select_op_intersect(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
564 work_stack
.pop_back();
567 if (work_stack
.size() < 1)
568 log_cmd_error("Must have at least one element on the stack for operator %%s.\n");
569 select_op_submod(design
, work_stack
[work_stack
.size()-1]);
571 if (arg
== "%x" || (arg
.size() > 2 && arg
.substr(0, 2) == "%x" && (arg
[2] == ':' || arg
[2] == '*' || arg
[2] == '.' || ('0' <= arg
[2] && arg
[2] <= '9')))) {
572 if (work_stack
.size() < 1)
573 log_cmd_error("Must have at least one element on the stack for operator %%x.\n");
574 select_op_expand(design
, arg
, 'x');
576 if (arg
== "%ci" || (arg
.size() > 3 && arg
.substr(0, 3) == "%ci" && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
577 if (work_stack
.size() < 1)
578 log_cmd_error("Must have at least one element on the stack for operator %%ci.\n");
579 select_op_expand(design
, arg
, 'i');
581 if (arg
== "%co" || (arg
.size() > 3 && arg
.substr(0, 3) == "%co" && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
582 if (work_stack
.size() < 1)
583 log_cmd_error("Must have at least one element on the stack for operator %%co.\n");
584 select_op_expand(design
, arg
, 'o');
586 log_cmd_error("Unknown selection operator '%s'.\n", arg
.c_str());
587 if (work_stack
.size() >= 1)
588 select_filter_active_mod(design
, work_stack
.back());
593 std::string set_name
= RTLIL::escape_id(arg
.substr(1));
594 if (design
->selection_vars
.count(set_name
) > 0)
595 work_stack
.push_back(design
->selection_vars
[set_name
]);
597 log_cmd_error("Selection @%s is not defined!\n", RTLIL::id2cstr(set_name
));
598 select_filter_active_mod(design
, work_stack
.back());
602 if (!design
->selected_active_module
.empty()) {
603 arg_mod
= design
->selected_active_module
;
606 size_t pos
= arg
.find('/');
607 if (pos
== std::string::npos
) {
608 if (arg
.find(':') == std::string::npos
|| arg
.substr(0, 1) == "A")
611 arg_mod
= "*", arg_memb
= arg
;
613 arg_mod
= arg
.substr(0, pos
);
614 arg_memb
= arg
.substr(pos
+1);
618 work_stack
.push_back(RTLIL::Selection());
619 RTLIL::Selection
&sel
= work_stack
.back();
621 if (arg
== "*" && arg_mod
== "*") {
622 select_filter_active_mod(design
, work_stack
.back());
626 sel
.full_selection
= false;
627 for (auto &mod_it
: design
->modules
)
629 if (arg_mod
.substr(0, 2) == "A:") {
630 if (!match_attr(mod_it
.second
->attributes
, arg_mod
.substr(2)))
633 if (!match_ids(mod_it
.first
, arg_mod
))
636 if (arg_memb
== "") {
637 sel
.selected_modules
.insert(mod_it
.first
);
641 RTLIL::Module
*mod
= mod_it
.second
;
642 if (arg_memb
.substr(0, 2) == "w:") {
643 for (auto &it
: mod
->wires
)
644 if (match_ids(it
.first
, arg_memb
.substr(2)))
645 sel
.selected_members
[mod
->name
].insert(it
.first
);
647 if (arg_memb
.substr(0, 2) == "m:") {
648 for (auto &it
: mod
->memories
)
649 if (match_ids(it
.first
, arg_memb
.substr(2)))
650 sel
.selected_members
[mod
->name
].insert(it
.first
);
652 if (arg_memb
.substr(0, 2) == "c:") {
653 for (auto &it
: mod
->cells
)
654 if (match_ids(it
.first
, arg_memb
.substr(2)))
655 sel
.selected_members
[mod
->name
].insert(it
.first
);
657 if (arg_memb
.substr(0, 2) == "t:") {
658 for (auto &it
: mod
->cells
)
659 if (match_ids(it
.second
->type
, arg_memb
.substr(2)))
660 sel
.selected_members
[mod
->name
].insert(it
.first
);
662 if (arg_memb
.substr(0, 2) == "p:") {
663 for (auto &it
: mod
->processes
)
664 if (match_ids(it
.first
, arg_memb
.substr(2)))
665 sel
.selected_members
[mod
->name
].insert(it
.first
);
667 if (arg_memb
.substr(0, 2) == "a:") {
668 for (auto &it
: mod
->wires
)
669 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
670 sel
.selected_members
[mod
->name
].insert(it
.first
);
671 for (auto &it
: mod
->memories
)
672 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
673 sel
.selected_members
[mod
->name
].insert(it
.first
);
674 for (auto &it
: mod
->cells
)
675 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
676 sel
.selected_members
[mod
->name
].insert(it
.first
);
677 for (auto &it
: mod
->processes
)
678 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
679 sel
.selected_members
[mod
->name
].insert(it
.first
);
681 if (arg_memb
.substr(0, 2) == "r:") {
682 for (auto &it
: mod
->cells
)
683 if (match_attr(it
.second
->parameters
, arg_memb
.substr(2)))
684 sel
.selected_members
[mod
->name
].insert(it
.first
);
686 if (arg_memb
.substr(0, 2) == "n:")
687 arg_memb
= arg_memb
.substr(2);
688 for (auto &it
: mod
->wires
)
689 if (match_ids(it
.first
, arg_memb
))
690 sel
.selected_members
[mod
->name
].insert(it
.first
);
691 for (auto &it
: mod
->memories
)
692 if (match_ids(it
.first
, arg_memb
))
693 sel
.selected_members
[mod
->name
].insert(it
.first
);
694 for (auto &it
: mod
->cells
)
695 if (match_ids(it
.first
, arg_memb
))
696 sel
.selected_members
[mod
->name
].insert(it
.first
);
697 for (auto &it
: mod
->processes
)
698 if (match_ids(it
.first
, arg_memb
))
699 sel
.selected_members
[mod
->name
].insert(it
.first
);
703 select_filter_active_mod(design
, work_stack
.back());
706 // used in kernel/register.cc and maybe other locations, extern decl. in register.h
707 void handle_extra_select_args(Pass
*pass
, std::vector
<std::string
> args
, size_t argidx
, size_t args_size
, RTLIL::Design
*design
)
710 for (; argidx
< args_size
; argidx
++) {
711 if (args
[argidx
].substr(0, 1) == "-") {
713 pass
->cmd_error(args
, argidx
, "Unexpected option in selection arguments.");
715 log_cmd_error("Unexpected option in selection arguments.");
717 select_stmt(design
, args
[argidx
]);
719 while (work_stack
.size() > 1) {
720 select_op_union(design
, work_stack
.front(), work_stack
.back());
721 work_stack
.pop_back();
723 if (work_stack
.size() > 0)
724 design
->selection_stack
.push_back(work_stack
.back());
726 design
->selection_stack
.push_back(RTLIL::Selection(false));
729 struct SelectPass
: public Pass
{
730 SelectPass() : Pass("select", "modify and view the list of selected objects") { }
733 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
735 log(" select [ -add | -del | -set <name> ] <selection>\n");
736 log(" select [ -assert-none | -assert-any ] <selection>\n");
737 log(" select [ -list | -write <filename> | -count | -clear ]\n");
738 log(" select -module <modname>\n");
740 log("Most commands use the list of currently selected objects to determine which part\n");
741 log("of the design to operate on. This command can be used to modify and view this\n");
742 log("list of selected objects.\n");
744 log("Note that many commands support an optional [selection] argument that can be\n");
745 log("used to override the global selection for the command. The syntax of this\n");
746 log("optional argument is identical to the syntax of the <selection> argument\n");
747 log("described here.\n");
749 log(" -add, -del\n");
750 log(" add or remove the given objects to the current selection.\n");
751 log(" without this options the current selection is replaced.\n");
753 log(" -set <name>\n");
754 log(" do not modify the current selection. instead save the new selection\n");
755 log(" under the given name (see @<name> below). to save the current selection,\n");
756 log(" use \"select -set <name> %%\"\n");
758 log(" -assert-none\n");
759 log(" do not modify the current selection. instead assert that the given\n");
760 log(" selection is empty. i.e. produce an error if any object matching the\n");
761 log(" selection is found.\n");
763 log(" -assert-any\n");
764 log(" do not modify the current selection. instead assert that the given\n");
765 log(" selection is non-empty. i.e. produce an error if no object matching\n");
766 log(" the selection is found.\n");
769 log(" list all objects in the current selection\n");
771 log(" -write <filename>\n");
772 log(" like -list but write the output to the specified file\n");
775 log(" count all objects in the current selection\n");
778 log(" clear the current selection. this effectively selects the whole\n");
779 log(" design. it also resets the selected module (see -module). use the\n");
780 log(" command 'select *' to select everything but stay in the current module.\n");
783 log(" create an empty selection. the current module is unchanged.\n");
785 log(" -module <modname>\n");
786 log(" limit the current scope to the specified module.\n");
787 log(" the difference between this and simply selecting the module\n");
788 log(" is that all object names are interpreted relative to this\n");
789 log(" module after this command until the selection is cleared again.\n");
791 log("When this command is called without an argument, the current selection\n");
792 log("is displayed in a compact form (i.e. only the module name when a whole module\n");
793 log("is selected).\n");
795 log("The <selection> argument itself is a series of commands for a simple stack\n");
796 log("machine. Each element on the stack represents a set of selected objects.\n");
797 log("After this commands have been executed, the union of all remaining sets\n");
798 log("on the stack is computed and used as selection for the command.\n");
800 log("Pushing (selecting) object when not in -module mode:\n");
802 log(" <mod_pattern>\n");
803 log(" select the specified module(s)\n");
805 log(" <mod_pattern>/<obj_pattern>\n");
806 log(" select the specified object(s) from the module(s)\n");
808 log("Pushing (selecting) object when in -module mode:\n");
810 log(" <obj_pattern>\n");
811 log(" select the specified object(s) from the current module\n");
813 log("A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])\n");
814 log("matching module names, or one of the following:\n");
816 log(" A:<pattern>, A:<pattern>=<pattern>\n");
817 log(" all modules with an attribute matching the given pattern\n");
818 log(" in addition to = also <, <=, >=, and > are supported\n");
820 log("An <obj_pattern> can be an object name, wildcard expression, or one of\n");
821 log("the following:\n");
823 log(" w:<pattern>\n");
824 log(" all wires with a name matching the given wildcard pattern\n");
826 log(" m:<pattern>\n");
827 log(" all memories with a name matching the given pattern\n");
829 log(" c:<pattern>\n");
830 log(" all cells with a name matching the given pattern\n");
832 log(" t:<pattern>\n");
833 log(" all cells with a type matching the given pattern\n");
835 log(" p:<pattern>\n");
836 log(" all processes with a name matching the given pattern\n");
838 log(" a:<pattern>\n");
839 log(" all objects with an attribute name matching the given pattern\n");
841 log(" a:<pattern>=<pattern>\n");
842 log(" all objects with a matching attribute name-value-pair.\n");
843 log(" in addition to = also <, <=, >=, and > are supported\n");
845 log(" r:<pattern>, r:<pattern>=<pattern>\n");
846 log(" cells with matching parameters. also with <, <=, >= and >.\n");
848 log(" n:<pattern>\n");
849 log(" all objects with a name matching the given pattern\n");
850 log(" (i.e. 'n:' is optional as it is the default matching rule)\n");
853 log(" push the selection saved prior with 'select -set <name> ...'\n");
855 log("The following actions can be performed on the top sets on the stack:\n");
858 log(" push a copy of the current selection to the stack\n");
861 log(" replace the stack with a union of all elements on it\n");
864 log(" replace top set with its invert\n");
867 log(" replace the two top sets on the stack with their union\n");
870 log(" replace the two top sets on the stack with their intersection\n");
873 log(" pop the top set from the stack and subtract it from the new top\n");
875 log(" %%x[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
876 log(" expand top set <num1> num times according to the specified rules.\n");
877 log(" (i.e. select all cells connected to selected wires and select all\n");
878 log(" wires connected to selected cells) The rules specify which cell\n");
879 log(" ports to use for this. the syntax for a rule is a '-' for exclusion\n");
880 log(" and a '+' for inclusion, followed by an optional comma seperated\n");
881 log(" list of cell types followed by an optional comma separated list of\n");
882 log(" cell ports in square brackets. a rule can also be just a cell or wire\n");
883 log(" name that limits the expansion (is included but does not go beyond).\n");
884 log(" select at most <num2> objects. a warning message is printed when this\n");
885 log(" limit is reached. When '*' is used instead of <num1> then the process\n");
886 log(" is repeated until no further object are selected.\n");
888 log(" %%ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
889 log(" %%co[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
890 log(" simmilar to %%x, but only select input (%%ci) or output cones (%%co)\n");
893 log(" expand top set by adding all modules of instantiated cells in selected\n");
896 log("Example: the following command selects all wires that are connected to a\n");
897 log("'GATE' input of a 'SWITCH' cell:\n");
899 log(" select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n");
902 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
904 bool add_mode
= false;
905 bool del_mode
= false;
906 bool clear_mode
= false;
907 bool none_mode
= false;
908 bool list_mode
= false;
909 bool count_mode
= false;
910 bool got_module
= false;
911 bool assert_none
= false;
912 bool assert_any
= false;
913 std::string write_file
;
914 std::string set_name
;
920 for (argidx
= 1; argidx
< args
.size(); argidx
++)
922 std::string arg
= args
[argidx
];
931 if (arg
== "-assert-none") {
935 if (arg
== "-assert-any") {
939 if (arg
== "-clear") {
943 if (arg
== "-none") {
947 if (arg
== "-list") {
951 if (arg
== "-write" && argidx
+1 < args
.size()) {
952 write_file
= args
[++argidx
];
955 if (arg
== "-count") {
959 if (arg
== "-module" && argidx
+1 < args
.size()) {
960 RTLIL::IdString mod_name
= RTLIL::escape_id(args
[++argidx
]);
961 if (design
->modules
.count(mod_name
) == 0)
962 log_cmd_error("No such module: %s\n", id2cstr(mod_name
));
963 design
->selected_active_module
= mod_name
;
967 if (arg
== "-set" && argidx
+1 < args
.size()) {
968 set_name
= RTLIL::escape_id(args
[++argidx
]);
971 if (arg
.size() > 0 && arg
[0] == '-')
972 log_cmd_error("Unkown option %s.\n", arg
.c_str());
973 select_stmt(design
, arg
);
974 sel_str
+= " " + arg
;
977 if (clear_mode
&& args
.size() != 2)
978 log_cmd_error("Option -clear can not be combined with any other options.\n");
980 if (none_mode
&& args
.size() != 2)
981 log_cmd_error("Option -none can not be combined with any other options.\n");
983 if (add_mode
+ del_mode
+ assert_none
+ assert_any
> 1)
984 log_cmd_error("Options -add, -del, -assert-none or -assert-any can not be combined.\n");
986 if ((list_mode
|| !write_file
.empty() || count_mode
) && (add_mode
|| del_mode
|| assert_none
|| assert_any
))
987 log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none or -assert-any.\n");
989 if (!set_name
.empty() && (list_mode
|| !write_file
.empty() || count_mode
|| add_mode
|| del_mode
|| assert_none
|| assert_any
))
990 log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none or -assert-any.\n");
992 if (work_stack
.size() == 0 && got_module
) {
993 RTLIL::Selection sel
;
994 select_filter_active_mod(design
, sel
);
995 work_stack
.push_back(sel
);
998 while (work_stack
.size() > 1) {
999 select_op_union(design
, work_stack
.front(), work_stack
.back());
1000 work_stack
.pop_back();
1003 assert(design
->selection_stack
.size() > 0);
1006 design
->selection_stack
.back() = RTLIL::Selection(true);
1007 design
->selected_active_module
= std::string();
1012 design
->selection_stack
.back() = RTLIL::Selection(false);
1016 if (list_mode
|| count_mode
|| !write_file
.empty())
1018 #define LOG_OBJECT(...) do { if (list_mode) log(__VA_ARGS__); if (f != NULL) fprintf(f, __VA_ARGS__); total_count++; } while (0)
1019 int total_count
= 0;
1021 if (!write_file
.empty()) {
1022 f
= fopen(write_file
.c_str(), "w");
1024 log_error("Can't open '%s' for writing: %s\n", write_file
.c_str(), strerror(errno
));
1026 RTLIL::Selection
*sel
= &design
->selection_stack
.back();
1027 if (work_stack
.size() > 0)
1028 sel
= &work_stack
.back();
1029 sel
->optimize(design
);
1030 for (auto mod_it
: design
->modules
)
1032 if (sel
->selected_whole_module(mod_it
.first
) && list_mode
)
1033 log("%s\n", id2cstr(mod_it
.first
));
1034 if (sel
->selected_module(mod_it
.first
)) {
1035 for (auto &it
: mod_it
.second
->wires
)
1036 if (sel
->selected_member(mod_it
.first
, it
.first
))
1037 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
));
1038 for (auto &it
: mod_it
.second
->memories
)
1039 if (sel
->selected_member(mod_it
.first
, it
.first
))
1040 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
));
1041 for (auto &it
: mod_it
.second
->cells
)
1042 if (sel
->selected_member(mod_it
.first
, it
.first
))
1043 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
));
1044 for (auto &it
: mod_it
.second
->processes
)
1045 if (sel
->selected_member(mod_it
.first
, it
.first
))
1046 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
));
1050 log("%d objects.\n", total_count
);
1059 if (work_stack
.size() == 0)
1060 log_cmd_error("Nothing to add to selection.\n");
1061 select_op_union(design
, design
->selection_stack
.back(), work_stack
.back());
1062 design
->selection_stack
.back().optimize(design
);
1068 if (work_stack
.size() == 0)
1069 log_cmd_error("Nothing to delete from selection.\n");
1070 select_op_diff(design
, design
->selection_stack
.back(), work_stack
.back());
1071 design
->selection_stack
.back().optimize(design
);
1077 if (work_stack
.size() == 0)
1078 log_cmd_error("No selection to check.\n");
1079 if (!work_stack
.back().empty())
1080 log_error("Assertation failed: selection is not empty:%s\n", sel_str
.c_str());
1086 if (work_stack
.size() == 0)
1087 log_cmd_error("No selection to check.\n");
1088 if (work_stack
.back().empty())
1089 log_error("Assertation failed: selection is empty:%s\n", sel_str
.c_str());
1093 if (!set_name
.empty())
1095 if (work_stack
.size() == 0)
1096 design
->selection_vars
[set_name
] = RTLIL::Selection(false);
1098 design
->selection_vars
[set_name
] = work_stack
.back();
1102 if (work_stack
.size() == 0) {
1103 RTLIL::Selection
&sel
= design
->selection_stack
.back();
1104 if (sel
.full_selection
)
1106 for (auto &it
: sel
.selected_modules
)
1107 log("%s\n", id2cstr(it
));
1108 for (auto &it
: sel
.selected_members
)
1109 for (auto &it2
: it
.second
)
1110 log("%s/%s\n", id2cstr(it
.first
), id2cstr(it2
));
1114 design
->selection_stack
.back() = work_stack
.back();
1115 design
->selection_stack
.back().optimize(design
);
1119 struct CdPass
: public Pass
{
1120 CdPass() : Pass("cd", "a shortcut for 'select -module <name>'") { }
1123 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1125 log(" cd <modname>\n");
1127 log("This is just a shortcut for 'select -module <modname>'.\n");
1130 log(" cd <cellname>\n");
1132 log("When no module with the specified name is found, but there is a cell\n");
1133 log("with the specified name in the current module, then this is equivialent\n");
1134 log("to 'cd <celltype>'.\n");
1138 log("This is just a shortcut for 'select -clear'.\n");
1141 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
1143 if (args
.size() != 2)
1144 log_cmd_error("Invalid number of arguments.\n");
1146 if (args
[1] == "..") {
1147 design
->selection_stack
.back() = RTLIL::Selection(true);
1148 design
->selected_active_module
= std::string();
1152 std::string modname
= RTLIL::escape_id(args
[1]);
1154 if (design
->modules
.count(modname
) == 0 && !design
->selected_active_module
.empty()) {
1155 RTLIL::Module
*module
= NULL
;
1156 if (design
->modules
.count(design
->selected_active_module
) > 0)
1157 module
= design
->modules
.at(design
->selected_active_module
);
1158 if (module
!= NULL
&& module
->cells
.count(modname
) > 0)
1159 modname
= module
->cells
.at(modname
)->type
;
1162 if (design
->modules
.count(modname
) > 0) {
1163 design
->selected_active_module
= modname
;
1164 design
->selection_stack
.back() = RTLIL::Selection();
1165 select_filter_active_mod(design
, design
->selection_stack
.back());
1166 design
->selection_stack
.back().optimize(design
);
1170 log_cmd_error("No such module `%s' found!\n", RTLIL::id2cstr(modname
));
1174 template<typename T
>
1175 static int log_matches(const char *title
, std::string pattern
, T list
)
1177 std::vector
<std::string
> matches
;
1179 for (auto &it
: list
)
1180 if (pattern
.empty() || match_ids(it
.first
, pattern
))
1181 matches
.push_back(it
.first
);
1183 if (matches
.empty())
1186 log("\n%d %s:\n", int(matches
.size()), title
);
1187 for (auto &id
: matches
)
1188 log(" %s\n", RTLIL::id2cstr(id
));
1189 return matches
.size();
1192 struct LsPass
: public Pass
{
1193 LsPass() : Pass("ls", "list modules or objects in modules") { }
1196 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1198 log(" ls [pattern]\n");
1200 log("When no active module is selected, this prints a list of all modules.\n");
1202 log("When an active module is selected, this prints a list of objects in the module.\n");
1204 log("If a pattern is given, the objects matching the pattern are printed\n");
1206 log("Note that this command does not use the selection mechanism and always operates\n");
1207 log("on the whole design or whole active module. Use 'select -list' to show a list\n");
1208 log("of currently selected objects.\n");
1211 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
1213 std::string pattern
;
1216 if (args
.size() != 1 && args
.size() != 2)
1217 log_cmd_error("Invalid number of arguments.\n");
1218 if (args
.size() == 2)
1219 pattern
= args
.at(1);
1221 if (design
->selected_active_module
.empty())
1223 counter
+= log_matches("modules", pattern
, design
->modules
);
1226 if (design
->modules
.count(design
->selected_active_module
) > 0)
1228 RTLIL::Module
*module
= design
->modules
.at(design
->selected_active_module
);
1229 counter
+= log_matches("wires", pattern
, module
->wires
);
1230 counter
+= log_matches("memories", pattern
, module
->memories
);
1231 counter
+= log_matches("cells", pattern
, module
->cells
);
1232 counter
+= log_matches("processes", pattern
, module
->processes
);
1235 // log("\nfound %d item%s.\n", counter, counter == 1 ? "" : "s");