2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/sigtools.h"
27 PRIVATE_NAMESPACE_BEGIN
31 static std::vector
<RTLIL::Selection
> work_stack
;
33 static bool match_ids(RTLIL::IdString id
, std::string pattern
)
37 if (id
.size() > 0 && id
[0] == '\\' && id
.substr(1) == pattern
)
39 if (patmatch(pattern
.c_str(), id
.c_str()))
41 if (id
.size() > 0 && id
[0] == '\\' && patmatch(pattern
.c_str(), id
.substr(1).c_str()))
43 if (id
.size() > 0 && id
[0] == '$' && pattern
.size() > 0 && pattern
[0] == '$') {
44 const char *p
= id
.c_str();
45 const char *q
= strrchr(p
, '$');
52 static bool match_attr_val(const RTLIL::Const
&value
, std::string pattern
, char match_op
)
57 if ((value
.flags
& RTLIL::CONST_FLAG_STRING
) == 0)
59 RTLIL::SigSpec sig_value
;
61 if (!RTLIL::SigSpec::parse(sig_value
, NULL
, pattern
))
64 RTLIL::Const pattern_value
= sig_value
.as_const();
67 return value
== pattern_value
;
69 return value
!= pattern_value
;
71 return value
.as_int() < pattern_value
.as_int();
73 return value
.as_int() > pattern_value
.as_int();
75 return value
.as_int() <= pattern_value
.as_int();
77 return value
.as_int() >= pattern_value
.as_int();
81 std::string value_str
= value
.decode_string();
84 if (patmatch(pattern
.c_str(), value
.decode_string().c_str()))
88 return value_str
== pattern
;
90 return value_str
!= pattern
;
92 return value_str
< pattern
;
94 return value_str
> pattern
;
96 return value_str
<= pattern
;
98 return value_str
>= pattern
;
104 static bool match_attr(const dict
<RTLIL::IdString
, RTLIL::Const
> &attributes
, std::string name_pat
, std::string value_pat
, char match_op
)
106 if (name_pat
.find('*') != std::string::npos
|| name_pat
.find('?') != std::string::npos
|| name_pat
.find('[') != std::string::npos
) {
107 for (auto &it
: attributes
) {
108 if (patmatch(name_pat
.c_str(), it
.first
.c_str()) && match_attr_val(it
.second
, value_pat
, match_op
))
110 if (it
.first
.size() > 0 && it
.first
[0] == '\\' && patmatch(name_pat
.c_str(), it
.first
.substr(1).c_str()) && match_attr_val(it
.second
, value_pat
, match_op
))
114 if (name_pat
.size() > 0 && (name_pat
[0] == '\\' || name_pat
[0] == '$') && attributes
.count(name_pat
) && match_attr_val(attributes
.at(name_pat
), value_pat
, match_op
))
116 if (attributes
.count("\\" + name_pat
) && match_attr_val(attributes
.at("\\" + name_pat
), value_pat
, match_op
))
122 static bool match_attr(const dict
<RTLIL::IdString
, RTLIL::Const
> &attributes
, std::string match_expr
)
124 size_t pos
= match_expr
.find_first_of("<!=>");
126 if (pos
!= std::string::npos
) {
127 if (match_expr
.substr(pos
, 2) == "!=")
128 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), '!');
129 if (match_expr
.substr(pos
, 2) == "<=")
130 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), '[');
131 if (match_expr
.substr(pos
, 2) == ">=")
132 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+2), ']');
133 return match_attr(attributes
, match_expr
.substr(0, pos
), match_expr
.substr(pos
+1), match_expr
[pos
]);
136 return match_attr(attributes
, match_expr
, std::string(), 0);
139 static void select_op_neg(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
141 if (lhs
.full_selection
) {
142 lhs
.full_selection
= false;
143 lhs
.selected_modules
.clear();
144 lhs
.selected_members
.clear();
148 if (lhs
.selected_modules
.size() == 0 && lhs
.selected_members
.size() == 0) {
149 lhs
.full_selection
= true;
153 RTLIL::Selection
new_sel(false);
155 for (auto &mod_it
: design
->modules_
)
157 if (lhs
.selected_whole_module(mod_it
.first
))
159 if (!lhs
.selected_module(mod_it
.first
)) {
160 new_sel
.selected_modules
.insert(mod_it
.first
);
164 RTLIL::Module
*mod
= mod_it
.second
;
165 for (auto &it
: mod
->wires_
)
166 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
167 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
168 for (auto &it
: mod
->memories
)
169 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
170 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
171 for (auto &it
: mod
->cells_
)
172 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
173 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
174 for (auto &it
: mod
->processes
)
175 if (!lhs
.selected_member(mod_it
.first
, it
.first
))
176 new_sel
.selected_members
[mod
->name
].insert(it
.first
);
179 lhs
.selected_modules
.swap(new_sel
.selected_modules
);
180 lhs
.selected_members
.swap(new_sel
.selected_members
);
183 static void select_op_submod(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
185 for (auto &mod_it
: design
->modules_
)
187 if (lhs
.selected_whole_module(mod_it
.first
))
189 for (auto &cell_it
: mod_it
.second
->cells_
)
191 if (design
->modules_
.count(cell_it
.second
->type
) == 0)
193 lhs
.selected_modules
.insert(cell_it
.second
->type
);
199 static void select_op_fullmod(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
201 lhs
.optimize(design
);
202 for (auto &it
: lhs
.selected_members
)
203 lhs
.selected_modules
.insert(it
.first
);
204 lhs
.selected_members
.clear();
207 static void select_op_alias(RTLIL::Design
*design
, RTLIL::Selection
&lhs
)
209 for (auto &mod_it
: design
->modules_
)
211 if (lhs
.selected_whole_module(mod_it
.first
))
213 if (!lhs
.selected_module(mod_it
.first
))
216 SigMap
sigmap(mod_it
.second
);
217 SigPool selected_bits
;
219 for (auto &it
: mod_it
.second
->wires_
)
220 if (lhs
.selected_member(mod_it
.first
, it
.first
))
221 selected_bits
.add(sigmap(it
.second
));
223 for (auto &it
: mod_it
.second
->wires_
)
224 if (!lhs
.selected_member(mod_it
.first
, it
.first
) && selected_bits
.check_any(sigmap(it
.second
)))
225 lhs
.selected_members
[mod_it
.first
].insert(it
.first
);
229 static void select_op_union(RTLIL::Design
*, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
231 if (rhs
.full_selection
) {
232 lhs
.full_selection
= true;
233 lhs
.selected_modules
.clear();
234 lhs
.selected_members
.clear();
238 if (lhs
.full_selection
)
241 for (auto &it
: rhs
.selected_members
)
242 for (auto &it2
: it
.second
)
243 lhs
.selected_members
[it
.first
].insert(it2
);
245 for (auto &it
: rhs
.selected_modules
) {
246 lhs
.selected_modules
.insert(it
);
247 lhs
.selected_members
.erase(it
);
251 static void select_op_diff(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
253 if (rhs
.full_selection
) {
254 lhs
.full_selection
= false;
255 lhs
.selected_modules
.clear();
256 lhs
.selected_members
.clear();
260 if (lhs
.full_selection
) {
261 if (!rhs
.full_selection
&& rhs
.selected_modules
.size() == 0 && rhs
.selected_members
.size() == 0)
263 lhs
.full_selection
= false;
264 for (auto &it
: design
->modules_
)
265 lhs
.selected_modules
.insert(it
.first
);
268 for (auto &it
: rhs
.selected_modules
) {
269 lhs
.selected_modules
.erase(it
);
270 lhs
.selected_members
.erase(it
);
273 for (auto &it
: rhs
.selected_members
)
275 if (design
->modules_
.count(it
.first
) == 0)
278 RTLIL::Module
*mod
= design
->modules_
[it
.first
];
280 if (lhs
.selected_modules
.count(mod
->name
) > 0)
282 for (auto &it
: mod
->wires_
)
283 lhs
.selected_members
[mod
->name
].insert(it
.first
);
284 for (auto &it
: mod
->memories
)
285 lhs
.selected_members
[mod
->name
].insert(it
.first
);
286 for (auto &it
: mod
->cells_
)
287 lhs
.selected_members
[mod
->name
].insert(it
.first
);
288 for (auto &it
: mod
->processes
)
289 lhs
.selected_members
[mod
->name
].insert(it
.first
);
290 lhs
.selected_modules
.erase(mod
->name
);
293 if (lhs
.selected_members
.count(mod
->name
) == 0)
296 for (auto &it2
: it
.second
)
297 lhs
.selected_members
[mod
->name
].erase(it2
);
301 static void select_op_intersect(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, const RTLIL::Selection
&rhs
)
303 if (rhs
.full_selection
)
306 if (lhs
.full_selection
) {
307 lhs
.full_selection
= false;
308 for (auto &it
: design
->modules_
)
309 lhs
.selected_modules
.insert(it
.first
);
312 std::vector
<RTLIL::IdString
> del_list
;
314 for (auto &it
: lhs
.selected_modules
)
315 if (rhs
.selected_modules
.count(it
) == 0) {
316 if (rhs
.selected_members
.count(it
) > 0)
317 for (auto &it2
: rhs
.selected_members
.at(it
))
318 lhs
.selected_members
[it
].insert(it2
);
319 del_list
.push_back(it
);
321 for (auto &it
: del_list
)
322 lhs
.selected_modules
.erase(it
);
325 for (auto &it
: lhs
.selected_members
) {
326 if (rhs
.selected_modules
.count(it
.first
) > 0)
328 if (rhs
.selected_members
.count(it
.first
) == 0) {
329 del_list
.push_back(it
.first
);
332 std::vector
<RTLIL::IdString
> del_list2
;
333 for (auto &it2
: it
.second
)
334 if (rhs
.selected_members
.at(it
.first
).count(it2
) == 0)
335 del_list2
.push_back(it2
);
336 for (auto &it2
: del_list2
)
337 it
.second
.erase(it2
);
338 if (it
.second
.size() == 0)
339 del_list
.push_back(it
.first
);
341 for (auto &it
: del_list
)
342 lhs
.selected_members
.erase(it
);
346 struct expand_rule_t
{
348 std::set
<RTLIL::IdString
> cell_types
, port_names
;
352 static int parse_comma_list(std::set
<RTLIL::IdString
> &tokens
, std::string str
, size_t pos
, std::string stopchar
)
356 size_t endpos
= str
.find_first_of(stopchar
, pos
);
357 if (endpos
== std::string::npos
)
360 tokens
.insert(RTLIL::escape_id(str
.substr(pos
, endpos
-pos
)));
362 if (pos
== str
.size() || str
[pos
] != ',')
368 static int select_op_expand(RTLIL::Design
*design
, RTLIL::Selection
&lhs
, std::vector
<expand_rule_t
> &rules
, std::set
<RTLIL::IdString
> &limits
, int max_objects
, char mode
, CellTypes
&ct
, bool eval_only
)
371 bool is_input
, is_output
;
372 for (auto &mod_it
: design
->modules_
)
374 if (lhs
.selected_whole_module(mod_it
.first
) || !lhs
.selected_module(mod_it
.first
))
377 RTLIL::Module
*mod
= mod_it
.second
;
378 std::set
<RTLIL::Wire
*> selected_wires
;
379 auto selected_members
= lhs
.selected_members
[mod
->name
];
381 for (auto &it
: mod
->wires_
)
382 if (lhs
.selected_member(mod_it
.first
, it
.first
) && limits
.count(it
.first
) == 0)
383 selected_wires
.insert(it
.second
);
385 for (auto &conn
: mod
->connections())
387 std::vector
<RTLIL::SigBit
> conn_lhs
= conn
.first
.to_sigbit_vector();
388 std::vector
<RTLIL::SigBit
> conn_rhs
= conn
.second
.to_sigbit_vector();
390 for (size_t i
= 0; i
< conn_lhs
.size(); i
++) {
391 if (conn_lhs
[i
].wire
== NULL
|| conn_rhs
[i
].wire
== NULL
)
393 if (mode
!= 'i' && selected_wires
.count(conn_rhs
[i
].wire
) && selected_members
.count(conn_lhs
[i
].wire
->name
) == 0)
394 lhs
.selected_members
[mod
->name
].insert(conn_lhs
[i
].wire
->name
), sel_objects
++, max_objects
--;
395 if (mode
!= 'o' && selected_wires
.count(conn_lhs
[i
].wire
) && selected_members
.count(conn_rhs
[i
].wire
->name
) == 0)
396 lhs
.selected_members
[mod
->name
].insert(conn_rhs
[i
].wire
->name
), sel_objects
++, max_objects
--;
400 for (auto &cell
: mod
->cells_
)
401 for (auto &conn
: cell
.second
->connections())
403 char last_mode
= '-';
404 if (eval_only
&& !yosys_celltypes
.cell_evaluable(cell
.second
->type
))
406 for (auto &rule
: rules
) {
407 last_mode
= rule
.mode
;
408 if (rule
.cell_types
.size() > 0 && rule
.cell_types
.count(cell
.second
->type
) == 0)
410 if (rule
.port_names
.size() > 0 && rule
.port_names
.count(conn
.first
) == 0)
412 if (rule
.mode
== '+')
417 if (last_mode
== '+')
420 is_input
= mode
== 'x' || ct
.cell_input(cell
.second
->type
, conn
.first
);
421 is_output
= mode
== 'x' || ct
.cell_output(cell
.second
->type
, conn
.first
);
422 for (auto &chunk
: conn
.second
.chunks())
423 if (chunk
.wire
!= NULL
) {
424 if (max_objects
!= 0 && selected_wires
.count(chunk
.wire
) > 0 && selected_members
.count(cell
.first
) == 0)
425 if (mode
== 'x' || (mode
== 'i' && is_output
) || (mode
== 'o' && is_input
))
426 lhs
.selected_members
[mod
->name
].insert(cell
.first
), sel_objects
++, max_objects
--;
427 if (max_objects
!= 0 && selected_members
.count(cell
.first
) > 0 && limits
.count(cell
.first
) == 0 && selected_members
.count(chunk
.wire
->name
) == 0)
428 if (mode
== 'x' || (mode
== 'i' && is_input
) || (mode
== 'o' && is_output
))
429 lhs
.selected_members
[mod
->name
].insert(chunk
.wire
->name
), sel_objects
++, max_objects
--;
438 static void select_op_expand(RTLIL::Design
*design
, std::string arg
, char mode
, bool eval_only
)
440 int pos
= (mode
== 'x' ? 2 : 3) + (eval_only
? 1 : 0);
441 int levels
= 1, rem_objects
= -1;
442 std::vector
<expand_rule_t
> rules
;
443 std::set
<RTLIL::IdString
> limits
;
450 if (pos
< int(arg
.size()) && arg
[pos
] == '*') {
454 if (pos
< int(arg
.size()) && '0' <= arg
[pos
] && arg
[pos
] <= '9') {
455 size_t endpos
= arg
.find_first_not_of("0123456789", pos
);
456 if (endpos
== std::string::npos
)
458 levels
= atoi(arg
.substr(pos
, endpos
-pos
).c_str());
462 if (pos
< int(arg
.size()) && arg
[pos
] == '.') {
463 size_t endpos
= arg
.find_first_not_of("0123456789", ++pos
);
464 if (endpos
== std::string::npos
)
466 if (int(endpos
) > pos
)
467 rem_objects
= atoi(arg
.substr(pos
, endpos
-pos
).c_str());
471 while (pos
< int(arg
.size())) {
472 if (arg
[pos
] != ':' || pos
+1 == int(arg
.size()))
473 log_cmd_error("Syntax error in expand operator '%s'.\n", arg
.c_str());
475 if (arg
[pos
] == '+' || arg
[pos
] == '-') {
477 rule
.mode
= arg
[pos
++];
478 pos
= parse_comma_list(rule
.cell_types
, arg
, pos
, "[:");
479 if (pos
< int(arg
.size()) && arg
[pos
] == '[') {
480 pos
= parse_comma_list(rule
.port_names
, arg
, pos
+1, "]:");
481 if (pos
< int(arg
.size()) && arg
[pos
] == ']')
484 rules
.push_back(rule
);
486 size_t endpos
= arg
.find(':', pos
);
487 if (endpos
== std::string::npos
)
489 if (int(endpos
) > pos
) {
490 std::string str
= arg
.substr(pos
, endpos
-pos
);
492 str
= RTLIL::escape_id(str
.substr(1));
493 if (design
->selection_vars
.count(str
) > 0) {
494 for (auto i1
: design
->selection_vars
.at(str
).selected_members
)
495 for (auto i2
: i1
.second
)
498 log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str
).c_str());
500 limits
.insert(RTLIL::escape_id(str
));
507 log("expand by %d levels (max. %d objects):\n", levels
, rem_objects
);
508 for (auto &rule
: rules
) {
509 log(" rule (%c):\n", rule
.mode
);
510 if (rule
.cell_types
.size() > 0) {
512 for (auto &it
: rule
.cell_types
)
513 log(" %s", it
.c_str());
516 if (rule
.port_names
.size() > 0) {
518 for (auto &it
: rule
.port_names
)
519 log(" %s", it
.c_str());
523 if (limits
.size() > 0) {
525 for (auto &it
: limits
)
526 log(" %s", it
.c_str());
531 while (levels
-- > 0 && rem_objects
!= 0) {
532 int num_objects
= select_op_expand(design
, work_stack
.back(), rules
, limits
, rem_objects
, mode
, ct
, eval_only
);
533 if (num_objects
== 0)
535 rem_objects
-= num_objects
;
538 if (rem_objects
== 0)
539 log_warning("reached configured limit at `%s'.\n", arg
.c_str());
542 static void select_filter_active_mod(RTLIL::Design
*design
, RTLIL::Selection
&sel
)
544 if (design
->selected_active_module
.empty())
547 if (sel
.full_selection
) {
548 sel
.full_selection
= false;
549 sel
.selected_modules
.clear();
550 sel
.selected_members
.clear();
551 sel
.selected_modules
.insert(design
->selected_active_module
);
555 std::vector
<RTLIL::IdString
> del_list
;
556 for (auto mod_name
: sel
.selected_modules
)
557 if (mod_name
!= design
->selected_active_module
)
558 del_list
.push_back(mod_name
);
559 for (auto &it
: sel
.selected_members
)
560 if (it
.first
!= design
->selected_active_module
)
561 del_list
.push_back(it
.first
);
562 for (auto mod_name
: del_list
) {
563 sel
.selected_modules
.erase(mod_name
);
564 sel
.selected_members
.erase(mod_name
);
568 static void select_stmt(RTLIL::Design
*design
, std::string arg
)
570 std::string arg_mod
, arg_memb
;
577 if (design
->selection_stack
.size() > 0)
578 work_stack
.push_back(design
->selection_stack
.back());
581 while (work_stack
.size() > 1) {
582 select_op_union(design
, work_stack
.front(), work_stack
.back());
583 work_stack
.pop_back();
587 if (work_stack
.size() < 1)
588 log_cmd_error("Must have at least one element on the stack for operator %%n.\n");
589 select_op_neg(design
, work_stack
[work_stack
.size()-1]);
592 if (work_stack
.size() < 2)
593 log_cmd_error("Must have at least two elements on the stack for operator %%u.\n");
594 select_op_union(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
595 work_stack
.pop_back();
598 if (work_stack
.size() < 2)
599 log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
600 select_op_diff(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
601 work_stack
.pop_back();
604 if (work_stack
.size() < 2)
605 log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
606 select_op_diff(design
, work_stack
[work_stack
.size()-1], work_stack
[work_stack
.size()-2]);
607 work_stack
[work_stack
.size()-2] = work_stack
[work_stack
.size()-1];
608 work_stack
.pop_back();
611 if (work_stack
.size() < 2)
612 log_cmd_error("Must have at least two elements on the stack for operator %%i.\n");
613 select_op_intersect(design
, work_stack
[work_stack
.size()-2], work_stack
[work_stack
.size()-1]);
614 work_stack
.pop_back();
617 if (work_stack
.size() < 1)
618 log_cmd_error("Must have at least one element on the stack for operator %%s.\n");
619 select_op_submod(design
, work_stack
[work_stack
.size()-1]);
622 if (work_stack
.size() < 1)
623 log_cmd_error("Must have at least one element on the stack for operator %%c.\n");
624 work_stack
.push_back(work_stack
.back());
627 if (work_stack
.size() < 1)
628 log_cmd_error("Must have at least one element on the stack for operator %%m.\n");
629 select_op_fullmod(design
, work_stack
[work_stack
.size()-1]);
632 if (work_stack
.size() < 1)
633 log_cmd_error("Must have at least one element on the stack for operator %%a.\n");
634 select_op_alias(design
, work_stack
[work_stack
.size()-1]);
636 if (arg
== "%x" || (arg
.size() > 2 && arg
.substr(0, 2) == "%x" && (arg
[2] == ':' || arg
[2] == '*' || arg
[2] == '.' || ('0' <= arg
[2] && arg
[2] <= '9')))) {
637 if (work_stack
.size() < 1)
638 log_cmd_error("Must have at least one element on the stack for operator %%x.\n");
639 select_op_expand(design
, arg
, 'x', false);
641 if (arg
== "%ci" || (arg
.size() > 3 && arg
.substr(0, 3) == "%ci" && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
642 if (work_stack
.size() < 1)
643 log_cmd_error("Must have at least one element on the stack for operator %%ci.\n");
644 select_op_expand(design
, arg
, 'i', false);
646 if (arg
== "%co" || (arg
.size() > 3 && arg
.substr(0, 3) == "%co" && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
647 if (work_stack
.size() < 1)
648 log_cmd_error("Must have at least one element on the stack for operator %%co.\n");
649 select_op_expand(design
, arg
, 'o', false);
651 if (arg
== "%xe" || (arg
.size() > 3 && arg
.substr(0, 3) == "%x" && (arg
[3] == ':' || arg
[3] == '*' || arg
[3] == '.' || ('0' <= arg
[3] && arg
[3] <= '9')))) {
652 if (work_stack
.size() < 1)
653 log_cmd_error("Must have at least one element on the stack for operator %%xe.\n");
654 select_op_expand(design
, arg
, 'x', true);
656 if (arg
== "%cie" || (arg
.size() > 4 && arg
.substr(0, 4) == "%cie" && (arg
[4] == ':' || arg
[4] == '*' || arg
[4] == '.' || ('0' <= arg
[4] && arg
[4] <= '9')))) {
657 if (work_stack
.size() < 1)
658 log_cmd_error("Must have at least one element on the stack for operator %%cie.\n");
659 select_op_expand(design
, arg
, 'i', true);
661 if (arg
== "%coe" || (arg
.size() > 4 && arg
.substr(0, 4) == "%coe" && (arg
[4] == ':' || arg
[4] == '*' || arg
[4] == '.' || ('0' <= arg
[4] && arg
[4] <= '9')))) {
662 if (work_stack
.size() < 1)
663 log_cmd_error("Must have at least one element on the stack for operator %%coe.\n");
664 select_op_expand(design
, arg
, 'o', true);
666 log_cmd_error("Unknown selection operator '%s'.\n", arg
.c_str());
667 if (work_stack
.size() >= 1)
668 select_filter_active_mod(design
, work_stack
.back());
673 std::string set_name
= RTLIL::escape_id(arg
.substr(1));
674 if (design
->selection_vars
.count(set_name
) > 0)
675 work_stack
.push_back(design
->selection_vars
[set_name
]);
677 log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name
).c_str());
678 select_filter_active_mod(design
, work_stack
.back());
682 if (!design
->selected_active_module
.empty()) {
683 arg_mod
= design
->selected_active_module
;
686 size_t pos
= arg
.find('/');
687 if (pos
== std::string::npos
) {
688 if (arg
.find(':') == std::string::npos
|| arg
.substr(0, 1) == "A")
691 arg_mod
= "*", arg_memb
= arg
;
693 arg_mod
= arg
.substr(0, pos
);
694 arg_memb
= arg
.substr(pos
+1);
698 work_stack
.push_back(RTLIL::Selection());
699 RTLIL::Selection
&sel
= work_stack
.back();
701 if (arg
== "*" && arg_mod
== "*") {
702 select_filter_active_mod(design
, work_stack
.back());
706 sel
.full_selection
= false;
707 for (auto &mod_it
: design
->modules_
)
709 if (arg_mod
.substr(0, 2) == "A:") {
710 if (!match_attr(mod_it
.second
->attributes
, arg_mod
.substr(2)))
713 if (!match_ids(mod_it
.first
, arg_mod
))
716 if (arg_memb
== "") {
717 sel
.selected_modules
.insert(mod_it
.first
);
721 RTLIL::Module
*mod
= mod_it
.second
;
722 if (arg_memb
.substr(0, 2) == "w:") {
723 for (auto &it
: mod
->wires_
)
724 if (match_ids(it
.first
, arg_memb
.substr(2)))
725 sel
.selected_members
[mod
->name
].insert(it
.first
);
727 if (arg_memb
.substr(0, 2) == "i:") {
728 for (auto &it
: mod
->wires_
)
729 if (it
.second
->port_input
&& match_ids(it
.first
, arg_memb
.substr(2)))
730 sel
.selected_members
[mod
->name
].insert(it
.first
);
732 if (arg_memb
.substr(0, 2) == "o:") {
733 for (auto &it
: mod
->wires_
)
734 if (it
.second
->port_output
&& match_ids(it
.first
, arg_memb
.substr(2)))
735 sel
.selected_members
[mod
->name
].insert(it
.first
);
737 if (arg_memb
.substr(0, 2) == "x:") {
738 for (auto &it
: mod
->wires_
)
739 if ((it
.second
->port_input
|| it
.second
->port_output
) && match_ids(it
.first
, arg_memb
.substr(2)))
740 sel
.selected_members
[mod
->name
].insert(it
.first
);
742 if (arg_memb
.substr(0, 2) == "s:") {
743 size_t delim
= arg_memb
.substr(2).find(':');
744 if (delim
== std::string::npos
) {
745 int width
= atoi(arg_memb
.substr(2).c_str());
746 for (auto &it
: mod
->wires_
)
747 if (it
.second
->width
== width
)
748 sel
.selected_members
[mod
->name
].insert(it
.first
);
750 std::string min_str
= arg_memb
.substr(2, delim
);
751 std::string max_str
= arg_memb
.substr(2+delim
+1);
752 int min_width
= min_str
.empty() ? 0 : atoi(min_str
.c_str());
753 int max_width
= max_str
.empty() ? -1 : atoi(max_str
.c_str());
754 for (auto &it
: mod
->wires_
)
755 if (min_width
<= it
.second
->width
&& (it
.second
->width
<= max_width
|| max_width
== -1))
756 sel
.selected_members
[mod
->name
].insert(it
.first
);
759 if (arg_memb
.substr(0, 2) == "m:") {
760 for (auto &it
: mod
->memories
)
761 if (match_ids(it
.first
, arg_memb
.substr(2)))
762 sel
.selected_members
[mod
->name
].insert(it
.first
);
764 if (arg_memb
.substr(0, 2) == "c:") {
765 for (auto &it
: mod
->cells_
)
766 if (match_ids(it
.first
, arg_memb
.substr(2)))
767 sel
.selected_members
[mod
->name
].insert(it
.first
);
769 if (arg_memb
.substr(0, 2) == "t:") {
770 for (auto &it
: mod
->cells_
)
771 if (match_ids(it
.second
->type
, arg_memb
.substr(2)))
772 sel
.selected_members
[mod
->name
].insert(it
.first
);
774 if (arg_memb
.substr(0, 2) == "p:") {
775 for (auto &it
: mod
->processes
)
776 if (match_ids(it
.first
, arg_memb
.substr(2)))
777 sel
.selected_members
[mod
->name
].insert(it
.first
);
779 if (arg_memb
.substr(0, 2) == "a:") {
780 for (auto &it
: mod
->wires_
)
781 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
782 sel
.selected_members
[mod
->name
].insert(it
.first
);
783 for (auto &it
: mod
->memories
)
784 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
785 sel
.selected_members
[mod
->name
].insert(it
.first
);
786 for (auto &it
: mod
->cells_
)
787 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
788 sel
.selected_members
[mod
->name
].insert(it
.first
);
789 for (auto &it
: mod
->processes
)
790 if (match_attr(it
.second
->attributes
, arg_memb
.substr(2)))
791 sel
.selected_members
[mod
->name
].insert(it
.first
);
793 if (arg_memb
.substr(0, 2) == "r:") {
794 for (auto &it
: mod
->cells_
)
795 if (match_attr(it
.second
->parameters
, arg_memb
.substr(2)))
796 sel
.selected_members
[mod
->name
].insert(it
.first
);
798 if (arg_memb
.substr(0, 2) == "n:")
799 arg_memb
= arg_memb
.substr(2);
800 for (auto &it
: mod
->wires_
)
801 if (match_ids(it
.first
, arg_memb
))
802 sel
.selected_members
[mod
->name
].insert(it
.first
);
803 for (auto &it
: mod
->memories
)
804 if (match_ids(it
.first
, arg_memb
))
805 sel
.selected_members
[mod
->name
].insert(it
.first
);
806 for (auto &it
: mod
->cells_
)
807 if (match_ids(it
.first
, arg_memb
))
808 sel
.selected_members
[mod
->name
].insert(it
.first
);
809 for (auto &it
: mod
->processes
)
810 if (match_ids(it
.first
, arg_memb
))
811 sel
.selected_members
[mod
->name
].insert(it
.first
);
815 select_filter_active_mod(design
, work_stack
.back());
818 PRIVATE_NAMESPACE_END
819 YOSYS_NAMESPACE_BEGIN
821 // used in kernel/register.cc and maybe other locations, extern decl. in register.h
822 void handle_extra_select_args(Pass
*pass
, vector
<string
> args
, size_t argidx
, size_t args_size
, RTLIL::Design
*design
)
825 for (; argidx
< args_size
; argidx
++) {
826 if (args
[argidx
].substr(0, 1) == "-") {
828 pass
->cmd_error(args
, argidx
, "Unexpected option in selection arguments.");
830 log_cmd_error("Unexpected option in selection arguments.");
832 select_stmt(design
, args
[argidx
]);
834 while (work_stack
.size() > 1) {
835 select_op_union(design
, work_stack
.front(), work_stack
.back());
836 work_stack
.pop_back();
838 if (work_stack
.empty())
839 design
->selection_stack
.push_back(RTLIL::Selection(false));
841 design
->selection_stack
.push_back(work_stack
.back());
844 // extern decl. in register.h
845 RTLIL::Selection
eval_select_args(const vector
<string
> &args
, RTLIL::Design
*design
)
848 for (auto &arg
: args
)
849 select_stmt(design
, arg
);
850 while (work_stack
.size() > 1) {
851 select_op_union(design
, work_stack
.front(), work_stack
.back());
852 work_stack
.pop_back();
854 if (work_stack
.empty())
855 return RTLIL::Selection(false);
856 return work_stack
.back();
859 // extern decl. in register.h
860 void eval_select_op(vector
<RTLIL::Selection
> &work
, const string
&op
, RTLIL::Design
*design
)
862 work_stack
.swap(work
);
863 select_stmt(design
, op
);
864 work_stack
.swap(work
);
868 PRIVATE_NAMESPACE_BEGIN
870 struct SelectPass
: public Pass
{
871 SelectPass() : Pass("select", "modify and view the list of selected objects") { }
874 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
876 log(" select [ -add | -del | -set <name> ] {-read <filename> | <selection>}\n");
877 log(" select [ -assert-none | -assert-any ] {-read <filename> | <selection>}\n");
878 log(" select [ -list | -write <filename> | -count | -clear ]\n");
879 log(" select -module <modname>\n");
881 log("Most commands use the list of currently selected objects to determine which part\n");
882 log("of the design to operate on. This command can be used to modify and view this\n");
883 log("list of selected objects.\n");
885 log("Note that many commands support an optional [selection] argument that can be\n");
886 log("used to override the global selection for the command. The syntax of this\n");
887 log("optional argument is identical to the syntax of the <selection> argument\n");
888 log("described here.\n");
890 log(" -add, -del\n");
891 log(" add or remove the given objects to the current selection.\n");
892 log(" without this options the current selection is replaced.\n");
894 log(" -set <name>\n");
895 log(" do not modify the current selection. instead save the new selection\n");
896 log(" under the given name (see @<name> below). to save the current selection,\n");
897 log(" use \"select -set <name> %%\"\n");
899 log(" -assert-none\n");
900 log(" do not modify the current selection. instead assert that the given\n");
901 log(" selection is empty. i.e. produce an error if any object matching the\n");
902 log(" selection is found.\n");
904 log(" -assert-any\n");
905 log(" do not modify the current selection. instead assert that the given\n");
906 log(" selection is non-empty. i.e. produce an error if no object matching\n");
907 log(" the selection is found.\n");
909 log(" -assert-count N\n");
910 log(" do not modify the current selection. instead assert that the given\n");
911 log(" selection contains exactly N objects.\n");
914 log(" list all objects in the current selection\n");
916 log(" -write <filename>\n");
917 log(" like -list but write the output to the specified file\n");
919 log(" -read <filename>\n");
920 log(" read the specified file (written by -write)\n");
923 log(" count all objects in the current selection\n");
926 log(" clear the current selection. this effectively selects the whole\n");
927 log(" design. it also resets the selected module (see -module). use the\n");
928 log(" command 'select *' to select everything but stay in the current module.\n");
931 log(" create an empty selection. the current module is unchanged.\n");
933 log(" -module <modname>\n");
934 log(" limit the current scope to the specified module.\n");
935 log(" the difference between this and simply selecting the module\n");
936 log(" is that all object names are interpreted relative to this\n");
937 log(" module after this command until the selection is cleared again.\n");
939 log("When this command is called without an argument, the current selection\n");
940 log("is displayed in a compact form (i.e. only the module name when a whole module\n");
941 log("is selected).\n");
943 log("The <selection> argument itself is a series of commands for a simple stack\n");
944 log("machine. Each element on the stack represents a set of selected objects.\n");
945 log("After this commands have been executed, the union of all remaining sets\n");
946 log("on the stack is computed and used as selection for the command.\n");
948 log("Pushing (selecting) object when not in -module mode:\n");
950 log(" <mod_pattern>\n");
951 log(" select the specified module(s)\n");
953 log(" <mod_pattern>/<obj_pattern>\n");
954 log(" select the specified object(s) from the module(s)\n");
956 log("Pushing (selecting) object when in -module mode:\n");
958 log(" <obj_pattern>\n");
959 log(" select the specified object(s) from the current module\n");
961 log("A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])\n");
962 log("matching module names, or one of the following:\n");
964 log(" A:<pattern>, A:<pattern>=<pattern>\n");
965 log(" all modules with an attribute matching the given pattern\n");
966 log(" in addition to = also <, <=, >=, and > are supported\n");
968 log("An <obj_pattern> can be an object name, wildcard expression, or one of\n");
969 log("the following:\n");
971 log(" w:<pattern>\n");
972 log(" all wires with a name matching the given wildcard pattern\n");
974 log(" i:<pattern>, o:<pattern>, x:<pattern>\n");
975 log(" all inputs (i:), outputs (o:) or any ports (x:) with matching names\n");
977 log(" s:<size>, s:<min>:<max>\n");
978 log(" all wires with a matching width\n");
980 log(" m:<pattern>\n");
981 log(" all memories with a name matching the given pattern\n");
983 log(" c:<pattern>\n");
984 log(" all cells with a name matching the given pattern\n");
986 log(" t:<pattern>\n");
987 log(" all cells with a type matching the given pattern\n");
989 log(" p:<pattern>\n");
990 log(" all processes with a name matching the given pattern\n");
992 log(" a:<pattern>\n");
993 log(" all objects with an attribute name matching the given pattern\n");
995 log(" a:<pattern>=<pattern>\n");
996 log(" all objects with a matching attribute name-value-pair.\n");
997 log(" in addition to = also <, <=, >=, and > are supported\n");
999 log(" r:<pattern>, r:<pattern>=<pattern>\n");
1000 log(" cells with matching parameters. also with <, <=, >= and >.\n");
1002 log(" n:<pattern>\n");
1003 log(" all objects with a name matching the given pattern\n");
1004 log(" (i.e. 'n:' is optional as it is the default matching rule)\n");
1007 log(" push the selection saved prior with 'select -set <name> ...'\n");
1009 log("The following actions can be performed on the top sets on the stack:\n");
1012 log(" push a copy of the current selection to the stack\n");
1015 log(" replace the stack with a union of all elements on it\n");
1018 log(" replace top set with its invert\n");
1021 log(" replace the two top sets on the stack with their union\n");
1024 log(" replace the two top sets on the stack with their intersection\n");
1027 log(" pop the top set from the stack and subtract it from the new top\n");
1030 log(" like %%d but swap the roles of two top sets on the stack\n");
1033 log(" create a copy of the top set rom the stack and push it\n");
1035 log(" %%x[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
1036 log(" expand top set <num1> num times according to the specified rules.\n");
1037 log(" (i.e. select all cells connected to selected wires and select all\n");
1038 log(" wires connected to selected cells) The rules specify which cell\n");
1039 log(" ports to use for this. the syntax for a rule is a '-' for exclusion\n");
1040 log(" and a '+' for inclusion, followed by an optional comma separated\n");
1041 log(" list of cell types followed by an optional comma separated list of\n");
1042 log(" cell ports in square brackets. a rule can also be just a cell or wire\n");
1043 log(" name that limits the expansion (is included but does not go beyond).\n");
1044 log(" select at most <num2> objects. a warning message is printed when this\n");
1045 log(" limit is reached. When '*' is used instead of <num1> then the process\n");
1046 log(" is repeated until no further object are selected.\n");
1048 log(" %%ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
1049 log(" %%co[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
1050 log(" simmilar to %%x, but only select input (%%ci) or output cones (%%co)\n");
1052 log(" %%xe[...] %%cie[...] %%coe\n");
1053 log(" like %%x, %%ci, and %%co but only consider combinatorial cells\n");
1056 log(" expand top set by selecting all wires that are (at least in part)\n");
1057 log(" aliases for selected wires.\n");
1060 log(" expand top set by adding all modules of instantiated cells in selected\n");
1064 log(" expand top set by selecting all modules that contain selected objects\n");
1066 log("Example: the following command selects all wires that are connected to a\n");
1067 log("'GATE' input of a 'SWITCH' cell:\n");
1069 log(" select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n");
1072 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
1074 bool add_mode
= false;
1075 bool del_mode
= false;
1076 bool clear_mode
= false;
1077 bool none_mode
= false;
1078 bool list_mode
= false;
1079 bool count_mode
= false;
1080 bool got_module
= false;
1081 bool assert_none
= false;
1082 bool assert_any
= false;
1083 int assert_count
= -1;
1084 std::string write_file
, read_file
;
1085 std::string set_name
, sel_str
;
1090 for (argidx
= 1; argidx
< args
.size(); argidx
++)
1092 std::string arg
= args
[argidx
];
1093 if (arg
== "-add") {
1097 if (arg
== "-del") {
1101 if (arg
== "-assert-none") {
1105 if (arg
== "-assert-any") {
1109 if (arg
== "-assert-count" && argidx
+1 < args
.size()) {
1110 assert_count
= atoi(args
[++argidx
].c_str());
1113 if (arg
== "-clear") {
1117 if (arg
== "-none") {
1121 if (arg
== "-list") {
1125 if (arg
== "-write" && argidx
+1 < args
.size()) {
1126 write_file
= args
[++argidx
];
1129 if (arg
== "-read" && argidx
+1 < args
.size()) {
1130 read_file
= args
[++argidx
];
1133 if (arg
== "-count") {
1137 if (arg
== "-module" && argidx
+1 < args
.size()) {
1138 RTLIL::IdString mod_name
= RTLIL::escape_id(args
[++argidx
]);
1139 if (design
->modules_
.count(mod_name
) == 0)
1140 log_cmd_error("No such module: %s\n", id2cstr(mod_name
));
1141 design
->selected_active_module
= mod_name
.str();
1145 if (arg
== "-set" && argidx
+1 < args
.size()) {
1146 set_name
= RTLIL::escape_id(args
[++argidx
]);
1149 if (arg
.size() > 0 && arg
[0] == '-')
1150 log_cmd_error("Unknown option %s.\n", arg
.c_str());
1151 select_stmt(design
, arg
);
1152 sel_str
+= " " + arg
;
1155 if (!read_file
.empty())
1157 if (!sel_str
.empty())
1158 log_cmd_error("Option -read can not be combined with a selection expression.\n");
1160 std::ifstream
f(read_file
);
1162 log_error("Can't open '%s' for reading: %s\n", read_file
.c_str(), strerror(errno
));
1164 RTLIL::Selection
sel(false);
1167 while (std::getline(f
, line
)) {
1168 size_t slash_pos
= line
.find('/');
1169 if (slash_pos
== string::npos
) {
1170 log_warning("Ignoring line without slash in 'select -read': %s\n", line
.c_str());
1173 IdString mod_name
= RTLIL::escape_id(line
.substr(0, slash_pos
));
1174 IdString obj_name
= RTLIL::escape_id(line
.substr(slash_pos
+1));
1175 sel
.selected_members
[mod_name
].insert(obj_name
);
1178 select_filter_active_mod(design
, sel
);
1179 sel
.optimize(design
);
1180 work_stack
.push_back(sel
);
1183 if (clear_mode
&& args
.size() != 2)
1184 log_cmd_error("Option -clear can not be combined with any other options.\n");
1186 if (none_mode
&& args
.size() != 2)
1187 log_cmd_error("Option -none can not be combined with any other options.\n");
1189 if (add_mode
+ del_mode
+ assert_none
+ assert_any
+ (assert_count
>= 0) > 1)
1190 log_cmd_error("Options -add, -del, -assert-none, -assert-any or -assert-count can not be combined.\n");
1192 if ((list_mode
|| !write_file
.empty() || count_mode
) && (add_mode
|| del_mode
|| assert_none
|| assert_any
|| assert_count
>= 0))
1193 log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none, -assert-any or -assert-count.\n");
1195 if (!set_name
.empty() && (list_mode
|| !write_file
.empty() || count_mode
|| add_mode
|| del_mode
|| assert_none
|| assert_any
|| assert_count
>= 0))
1196 log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any or -assert-count.\n");
1198 if (work_stack
.size() == 0 && got_module
) {
1199 RTLIL::Selection sel
;
1200 select_filter_active_mod(design
, sel
);
1201 work_stack
.push_back(sel
);
1204 while (work_stack
.size() > 1) {
1205 select_op_union(design
, work_stack
.front(), work_stack
.back());
1206 work_stack
.pop_back();
1209 log_assert(design
->selection_stack
.size() > 0);
1212 design
->selection_stack
.back() = RTLIL::Selection(true);
1213 design
->selected_active_module
= std::string();
1218 design
->selection_stack
.back() = RTLIL::Selection(false);
1222 if (list_mode
|| count_mode
|| !write_file
.empty())
1224 #define LOG_OBJECT(...) { if (list_mode) log(__VA_ARGS__); if (f != NULL) fprintf(f, __VA_ARGS__); total_count++; }
1225 int total_count
= 0;
1227 if (!write_file
.empty()) {
1228 f
= fopen(write_file
.c_str(), "w");
1230 log_error("Can't open '%s' for writing: %s\n", write_file
.c_str(), strerror(errno
));
1232 RTLIL::Selection
*sel
= &design
->selection_stack
.back();
1233 if (work_stack
.size() > 0)
1234 sel
= &work_stack
.back();
1235 sel
->optimize(design
);
1236 for (auto mod_it
: design
->modules_
)
1238 if (sel
->selected_whole_module(mod_it
.first
) && list_mode
)
1239 log("%s\n", id2cstr(mod_it
.first
));
1240 if (sel
->selected_module(mod_it
.first
)) {
1241 for (auto &it
: mod_it
.second
->wires_
)
1242 if (sel
->selected_member(mod_it
.first
, it
.first
))
1243 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
))
1244 for (auto &it
: mod_it
.second
->memories
)
1245 if (sel
->selected_member(mod_it
.first
, it
.first
))
1246 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
))
1247 for (auto &it
: mod_it
.second
->cells_
)
1248 if (sel
->selected_member(mod_it
.first
, it
.first
))
1249 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
))
1250 for (auto &it
: mod_it
.second
->processes
)
1251 if (sel
->selected_member(mod_it
.first
, it
.first
))
1252 LOG_OBJECT("%s/%s\n", id2cstr(mod_it
.first
), id2cstr(it
.first
))
1256 log("%d objects.\n", total_count
);
1265 if (work_stack
.size() == 0)
1266 log_cmd_error("Nothing to add to selection.\n");
1267 select_op_union(design
, design
->selection_stack
.back(), work_stack
.back());
1268 design
->selection_stack
.back().optimize(design
);
1274 if (work_stack
.size() == 0)
1275 log_cmd_error("Nothing to delete from selection.\n");
1276 select_op_diff(design
, design
->selection_stack
.back(), work_stack
.back());
1277 design
->selection_stack
.back().optimize(design
);
1283 if (work_stack
.size() == 0)
1284 log_cmd_error("No selection to check.\n");
1285 if (!work_stack
.back().empty())
1286 log_error("Assertation failed: selection is not empty:%s\n", sel_str
.c_str());
1292 if (work_stack
.size() == 0)
1293 log_cmd_error("No selection to check.\n");
1294 if (work_stack
.back().empty())
1295 log_error("Assertation failed: selection is empty:%s\n", sel_str
.c_str());
1299 if (assert_count
>= 0)
1301 int total_count
= 0;
1302 if (work_stack
.size() == 0)
1303 log_cmd_error("No selection to check.\n");
1304 RTLIL::Selection
*sel
= &work_stack
.back();
1305 sel
->optimize(design
);
1306 for (auto mod_it
: design
->modules_
)
1307 if (sel
->selected_module(mod_it
.first
)) {
1308 for (auto &it
: mod_it
.second
->wires_
)
1309 if (sel
->selected_member(mod_it
.first
, it
.first
))
1311 for (auto &it
: mod_it
.second
->memories
)
1312 if (sel
->selected_member(mod_it
.first
, it
.first
))
1314 for (auto &it
: mod_it
.second
->cells_
)
1315 if (sel
->selected_member(mod_it
.first
, it
.first
))
1317 for (auto &it
: mod_it
.second
->processes
)
1318 if (sel
->selected_member(mod_it
.first
, it
.first
))
1321 if (assert_count
!= total_count
)
1322 log_error("Assertation failed: selection contains %d elements instead of the asserted %d:%s\n",
1323 total_count
, assert_count
, sel_str
.c_str());
1327 if (!set_name
.empty())
1329 if (work_stack
.size() == 0)
1330 design
->selection_vars
[set_name
] = RTLIL::Selection(false);
1332 design
->selection_vars
[set_name
] = work_stack
.back();
1336 if (work_stack
.size() == 0) {
1337 RTLIL::Selection
&sel
= design
->selection_stack
.back();
1338 if (sel
.full_selection
)
1340 for (auto &it
: sel
.selected_modules
)
1341 log("%s\n", id2cstr(it
));
1342 for (auto &it
: sel
.selected_members
)
1343 for (auto &it2
: it
.second
)
1344 log("%s/%s\n", id2cstr(it
.first
), id2cstr(it2
));
1348 design
->selection_stack
.back() = work_stack
.back();
1349 design
->selection_stack
.back().optimize(design
);
1353 struct CdPass
: public Pass
{
1354 CdPass() : Pass("cd", "a shortcut for 'select -module <name>'") { }
1357 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1359 log(" cd <modname>\n");
1361 log("This is just a shortcut for 'select -module <modname>'.\n");
1364 log(" cd <cellname>\n");
1366 log("When no module with the specified name is found, but there is a cell\n");
1367 log("with the specified name in the current module, then this is equivialent\n");
1368 log("to 'cd <celltype>'.\n");
1372 log("This is just a shortcut for 'select -clear'.\n");
1375 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
1377 if (args
.size() != 2)
1378 log_cmd_error("Invalid number of arguments.\n");
1380 if (args
[1] == "..") {
1381 design
->selection_stack
.back() = RTLIL::Selection(true);
1382 design
->selected_active_module
= std::string();
1386 std::string modname
= RTLIL::escape_id(args
[1]);
1388 if (design
->modules_
.count(modname
) == 0 && !design
->selected_active_module
.empty()) {
1389 RTLIL::Module
*module
= NULL
;
1390 if (design
->modules_
.count(design
->selected_active_module
) > 0)
1391 module
= design
->modules_
.at(design
->selected_active_module
);
1392 if (module
!= NULL
&& module
->cells_
.count(modname
) > 0)
1393 modname
= module
->cells_
.at(modname
)->type
.str();
1396 if (design
->modules_
.count(modname
) > 0) {
1397 design
->selected_active_module
= modname
;
1398 design
->selection_stack
.back() = RTLIL::Selection();
1399 select_filter_active_mod(design
, design
->selection_stack
.back());
1400 design
->selection_stack
.back().optimize(design
);
1404 log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname
).c_str());
1408 template<typename T
>
1409 static void log_matches(const char *title
, Module
*module
, T list
)
1411 std::vector
<IdString
> matches
;
1413 for (auto &it
: list
)
1414 if (module
->selected(it
.second
))
1415 matches
.push_back(it
.first
);
1417 if (!matches
.empty()) {
1418 log("\n%d %s:\n", int(matches
.size()), title
);
1419 std::sort(matches
.begin(), matches
.end(), RTLIL::sort_by_id_str());
1420 for (auto id
: matches
)
1421 log(" %s\n", RTLIL::id2cstr(id
));
1425 struct LsPass
: public Pass
{
1426 LsPass() : Pass("ls", "list modules or objects in modules") { }
1429 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1431 log(" ls [selection]\n");
1433 log("When no active module is selected, this prints a list of modules.\n");
1435 log("When an active module is selected, this prints a list of objects in the module.\n");
1438 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
1441 extra_args(args
, argidx
, design
);
1443 if (design
->selected_active_module
.empty())
1445 std::vector
<IdString
> matches
;
1447 for (auto mod
: design
->selected_modules())
1448 matches
.push_back(mod
->name
);
1450 if (!matches
.empty()) {
1451 log("\n%d %s:\n", int(matches
.size()), "modules");
1452 std::sort(matches
.begin(), matches
.end(), RTLIL::sort_by_id_str());
1453 for (auto id
: matches
)
1454 log(" %s%s\n", log_id(id
), design
->selected_whole_module(design
->module(id
)) ? "" : "*");
1458 if (design
->module(design
->selected_active_module
) != nullptr)
1460 RTLIL::Module
*module
= design
->module(design
->selected_active_module
);
1461 log_matches("wires", module
, module
->wires_
);
1462 log_matches("memories", module
, module
->memories
);
1463 log_matches("cells", module
, module
->cells_
);
1464 log_matches("processes", module
, module
->processes
);
1469 PRIVATE_NAMESPACE_END