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Merge pull request #1105 from YosysHQ/clifford/fixlogicinit
[yosys.git] / passes / cmds / setundef.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/rtlil.h"
24 #include "kernel/log.h"
25
26 #define MODE_ZERO 0
27 #define MODE_ONE 1
28 #define MODE_UNDEF 2
29 #define MODE_RANDOM 3
30 #define MODE_ANYSEQ 4
31 #define MODE_ANYCONST 5
32
33 USING_YOSYS_NAMESPACE
34 PRIVATE_NAMESPACE_BEGIN
35
36 static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output)
37 {
38 RTLIL::Wire *wire = NULL;
39 name = RTLIL::escape_id(name);
40
41 if (module->count_id(name) != 0)
42 {
43 log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str());
44 name += "$";
45 return add_wire(module, name, width, flag_input, flag_output);
46 }
47 else
48 {
49 wire = module->addWire(name, width);
50 wire->port_input = flag_input;
51 wire->port_output = flag_output;
52
53 if (flag_input || flag_output) {
54 wire->port_id = module->wires_.size();
55 module->fixup_ports();
56 }
57
58 log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
59 }
60
61 return wire;
62 }
63
64 struct SetundefWorker
65 {
66 int next_bit_mode;
67 uint32_t next_bit_state;
68 vector<SigSpec*> siglist;
69
70 RTLIL::State next_bit()
71 {
72 if (next_bit_mode == MODE_ZERO)
73 return RTLIL::State::S0;
74
75 if (next_bit_mode == MODE_ONE)
76 return RTLIL::State::S1;
77
78 if (next_bit_mode == MODE_UNDEF)
79 return RTLIL::State::Sx;
80
81 if (next_bit_mode == MODE_RANDOM)
82 {
83 // xorshift32
84 next_bit_state ^= next_bit_state << 13;
85 next_bit_state ^= next_bit_state >> 17;
86 next_bit_state ^= next_bit_state << 5;
87 log_assert(next_bit_state != 0);
88
89 return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1;
90 }
91
92 log_abort();
93 }
94
95 void operator()(RTLIL::SigSpec &sig)
96 {
97 if (next_bit_mode == MODE_ANYSEQ || next_bit_mode == MODE_ANYCONST) {
98 siglist.push_back(&sig);
99 return;
100 }
101
102 for (auto &bit : sig)
103 if (bit.wire == NULL && bit.data > RTLIL::State::S1)
104 bit = next_bit();
105 }
106 };
107
108 struct SetundefPass : public Pass {
109 SetundefPass() : Pass("setundef", "replace undef values with defined constants") { }
110 void help() YS_OVERRIDE
111 {
112 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
113 log("\n");
114 log(" setundef [options] [selection]\n");
115 log("\n");
116 log("This command replaces undef (x) constants with defined (0/1) constants.\n");
117 log("\n");
118 log(" -undriven\n");
119 log(" also set undriven nets to constant values\n");
120 log("\n");
121 log(" -expose\n");
122 log(" also expose undriven nets as inputs (use with -undriven)\n");
123 log("\n");
124 log(" -zero\n");
125 log(" replace with bits cleared (0)\n");
126 log("\n");
127 log(" -one\n");
128 log(" replace with bits set (1)\n");
129 log("\n");
130 log(" -undef\n");
131 log(" replace with undef (x) bits, may be used with -undriven\n");
132 log("\n");
133 log(" -anyseq\n");
134 log(" replace with $anyseq drivers (for formal)\n");
135 log("\n");
136 log(" -anyconst\n");
137 log(" replace with $anyconst drivers (for formal)\n");
138 log("\n");
139 log(" -random <seed>\n");
140 log(" replace with random bits using the specified integer as seed\n");
141 log(" value for the random number generator.\n");
142 log("\n");
143 log(" -init\n");
144 log(" also create/update init values for flip-flops\n");
145 log("\n");
146 log(" -params\n");
147 log(" replace undef in cell parameters\n");
148 log("\n");
149 }
150 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
151 {
152 bool got_value = false;
153 bool undriven_mode = false;
154 bool expose_mode = false;
155 bool init_mode = false;
156 bool params_mode = false;
157 SetundefWorker worker;
158
159 log_header(design, "Executing SETUNDEF pass (replace undef values with defined constants).\n");
160
161 size_t argidx;
162 for (argidx = 1; argidx < args.size(); argidx++)
163 {
164 if (args[argidx] == "-undriven") {
165 undriven_mode = true;
166 continue;
167 }
168 if (args[argidx] == "-expose") {
169 expose_mode = true;
170 continue;
171 }
172 if (args[argidx] == "-zero") {
173 got_value = true;
174 worker.next_bit_mode = MODE_ZERO;
175 worker.next_bit_state = 0;
176 continue;
177 }
178 if (args[argidx] == "-one") {
179 got_value = true;
180 worker.next_bit_mode = MODE_ONE;
181 worker.next_bit_state = 0;
182 continue;
183 }
184 if (args[argidx] == "-anyseq") {
185 got_value = true;
186 worker.next_bit_mode = MODE_ANYSEQ;
187 worker.next_bit_state = 0;
188 continue;
189 }
190 if (args[argidx] == "-anyconst") {
191 got_value = true;
192 worker.next_bit_mode = MODE_ANYCONST;
193 worker.next_bit_state = 0;
194 continue;
195 }
196 if (args[argidx] == "-undef") {
197 got_value = true;
198 worker.next_bit_mode = MODE_UNDEF;
199 worker.next_bit_state = 0;
200 continue;
201 }
202 if (args[argidx] == "-init") {
203 init_mode = true;
204 continue;
205 }
206 if (args[argidx] == "-params") {
207 params_mode = true;
208 continue;
209 }
210 if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) {
211 got_value = true;
212 worker.next_bit_mode = MODE_RANDOM;
213 worker.next_bit_state = atoi(args[++argidx].c_str()) + 1;
214 for (int i = 0; i < 10; i++)
215 worker.next_bit();
216 continue;
217 }
218 break;
219 }
220 extra_args(args, argidx, design);
221
222 if (!got_value && expose_mode) {
223 log("Using default as -undef with -expose.\n");
224 got_value = true;
225 worker.next_bit_mode = MODE_UNDEF;
226 worker.next_bit_state = 0;
227 }
228
229 if (expose_mode && !undriven_mode)
230 log_cmd_error("Option -expose must be used with option -undriven.\n");
231 if (!got_value)
232 log_cmd_error("One of the options -zero, -one, -anyseq, -anyconst, or -random <seed> must be specified.\n");
233
234 if (init_mode && (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST))
235 log_cmd_error("The options -init and -anyseq / -anyconst are exclusive.\n");
236
237 for (auto module : design->selected_modules())
238 {
239 if (params_mode)
240 {
241 for (auto *cell : module->selected_cells()) {
242 for (auto &parameter : cell->parameters) {
243 for (auto &bit : parameter.second.bits) {
244 if (bit > RTLIL::State::S1)
245 bit = worker.next_bit();
246 }
247 }
248 }
249 }
250
251 if (undriven_mode)
252 {
253 if (!module->processes.empty())
254 log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n");
255
256 if (expose_mode)
257 {
258 SigMap sigmap(module);
259 dict<SigBit, bool> wire_drivers;
260 pool<SigBit> used_wires;
261 SigPool undriven_signals;
262
263 for (auto cell : module->cells())
264 for (auto &conn : cell->connections()) {
265 SigSpec sig = sigmap(conn.second);
266 if (cell->input(conn.first))
267 for (auto bit : sig)
268 if (bit.wire)
269 used_wires.insert(bit);
270 if (cell->output(conn.first))
271 for (int i = 0; i < GetSize(sig); i++)
272 if (sig[i].wire)
273 wire_drivers[sig[i]] = true;
274 }
275
276 for (auto wire : module->wires()) {
277 if (wire->port_input) {
278 SigSpec sig = sigmap(wire);
279 for (int i = 0; i < GetSize(sig); i++)
280 wire_drivers[sig[i]] = true;
281 }
282 if (wire->port_output) {
283 SigSpec sig = sigmap(wire);
284 for (auto bit : sig)
285 if (bit.wire)
286 used_wires.insert(bit);
287 }
288 }
289
290 pool<RTLIL::Wire*> undriven_wires;
291 for (auto bit : used_wires)
292 if (!wire_drivers.count(bit))
293 undriven_wires.insert(bit.wire);
294
295 for (auto &it : undriven_wires)
296 undriven_signals.add(sigmap(it));
297
298 for (auto &it : undriven_wires)
299 if (it->port_input)
300 undriven_signals.del(sigmap(it));
301
302 CellTypes ct(design);
303 for (auto &it : module->cells_)
304 for (auto &conn : it.second->connections())
305 if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
306 undriven_signals.del(sigmap(conn.second));
307
308 RTLIL::SigSpec sig = undriven_signals.export_all();
309 for (auto &c : sig.chunks()) {
310 RTLIL::Wire * wire;
311 if (c.wire->width == c.width) {
312 wire = c.wire;
313 wire->port_input = true;
314 } else {
315 string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]";
316 wire = add_wire(module, name, c.width, true, false);
317 module->connect(RTLIL::SigSig(c, wire));
318 }
319 log("Exposing undriven wire %s as input.\n", wire->name.c_str());
320 }
321 module->fixup_ports();
322 }
323 else
324 {
325 SigMap sigmap(module);
326 SigPool undriven_signals;
327
328 for (auto &it : module->wires_)
329 undriven_signals.add(sigmap(it.second));
330
331 for (auto &it : module->wires_)
332 if (it.second->port_input)
333 undriven_signals.del(sigmap(it.second));
334
335 CellTypes ct(design);
336 for (auto &it : module->cells_)
337 for (auto &conn : it.second->connections())
338 if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
339 undriven_signals.del(sigmap(conn.second));
340
341 RTLIL::SigSpec sig = undriven_signals.export_all();
342 for (auto &c : sig.chunks()) {
343 RTLIL::SigSpec bits;
344 if (worker.next_bit_mode == MODE_ANYSEQ)
345 bits = module->Anyseq(NEW_ID, c.width);
346 else if (worker.next_bit_mode == MODE_ANYCONST)
347 bits = module->Anyconst(NEW_ID, c.width);
348 else
349 for (int i = 0; i < c.width; i++)
350 bits.append(worker.next_bit());
351 module->connect(RTLIL::SigSig(c, bits));
352 }
353 }
354 }
355
356 if (init_mode)
357 {
358 SigMap sigmap(module);
359 pool<SigBit> ffbits;
360 pool<Wire*> initwires;
361
362 pool<IdString> fftypes;
363 fftypes.insert("$dff");
364 fftypes.insert("$dffe");
365 fftypes.insert("$dffsr");
366 fftypes.insert("$adff");
367
368 std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
369
370 for (auto c1 : list_np)
371 fftypes.insert(stringf("$_DFF_%c_", c1));
372
373 for (auto c1 : list_np)
374 for (auto c2 : list_np)
375 fftypes.insert(stringf("$_DFFE_%c%c_", c1, c2));
376
377 for (auto c1 : list_np)
378 for (auto c2 : list_np)
379 for (auto c3 : list_01)
380 fftypes.insert(stringf("$_DFF_%c%c%c_", c1, c2, c3));
381
382 for (auto c1 : list_np)
383 for (auto c2 : list_np)
384 for (auto c3 : list_np)
385 fftypes.insert(stringf("$_DFFSR_%c%c%c_", c1, c2, c3));
386
387 for (auto cell : module->cells())
388 {
389 if (!fftypes.count(cell->type))
390 continue;
391
392 for (auto bit : sigmap(cell->getPort("\\Q")))
393 ffbits.insert(bit);
394 }
395
396 auto process_initwires = [&]()
397 {
398 dict<Wire*, int> wire_weights;
399
400 for (auto wire : initwires)
401 {
402 int weight = 0;
403
404 for (auto bit : sigmap(wire))
405 weight += ffbits.count(bit) ? +1 : -1;
406
407 wire_weights[wire] = weight;
408 }
409
410 initwires.sort([&](Wire *a, Wire *b) { return wire_weights.at(a) > wire_weights.at(b); });
411
412 for (auto wire : initwires)
413 {
414 Const &initval = wire->attributes["\\init"];
415 initval.bits.resize(GetSize(wire), State::Sx);
416
417 for (int i = 0; i < GetSize(wire); i++) {
418 SigBit bit = sigmap(SigBit(wire, i));
419 if (initval[i] == State::Sx && ffbits.count(bit)) {
420 initval[i] = worker.next_bit();
421 ffbits.erase(bit);
422 }
423 }
424
425 if (initval.is_fully_undef())
426 wire->attributes.erase("\\init");
427 }
428
429 initwires.clear();
430 };
431
432 for (int wire_types = 0; wire_types < 2; wire_types++)
433 {
434 // prioritize wires that already have an init attribute
435 if (!ffbits.empty())
436 {
437 for (auto wire : module->wires())
438 {
439 if (wire->name[0] == (wire_types ? '\\' : '$'))
440 continue;
441
442 if (!wire->attributes.count("\\init"))
443 continue;
444
445 Const &initval = wire->attributes["\\init"];
446 initval.bits.resize(GetSize(wire), State::Sx);
447
448 if (initval.is_fully_undef()) {
449 wire->attributes.erase("\\init");
450 continue;
451 }
452
453 for (int i = 0; i < GetSize(wire); i++)
454 if (initval[i] != State::Sx)
455 ffbits.erase(sigmap(SigBit(wire, i)));
456
457 initwires.insert(wire);
458 }
459
460 process_initwires();
461 }
462
463 // next consider wires that completely contain bits to be initialized
464 if (!ffbits.empty())
465 {
466 for (auto wire : module->wires())
467 {
468 if (wire->name[0] == (wire_types ? '\\' : '$'))
469 continue;
470
471 for (auto bit : sigmap(wire))
472 if (!ffbits.count(bit))
473 goto next_wire;
474
475 initwires.insert(wire);
476
477 next_wire:
478 continue;
479 }
480
481 process_initwires();
482 }
483
484 // finally use whatever wire we can find.
485 if (!ffbits.empty())
486 {
487 for (auto wire : module->wires())
488 {
489 if (wire->name[0] == (wire_types ? '\\' : '$'))
490 continue;
491
492 for (auto bit : sigmap(wire))
493 if (ffbits.count(bit))
494 initwires.insert(wire);
495 }
496
497 process_initwires();
498 }
499 }
500
501 log_assert(ffbits.empty());
502 }
503
504 module->rewrite_sigspecs(worker);
505
506 if (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST)
507 {
508 vector<SigSpec*> siglist;
509 siglist.swap(worker.siglist);
510
511 for (auto sigptr : siglist)
512 {
513 SigSpec &sig = *sigptr;
514 int cursor = 0;
515
516 while (cursor < GetSize(sig))
517 {
518 int width = 0;
519 while (cursor+width < GetSize(sig) && sig[cursor+width] == State::Sx)
520 width++;
521
522 if (width > 0) {
523 if (worker.next_bit_mode == MODE_ANYSEQ)
524 sig.replace(cursor, module->Anyseq(NEW_ID, width));
525 else
526 sig.replace(cursor, module->Anyconst(NEW_ID, width));
527 cursor += width;
528 } else {
529 cursor++;
530 }
531 }
532 }
533 }
534 }
535 }
536 } SetundefPass;
537
538 PRIVATE_NAMESPACE_END