passes/cmds/splitnets.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SplitnetsWorker
  29 {
  30         std::map<RTLIL::Wire*, std::vector<RTLIL::SigBit>> splitmap;
  31
  32         void append_wire(RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format)
  33         {
  34                 std::string new_wire_name = wire->name.str();
  35
  36                 if (format.size() > 0)
  37                         new_wire_name += format.substr(0, 1);
  38
  39                 if (width > 1) {
  40                         if (wire->upto)
  41                                 new_wire_name += stringf("%d", wire->start_offset+wire->width-(offset+width)-1);
  42                         else
  43                                 new_wire_name += stringf("%d", wire->start_offset+offset+width-1);
  44                         if (format.size() > 2)
  45                                 new_wire_name += format.substr(2, 1);
  46                         else
  47                                 new_wire_name += ":";
  48                 }
  49
  50                 if (wire->upto)
  51                         new_wire_name += stringf("%d", wire->start_offset+wire->width-offset-1);
  52                 else
  53                         new_wire_name += stringf("%d", wire->start_offset+offset);
  54
  55                 if (format.size() > 1)
  56                         new_wire_name += format.substr(1, 1);
  57
  58                 RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width);
  59                 new_wire->port_id = wire->port_id ? wire->port_id + offset : 0;
  60                 new_wire->port_input = wire->port_input;
  61                 new_wire->port_output = wire->port_output;
  62
  63                 if (wire->attributes.count(ID::src))
  64                         new_wire->attributes[ID::src] = wire->attributes.at(ID::src);
  65
  66                 if (wire->attributes.count(ID::keep))
  67                         new_wire->attributes[ID::keep] = wire->attributes.at(ID::keep);
  68
  69                 if (wire->attributes.count(ID::init)) {
  70                         Const old_init = wire->attributes.at(ID::init), new_init;
  71                         for (int i = offset; i < offset+width; i++)
  72                                 new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
  73                         new_wire->attributes[ID::init] = new_init;
  74                 }
  75
  76                 std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
  77                 splitmap[wire].insert(splitmap[wire].end(), sigvec.begin(), sigvec.end());
  78         }
  79
  80         void operator()(RTLIL::SigSpec &sig)
  81         {
  82                 for (auto &bit : sig)
  83                         if (splitmap.count(bit.wire) > 0)
  84                                 bit = splitmap.at(bit.wire).at(bit.offset);
  85         }
  86 };
  87
  88 struct SplitnetsPass : public Pass {
  89         SplitnetsPass() : Pass("splitnets", "split up multi-bit nets") { }
  90         void help() YS_OVERRIDE
  91         {
  92                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  93                 log("\n");
  94                 log("    splitnets [options] [selection]\n");
  95                 log("\n");
  96                 log("This command splits multi-bit nets into single-bit nets.\n");
  97                 log("\n");
  98                 log("    -format char1[char2[char3]]\n");
  99                 log("        the first char is inserted between the net name and the bit index, the\n");
 100                 log("        second char is appended to the netname. e.g. -format () creates net\n");
 101                 log("        names like 'mysignal(42)'. the 3rd character is the range separation\n");
 102                 log("        character when creating multi-bit wires. the default is '[]:'.\n");
 103                 log("\n");
 104                 log("    -ports\n");
 105                 log("        also split module ports. per default only internal signals are split.\n");
 106                 log("\n");
 107                 log("    -driver\n");
 108                 log("        don't blindly split nets in individual bits. instead look at the driver\n");
 109                 log("        and split nets so that no driver drives only part of a net.\n");
 110                 log("\n");
 111         }
 112         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 113         {
 114                 bool flag_ports = false;
 115                 bool flag_driver = false;
 116                 std::string format = "[]:";
 117
 118                 log_header(design, "Executing SPLITNETS pass (splitting up multi-bit signals).\n");
 119
 120                 size_t argidx;
 121                 for (argidx = 1; argidx < args.size(); argidx++)
 122                 {
 123                         if (args[argidx] == "-format" && argidx+1 < args.size()) {
 124                                 format = args[++argidx];
 125                                 continue;
 126                         }
 127                         if (args[argidx] == "-ports") {
 128                                 flag_ports = true;
 129                                 continue;
 130                         }
 131                         if (args[argidx] == "-driver") {
 132                                 flag_driver = true;
 133                                 continue;
 134                         }
 135                         break;
 136                 }
 137                 extra_args(args, argidx, design);
 138
 139                 // module_ports_db[module_name][old_port_name] = new_port_name_list
 140                 dict<IdString, dict<IdString, vector<IdString>>> module_ports_db;
 141
 142                 for (auto module : design->selected_modules())
 143                 {
 144                         if (module->has_processes_warn())
 145                                 continue;
 146
 147                         SplitnetsWorker worker;
 148
 149                         if (flag_ports)
 150                         {
 151                                 int normalized_port_factor = 0;
 152
 153                                 for (auto wire : module->wires())
 154                                         if (wire->port_id != 0) {
 155                                                 normalized_port_factor = max(normalized_port_factor, wire->port_id+1);
 156                                                 normalized_port_factor = max(normalized_port_factor, GetSize(wire)+1);
 157                                         }
 158
 159                                 for (auto wire : module->wires())
 160                                         wire->port_id *= normalized_port_factor;
 161                         }
 162
 163                         if (flag_driver)
 164                         {
 165                                 CellTypes ct(design);
 166
 167                                 std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
 168
 169                                 for (auto &c : module->cells_)
 170                                 for (auto &p : c.second->connections())
 171                                 {
 172                                         if (!ct.cell_known(c.second->type))
 173                                                 continue;
 174                                         if (!ct.cell_output(c.second->type, p.first))
 175                                                 continue;
 176
 177                                         RTLIL::SigSpec sig = p.second;
 178                                         for (auto &chunk : sig.chunks()) {
 179                                                 if (chunk.wire == NULL)
 180                                                         continue;
 181                                                 if (chunk.wire->port_id == 0 || flag_ports) {
 182                                                         if (chunk.offset != 0)
 183                                                                 split_wires_at[chunk.wire].insert(chunk.offset);
 184                                                         if (chunk.offset + chunk.width < chunk.wire->width)
 185                                                                 split_wires_at[chunk.wire].insert(chunk.offset + chunk.width);
 186                                                 }
 187                                         }
 188                                 }
 189
 190                                 for (auto &it : split_wires_at) {
 191                                         int cursor = 0;
 192                                         for (int next_cursor : it.second) {
 193                                                 worker.append_wire(module, it.first, cursor, next_cursor - cursor, format);
 194                                                 cursor = next_cursor;
 195                                         }
 196                                         worker.append_wire(module, it.first, cursor, it.first->width - cursor, format);
 197                                 }
 198                         }
 199                         else
 200                         {
 201                                 for (auto &w : module->wires_) {
 202                                         RTLIL::Wire *wire = w.second;
 203                                         if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second))
 204                                                 worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
 205                                 }
 206
 207                                 for (auto &it : worker.splitmap)
 208                                         for (int i = 0; i < it.first->width; i++)
 209                                                 worker.append_wire(module, it.first, i, 1, format);
 210                         }
 211
 212                         module->rewrite_sigspecs(worker);
 213
 214                         if (flag_ports)
 215                         {
 216                                 for (auto wire : module->wires())
 217                                 {
 218                                         if (wire->port_id == 0)
 219                                                 continue;
 220
 221                                         SigSpec sig(wire);
 222                                         worker(sig);
 223
 224                                         if (sig == wire)
 225                                                 continue;
 226
 227                                         vector<IdString> &new_ports = module_ports_db[module->name][wire->name];
 228
 229                                         for (SigSpec c : sig.chunks())
 230                                                 new_ports.push_back(c.as_wire()->name);
 231                                 }
 232                         }
 233
 234                         pool<RTLIL::Wire*> delete_wires;
 235                         for (auto &it : worker.splitmap)
 236                                 delete_wires.insert(it.first);
 237                         module->remove(delete_wires);
 238
 239                         if (flag_ports)
 240                                 module->fixup_ports();
 241                 }
 242
 243                 if (!module_ports_db.empty())
 244                 {
 245                         for (auto module : design->modules())
 246                         for (auto cell : module->cells())
 247                         {
 248                                 if (module_ports_db.count(cell->type) == 0)
 249                                         continue;
 250
 251                                 for (auto &it : module_ports_db.at(cell->type))
 252                                 {
 253                                         IdString port_id = it.first;
 254                                         const auto &new_port_ids = it.second;
 255
 256                                         if (!cell->hasPort(port_id))
 257                                                 continue;
 258
 259                                         int offset = 0;
 260                                         SigSpec sig = cell->getPort(port_id);
 261
 262                                         for (auto nid : new_port_ids)
 263                                         {
 264                                                 int nlen = GetSize(design->module(cell->type)->wire(nid));
 265                                                 if (offset + nlen > GetSize(sig))
 266                                                         nlen = GetSize(sig) - offset;
 267                                                 if (nlen > 0)
 268                                                         cell->setPort(nid, sig.extract(offset, nlen));
 269                                                 offset += nlen;
 270                                         }
 271
 272                                         cell->unsetPort(port_id);
 273                                 }
 274                         }
 275                 }
 276         }
 277 } SplitnetsPass;
 278
 279 PRIVATE_NAMESPACE_END