2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2014 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2014 Johann Glaser <Johann.Glaser@gmx.at>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "kernel/yosys.h"
24 PRIVATE_NAMESPACE_BEGIN
26 struct TraceMonitor
: public RTLIL::Monitor
28 void notify_module_add(RTLIL::Module
*module
) YS_OVERRIDE
30 log("#TRACE# Module add: %s\n", log_id(module
));
33 void notify_module_del(RTLIL::Module
*module
) YS_OVERRIDE
35 log("#TRACE# Module delete: %s\n", log_id(module
));
38 void notify_connect(RTLIL::Cell
*cell
, const RTLIL::IdString
&port
, const RTLIL::SigSpec
&old_sig
, const RTLIL::SigSpec
&sig
) YS_OVERRIDE
40 log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell
->module
), log_id(cell
), log_id(port
), log_signal(sig
), log_signal(old_sig
));
43 void notify_connect(RTLIL::Module
*module
, const RTLIL::SigSig
&sigsig
) YS_OVERRIDE
45 log("#TRACE# Connection in module %s: %s = %s\n", log_id(module
), log_signal(sigsig
.first
), log_signal(sigsig
.second
));
48 void notify_connect(RTLIL::Module
*module
, const std::vector
<RTLIL::SigSig
> &sigsig_vec
) YS_OVERRIDE
50 log("#TRACE# New connections in module %s:\n", log_id(module
));
51 for (auto &sigsig
: sigsig_vec
)
52 log("## %s = %s\n", log_signal(sigsig
.first
), log_signal(sigsig
.second
));
55 void notify_blackout(RTLIL::Module
*module
) YS_OVERRIDE
57 log("#TRACE# Blackout in module %s:\n", log_id(module
));
61 struct TracePass
: public Pass
{
62 TracePass() : Pass("trace", "redirect command output to file") { }
63 void help() YS_OVERRIDE
65 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
69 log("Execute the specified command, logging all changes the command performs on\n");
70 log("the design in real time.\n");
73 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
76 for (argidx
= 1; argidx
< args
.size(); argidx
++)
78 // .. parse options ..
83 design
->monitors
.insert(&monitor
);
86 std::vector
<std::string
> new_args(args
.begin() + argidx
, args
.end());
87 Pass::call(design
, new_args
);
89 design
->monitors
.erase(&monitor
);
93 design
->monitors
.erase(&monitor
);
97 struct DebugPass
: public Pass
{
98 DebugPass() : Pass("debug", "run command with debug log messages enabled") { }
99 void help() YS_OVERRIDE
101 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
105 log("Execute the specified command with debug log messages enabled\n");
108 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
111 for (argidx
= 1; argidx
< args
.size(); argidx
++)
113 // .. parse options ..
120 std::vector
<std::string
> new_args(args
.begin() + argidx
, args
.end());
121 Pass::call(design
, new_args
);
131 PRIVATE_NAMESPACE_END