passes/cmds/trace.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2014  Clifford Wolf <clifford@clifford.at>
   5  *  Copyright (C) 2014  Johann Glaser <Johann.Glaser@gmx.at>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #include "kernel/yosys.h"
  22
  23 USING_YOSYS_NAMESPACE
  24 PRIVATE_NAMESPACE_BEGIN
  25
  26 struct TraceMonitor : public RTLIL::Monitor
  27 {
  28         virtual void notify_module_add(RTLIL::Module *module) YS_OVERRIDE
  29         {
  30                 log("#TRACE# Module add: %s\n", log_id(module));
  31         }
  32
  33         virtual void notify_module_del(RTLIL::Module *module) YS_OVERRIDE
  34         {
  35                 log("#TRACE# Module delete: %s\n", log_id(module));
  36         }
  37
  38         virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE
  39         {
  40                 log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
  41         }
  42
  43         virtual void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) YS_OVERRIDE
  44         {
  45                 log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second));
  46         }
  47
  48         virtual void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) YS_OVERRIDE
  49         {
  50                 log("#TRACE# New connections in module %s:\n", log_id(module));
  51                 for (auto &sigsig : sigsig_vec)
  52                         log("##    %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second));
  53         }
  54
  55         virtual void notify_blackout(RTLIL::Module *module) YS_OVERRIDE
  56         {
  57                 log("#TRACE# Blackout in module %s:\n", log_id(module));
  58         }
  59 };
  60
  61 struct TracePass : public Pass {
  62         TracePass() : Pass("trace", "redirect command output to file") { }
  63         virtual void help()
  64         {
  65                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  66                 log("\n");
  67                 log("    trace cmd\n");
  68                 log("\n");
  69                 log("Execute the specified command, logging all changes the command performs on\n");
  70                 log("the design in real time.\n");
  71                 log("\n");
  72         }
  73         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
  74         {
  75                 size_t argidx;
  76                 for (argidx = 1; argidx < args.size(); argidx++)
  77                 {
  78                         // .. parse options ..
  79                         break;
  80                 }
  81
  82                 TraceMonitor monitor;
  83                 design->monitors.insert(&monitor);
  84
  85                 try {
  86                         std::vector<std::string> new_args(args.begin() + argidx, args.end());
  87                         Pass::call(design, new_args);
  88                 } catch (log_cmd_error_exception) {
  89                         design->monitors.erase(&monitor);
  90                         throw log_cmd_error_exception();
  91                 }
  92
  93                 design->monitors.erase(&monitor);
  94         }
  95 } TracePass;
  96
  97 PRIVATE_NAMESPACE_END
  98