passes/equiv/equiv_add.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/sigtools.h"
  22
  23 USING_YOSYS_NAMESPACE
  24 PRIVATE_NAMESPACE_BEGIN
  25
  26 struct EquivAddPass : public Pass {
  27         EquivAddPass() : Pass("equiv_add", "add a $equiv cell") { }
  28         virtual void help()
  29         {
  30                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  31                 log("\n");
  32                 log("    equiv_add gold_sig gate_sig\n");
  33                 log("\n");
  34                 log("This command adds an $equiv cell for the specified signals.\n");
  35                 log("\n");
  36         }
  37         virtual void execute(std::vector<std::string> args, Design *design)
  38         {
  39                 if (GetSize(args) != 3)
  40                          cmd_error(args, GetSize(args)-1, "Invalid number of arguments.");
  41
  42                 if (design->selected_active_module.empty())
  43                         log_cmd_error("This command must be executed in module context!\n");
  44
  45                 Module *module = design->module(design->selected_active_module);
  46                 log_assert(module != nullptr);
  47
  48                 SigSpec gold_signal, gate_signal;
  49
  50                 if (!SigSpec::parse(gate_signal, module, args[2]))
  51                         log_cmd_error("Error in gate signal: %s\n", args[2].c_str());
  52
  53                 if (!SigSpec::parse_rhs(gate_signal, gold_signal, module, args[1]))
  54                         log_cmd_error("Error in gold signal: %s\n", args[1].c_str());
  55
  56                 log_assert(GetSize(gold_signal) == GetSize(gate_signal));
  57                 SigSpec equiv_signal = module->addWire(NEW_ID, GetSize(gold_signal));
  58
  59                 SigMap sigmap(module);
  60                 sigmap.apply(gold_signal);
  61                 sigmap.apply(gate_signal);
  62
  63                 dict<SigBit, SigBit> to_equiv_bits;
  64                 pool<Cell*> added_equiv_cells;
  65
  66                 for (int i = 0; i < GetSize(gold_signal); i++) {
  67                         Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]);
  68                         equiv_cell->set_bool_attribute("\\keep");
  69                         to_equiv_bits[gold_signal[i]] = equiv_signal[i];
  70                         to_equiv_bits[gate_signal[i]] = equiv_signal[i];
  71                         added_equiv_cells.insert(equiv_cell);
  72                 }
  73
  74                 for (auto cell : module->cells())
  75                 for (auto conn : cell->connections())
  76                         if (!added_equiv_cells.count(cell) && cell->input(conn.first)) {
  77                                 SigSpec new_sig;
  78                                 for (auto bit : conn.second)
  79                                         if (to_equiv_bits.count(sigmap(bit)))
  80                                                 new_sig.append(to_equiv_bits.at(sigmap(bit)));
  81                                         else
  82                                                  new_sig.append(bit);
  83                                 if (conn.second != new_sig)
  84                                         cell->setPort(conn.first, new_sig);
  85                         }
  86         }
  87 } EquivAddPass;
  88
  89 PRIVATE_NAMESPACE_END