Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock
[yosys.git] / passes / equiv / equiv_opt.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2018 whitequark <whitequark@whitequark.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21
22 USING_YOSYS_NAMESPACE
23 PRIVATE_NAMESPACE_BEGIN
24
25 struct EquivOptPass:public ScriptPass
26 {
27 EquivOptPass() : ScriptPass("equiv_opt", "prove equivalence for optimized circuit") { }
28
29 void help() YS_OVERRIDE
30 {
31 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
32 log("\n");
33 log(" equiv_opt [options] [command]\n");
34 log("\n");
35 log("This command checks circuit equivalence before and after an optimization pass.\n");
36 log("\n");
37 log(" -run <from_label>:<to_label>\n");
38 log(" only run the commands between the labels (see below). an empty\n");
39 log(" from label is synonymous to the start of the command list, and empty to\n");
40 log(" label is synonymous to the end of the command list.\n");
41 log("\n");
42 log(" -map <filename>\n");
43 log(" expand the modules in this file before proving equivalence. this is\n");
44 log(" useful for handling architecture-specific primitives.\n");
45 log("\n");
46 log(" -assert\n");
47 log(" produce an error if the circuits are not equivalent.\n");
48 log("\n");
49 log(" -multiclock\n");
50 log(" run clk2fflogic before equivalence checking.\n");
51 log("\n");
52 log(" -undef\n");
53 log(" enable modelling of undef states during equiv_induct.\n");
54 log("\n");
55 log("The following commands are executed by this verification command:\n");
56 help_script();
57 log("\n");
58 }
59
60 std::string command, techmap_opts;
61 bool assert, undef, multiclock;
62
63 void clear_flags() YS_OVERRIDE
64 {
65 command = "";
66 techmap_opts = "";
67 assert = false;
68 undef = false;
69 multiclock = false;
70 }
71
72 void execute(std::vector < std::string > args, RTLIL::Design * design) YS_OVERRIDE
73 {
74 string run_from, run_to;
75 clear_flags();
76
77 size_t argidx;
78 for (argidx = 1; argidx < args.size(); argidx++) {
79 if (args[argidx] == "-run" && argidx + 1 < args.size()) {
80 size_t pos = args[argidx + 1].find(':');
81 if (pos == std::string::npos)
82 break;
83 run_from = args[++argidx].substr(0, pos);
84 run_to = args[argidx].substr(pos + 1);
85 continue;
86 }
87 if (args[argidx] == "-map" && argidx + 1 < args.size()) {
88 techmap_opts += " -map " + args[++argidx];
89 continue;
90 }
91 if (args[argidx] == "-assert") {
92 assert = true;
93 continue;
94 }
95 if (args[argidx] == "-undef") {
96 undef = true;
97 continue;
98 }
99 if (args[argidx] == "-multiclock") {
100 multiclock = true;
101 continue;
102 }
103 break;
104 }
105
106 for (; argidx < args.size(); argidx++) {
107 if (command.empty()) {
108 if (args[argidx].compare(0, 1, "-") == 0)
109 cmd_error(args, argidx, "Unknown option.");
110 } else {
111 command += " ";
112 }
113 command += args[argidx];
114 }
115
116 if (command.empty())
117 log_cmd_error("No optimization pass specified!\n");
118
119 if (!design->full_selection())
120 log_cmd_error("This command only operates on fully selected designs!\n");
121
122 log_header(design, "Executing EQUIV_OPT pass.\n");
123 log_push();
124
125 run_script(design, run_from, run_to);
126
127 log_pop();
128 }
129
130 void script() YS_OVERRIDE
131 {
132 if (check_label("run_pass")) {
133 run("hierarchy -auto-top");
134 run("design -save preopt");
135 if (help_mode)
136 run("[command]");
137 else
138 run(command);
139 run("design -stash postopt");
140 }
141
142 if (check_label("prepare")) {
143 run("design -copy-from preopt -as gold A:top");
144 run("design -copy-from postopt -as gate A:top");
145 }
146
147 if ((!techmap_opts.empty() || help_mode) && check_label("techmap", "(only with -map)")) {
148 string opts;
149 if (help_mode)
150 opts = " -map <filename> ...";
151 else
152 opts = techmap_opts;
153 run("techmap -wb -D EQUIV -autoproc" + opts);
154 }
155
156 if (check_label("prove")) {
157 if (multiclock || help_mode)
158 run("clk2fflogic", "(only with -multiclock)");
159 run("equiv_make gold gate equiv");
160 if (help_mode)
161 run("equiv_induct [-undef] equiv");
162 else if (undef)
163 run("equiv_induct -undef equiv");
164 else
165 run("equiv_induct equiv");
166 if (help_mode)
167 run("equiv_status [-assert] equiv");
168 else if (assert)
169 run("equiv_status -assert equiv");
170 else
171 run("equiv_status equiv");
172 }
173
174 if (check_label("restore")) {
175 run("design -load preopt");
176 }
177 }
178 } EquivOptPass;
179
180 PRIVATE_NAMESPACE_END