2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2018 whitequark <whitequark@whitequark.org>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
23 PRIVATE_NAMESPACE_BEGIN
25 struct EquivOptPass
:public ScriptPass
27 EquivOptPass() : ScriptPass("equiv_opt", "prove equivalence for optimized circuit") { }
29 void help() YS_OVERRIDE
31 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
33 log(" equiv_opt [options] [command]\n");
35 log("This command checks circuit equivalence before and after an optimization pass.\n");
37 log(" -run <from_label>:<to_label>\n");
38 log(" only run the commands between the labels (see below). an empty\n");
39 log(" from label is synonymous to the start of the command list, and empty to\n");
40 log(" label is synonymous to the end of the command list.\n");
42 log(" -map <filename>\n");
43 log(" expand the modules in this file before proving equivalence. this is\n");
44 log(" useful for handling architecture-specific primitives.\n");
47 log(" produce an error if the circuits are not equivalent.\n");
50 log(" enable modelling of undef states during equiv_induct.\n");
52 log("The following commands are executed by this verification command:\n");
57 std::string command
, techmap_opts
;
60 void clear_flags() YS_OVERRIDE
68 void execute(std::vector
< std::string
> args
, RTLIL::Design
* design
) YS_OVERRIDE
70 string run_from
, run_to
;
74 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
75 if (args
[argidx
] == "-run" && argidx
+ 1 < args
.size()) {
76 size_t pos
= args
[argidx
+ 1].find(':');
77 if (pos
== std::string::npos
)
79 run_from
= args
[++argidx
].substr(0, pos
);
80 run_to
= args
[argidx
].substr(pos
+ 1);
83 if (args
[argidx
] == "-map" && argidx
+ 1 < args
.size()) {
84 techmap_opts
+= " -map " + args
[++argidx
];
87 if (args
[argidx
] == "-assert") {
91 if (args
[argidx
] == "-undef") {
98 for (; argidx
< args
.size(); argidx
++) {
99 if (command
.empty()) {
100 if (args
[argidx
].compare(0, 1, "-") == 0)
101 cmd_error(args
, argidx
, "Unknown option.");
105 command
+= args
[argidx
];
109 log_cmd_error("No optimization pass specified!\n");
111 if (!design
->full_selection())
112 log_cmd_error("This command only operates on fully selected designs!\n");
114 log_header(design
, "Executing EQUIV_OPT pass.\n");
117 run_script(design
, run_from
, run_to
);
122 void script() YS_OVERRIDE
124 if (check_label("run_pass")) {
125 run("hierarchy -auto-top");
126 run("design -save preopt");
131 run("design -stash postopt");
134 if (check_label("prepare")) {
135 run("design -copy-from preopt -as gold A:top");
136 run("design -copy-from postopt -as gate A:top");
139 if ((!techmap_opts
.empty() || help_mode
) && check_label("techmap", "(only with -map)")) {
142 opts
= " -map <filename> ...";
145 run("techmap -wb -D EQUIV -autoproc" + opts
);
148 if (check_label("prove")) {
149 run("equiv_make gold gate equiv");
151 run("equiv_induct [-undef] equiv");
153 run("equiv_induct -undef equiv");
155 run("equiv_induct equiv");
157 run("equiv_status [-assert] equiv");
159 run("equiv_status -assert equiv");
161 run("equiv_status equiv");
164 if (check_label("restore")) {
165 run("design -load preopt");
170 PRIVATE_NAMESPACE_END