Restore part of doc
[yosys.git] / passes / equiv / equiv_opt.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2018 whitequark <whitequark@whitequark.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21
22 USING_YOSYS_NAMESPACE
23 PRIVATE_NAMESPACE_BEGIN
24
25 struct EquivOptPass:public ScriptPass
26 {
27 EquivOptPass() : ScriptPass("equiv_opt", "prove equivalence for optimized circuit") { }
28
29 void help() YS_OVERRIDE
30 {
31 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
32 log("\n");
33 log(" equiv_opt [options] [command]\n");
34 log("\n");
35 log("This command uses temporal induction to check circuit equivalence before and\n");
36 log("after an optimization pass.\n");
37 log("\n");
38 log(" -run <from_label>:<to_label>\n");
39 log(" only run the commands between the labels (see below). an empty\n");
40 log(" from label is synonymous to the start of the command list, and empty to\n");
41 log(" label is synonymous to the end of the command list.\n");
42 log("\n");
43 log(" -map <filename>\n");
44 log(" expand the modules in this file before proving equivalence. this is\n");
45 log(" useful for handling architecture-specific primitives.\n");
46 log("\n");
47 log(" -assert\n");
48 log(" produce an error if the circuits are not equivalent.\n");
49 log("\n");
50 log(" -multiclock\n");
51 log(" run clk2fflogic before equivalence checking.\n");
52 log("\n");
53 log(" -undef\n");
54 log(" enable modelling of undef states during equiv_induct.\n");
55 log("\n");
56 log("The following commands are executed by this verification command:\n");
57 help_script();
58 log("\n");
59 }
60
61 std::string command, techmap_opts;
62 bool assert, undef, multiclock, async2sync;
63
64 void clear_flags() YS_OVERRIDE
65 {
66 command = "";
67 techmap_opts = "";
68 assert = false;
69 undef = false;
70 multiclock = false;
71 async2sync = false;
72 }
73
74 void execute(std::vector < std::string > args, RTLIL::Design * design) YS_OVERRIDE
75 {
76 string run_from, run_to;
77 clear_flags();
78
79 size_t argidx;
80 for (argidx = 1; argidx < args.size(); argidx++) {
81 if (args[argidx] == "-run" && argidx + 1 < args.size()) {
82 size_t pos = args[argidx + 1].find(':');
83 if (pos == std::string::npos)
84 break;
85 run_from = args[++argidx].substr(0, pos);
86 run_to = args[argidx].substr(pos + 1);
87 continue;
88 }
89 if (args[argidx] == "-map" && argidx + 1 < args.size()) {
90 techmap_opts += " -map " + args[++argidx];
91 continue;
92 }
93 if (args[argidx] == "-assert") {
94 assert = true;
95 continue;
96 }
97 if (args[argidx] == "-undef") {
98 undef = true;
99 continue;
100 }
101 if (args[argidx] == "-multiclock") {
102 multiclock = true;
103 continue;
104 }
105 if (args[argidx] == "-async2sync") {
106 async2sync = true;
107 continue;
108 }
109 break;
110 }
111
112 for (; argidx < args.size(); argidx++) {
113 if (command.empty()) {
114 if (args[argidx].compare(0, 1, "-") == 0)
115 cmd_error(args, argidx, "Unknown option.");
116 } else {
117 command += " ";
118 }
119 command += args[argidx];
120 }
121
122 if (command.empty())
123 log_cmd_error("No optimization pass specified!\n");
124
125 if (!design->full_selection())
126 log_cmd_error("This command only operates on fully selected designs!\n");
127
128 if (async2sync && multiclock)
129 log_cmd_error("The '-async2sync' and '-multiclock' options are mutually exclusive!\n");
130
131 log_header(design, "Executing EQUIV_OPT pass.\n");
132 log_push();
133
134 run_script(design, run_from, run_to);
135
136 log_pop();
137 }
138
139 void script() YS_OVERRIDE
140 {
141 if (check_label("run_pass")) {
142 run("hierarchy -auto-top");
143 run("design -save preopt");
144 if (help_mode)
145 run("[command]");
146 else
147 run(command);
148 run("design -stash postopt");
149 }
150
151 if (check_label("prepare")) {
152 run("design -copy-from preopt -as gold A:top");
153 run("design -copy-from postopt -as gate A:top");
154 }
155
156 if ((!techmap_opts.empty() || help_mode) && check_label("techmap", "(only with -map)")) {
157 string opts;
158 if (help_mode)
159 opts = " -map <filename> ...";
160 else
161 opts = techmap_opts;
162 run("techmap -wb -D EQUIV -autoproc" + opts);
163 }
164
165 if (check_label("prove")) {
166 if (multiclock || help_mode)
167 run("clk2fflogic", "(only with -multiclock)");
168 if (async2sync || help_mode)
169 run("async2sync", "(only with -async2sync)");
170 run("equiv_make gold gate equiv");
171 if (help_mode)
172 run("equiv_induct [-undef] equiv");
173 else if (undef)
174 run("equiv_induct -undef equiv");
175 else
176 run("equiv_induct equiv");
177 if (help_mode)
178 run("equiv_status [-assert] equiv");
179 else if (assert)
180 run("equiv_status -assert equiv");
181 else
182 run("equiv_status equiv");
183 }
184
185 if (check_label("restore")) {
186 run("design -load preopt");
187 }
188 }
189 } EquivOptPass;
190
191 PRIVATE_NAMESPACE_END