2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
23 PRIVATE_NAMESPACE_BEGIN
25 struct EquivRemovePass
: public Pass
{
26 EquivRemovePass() : Pass("equiv_remove", "remove $equiv cells") { }
27 void help() YS_OVERRIDE
29 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
31 log(" equiv_remove [options] [selection]\n");
33 log("This command removes the selected $equiv cells. If neither -gold nor -gate is\n");
34 log("used then only proven cells are removed.\n");
37 log(" keep gold circuit\n");
40 log(" keep gate circuit\n");
43 void execute(std::vector
<std::string
> args
, Design
*design
) YS_OVERRIDE
45 bool mode_gold
= false;
46 bool mode_gate
= false;
49 log_header(design
, "Executing EQUIV_REMOVE pass.\n");
52 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
53 if (args
[argidx
] == "-gold") {
57 if (args
[argidx
] == "-gate") {
63 extra_args(args
, argidx
, design
);
65 if (mode_gold
&& mode_gate
)
66 log_cmd_error("Options -gold and -gate are exclusive.\n");
68 for (auto module
: design
->selected_modules())
70 for (auto cell
: module
->selected_cells())
71 if (cell
->type
== "$equiv" && (mode_gold
|| mode_gate
|| cell
->getPort("\\A") == cell
->getPort("\\B"))) {
72 log("Removing $equiv cell %s.%s (%s).\n", log_id(module
), log_id(cell
), log_signal(cell
->getPort("\\Y")));
73 module
->connect(cell
->getPort("\\Y"), mode_gate
? cell
->getPort("\\B") : cell
->getPort("\\A"));
79 log("Removed a total of %d $equiv cells.\n", remove_count
);