Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"
[yosys.git] / passes / equiv / equiv_status.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21
22 USING_YOSYS_NAMESPACE
23 PRIVATE_NAMESPACE_BEGIN
24
25 struct EquivStatusPass : public Pass {
26 EquivStatusPass() : Pass("equiv_status", "print status of equivalent checking module") { }
27 void help() YS_OVERRIDE
28 {
29 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
30 log("\n");
31 log(" equiv_status [options] [selection]\n");
32 log("\n");
33 log("This command prints status information for all selected $equiv cells.\n");
34 log("\n");
35 log(" -assert\n");
36 log(" produce an error if any unproven $equiv cell is found\n");
37 log("\n");
38 }
39 void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
40 {
41 bool assert_mode = false;
42 int unproven_count = 0;
43
44 log_header(design, "Executing EQUIV_STATUS pass.\n");
45
46 size_t argidx;
47 for (argidx = 1; argidx < args.size(); argidx++) {
48 if (args[argidx] == "-assert") {
49 assert_mode = true;
50 continue;
51 }
52 break;
53 }
54 extra_args(args, argidx, design);
55
56 for (auto module : design->selected_modules())
57 {
58 vector<Cell*> unproven_equiv_cells;
59 int proven_equiv_cells = 0;
60
61 for (auto cell : module->selected_cells())
62 if (cell->type == ID($equiv)) {
63 if (cell->getPort(ID::A) != cell->getPort(ID::B))
64 unproven_equiv_cells.push_back(cell);
65 else
66 proven_equiv_cells++;
67 }
68
69 if (unproven_equiv_cells.empty() && !proven_equiv_cells) {
70 log("No $equiv cells found in %s.\n", log_id(module));
71 continue;
72 }
73
74 log("Found %d $equiv cells in %s:\n", GetSize(unproven_equiv_cells) + proven_equiv_cells, log_id(module));
75 log(" Of those cells %d are proven and %d are unproven.\n", proven_equiv_cells, GetSize(unproven_equiv_cells));
76 if (unproven_equiv_cells.empty()) {
77 log(" Equivalence successfully proven!\n");
78 } else {
79 for (auto cell : unproven_equiv_cells)
80 log(" Unproven $equiv %s: %s %s\n", log_id(cell), log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
81 }
82
83 unproven_count += GetSize(unproven_equiv_cells);
84 }
85
86 if (unproven_count != 0) {
87 log("Found a total of %d unproven $equiv cells.\n", unproven_count);
88 if (assert_mode && unproven_count != 0)
89 log_error("Found %d unproven $equiv cells in 'equiv_status -assert'.\n", unproven_count);
90 }
91 }
92 } EquivStatusPass;
93
94 PRIVATE_NAMESPACE_END