2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/log.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/consteval.h"
24 #include "kernel/celltypes.h"
27 static RTLIL::Module
*module
;
28 static SigMap assign_map
;
29 typedef std::pair
<RTLIL::Cell
*,std::string
> sig2driver_entry_t
;
30 static SigSet
<sig2driver_entry_t
> sig2driver
, sig2user
;
31 static std::set
<RTLIL::Cell
*> muxtree_cells
;
32 static SigPool sig_at_port
;
34 static bool check_state_mux_tree(RTLIL::SigSpec old_sig
, RTLIL::SigSpec sig
, SigPool
&recursion_monitor
)
36 if (sig_at_port
.check_any(assign_map(sig
)))
39 if (sig
.is_fully_const() || old_sig
== sig
)
42 if (recursion_monitor
.check_any(sig
)) {
43 log("Warning: logic loop in mux tree at signal %s in module %s.\n",
44 log_signal(sig
), RTLIL::id2cstr(module
->name
));
48 recursion_monitor
.add(sig
);
50 std::set
<sig2driver_entry_t
> cellport_list
;
51 sig2driver
.find(sig
, cellport_list
);
52 for (auto &cellport
: cellport_list
) {
53 if ((cellport
.first
->type
!= "$mux" && cellport
.first
->type
!= "$pmux" && cellport
.first
->type
!= "$safe_pmux") || cellport
.second
!= "\\Y")
55 RTLIL::SigSpec sig_a
= assign_map(cellport
.first
->connections
["\\A"]);
56 RTLIL::SigSpec sig_b
= assign_map(cellport
.first
->connections
["\\B"]);
57 if (!check_state_mux_tree(old_sig
, sig_a
, recursion_monitor
))
59 for (int i
= 0; i
< sig_b
.size(); i
+= sig_a
.size())
60 if (!check_state_mux_tree(old_sig
, sig_b
.extract(i
, sig_a
.size()), recursion_monitor
))
62 muxtree_cells
.insert(cellport
.first
);
65 recursion_monitor
.del(sig
);
70 static bool check_state_users(RTLIL::SigSpec sig
)
72 if (sig_at_port
.check_any(assign_map(sig
)))
75 std::set
<sig2driver_entry_t
> cellport_list
;
76 sig2user
.find(sig
, cellport_list
);
77 for (auto &cellport
: cellport_list
) {
78 RTLIL::Cell
*cell
= cellport
.first
;
79 if (muxtree_cells
.count(cell
) > 0)
81 if (cellport
.second
!= "\\A" && cellport
.second
!= "\\B")
83 if (cell
->connections
.count("\\A") == 0 || cell
->connections
.count("\\B") == 0 || cell
->connections
.count("\\Y") == 0)
85 for (auto &port_it
: cell
->connections
)
86 if (port_it
.first
!= "\\A" && port_it
.first
!= "\\B" && port_it
.first
!= "\\Y")
88 if (assign_map(cell
->connections
["\\A"]) == sig
&& cell
->connections
["\\B"].is_fully_const())
90 if (assign_map(cell
->connections
["\\B"]) == sig
&& cell
->connections
["\\A"].is_fully_const())
98 static void detect_fsm(RTLIL::Wire
*wire
)
100 if (wire
->attributes
.count("\\fsm_encoding") > 0 || wire
->width
<= 1)
102 if (sig_at_port
.check_any(assign_map(RTLIL::SigSpec(wire
))))
105 std::set
<sig2driver_entry_t
> cellport_list
;
106 sig2driver
.find(RTLIL::SigSpec(wire
), cellport_list
);
107 for (auto &cellport
: cellport_list
) {
108 if ((cellport
.first
->type
!= "$dff" && cellport
.first
->type
!= "$adff") || cellport
.second
!= "\\Q")
110 muxtree_cells
.clear();
111 SigPool recursion_monitor
;
112 RTLIL::SigSpec sig_q
= assign_map(cellport
.first
->connections
["\\Q"]);
113 RTLIL::SigSpec sig_d
= assign_map(cellport
.first
->connections
["\\D"]);
114 if (sig_q
== RTLIL::SigSpec(wire
) && check_state_mux_tree(sig_q
, sig_d
, recursion_monitor
) && check_state_users(sig_q
)) {
115 log("Found FSM state register %s in module %s.\n", wire
->name
.c_str(), module
->name
.c_str());
116 wire
->attributes
["\\fsm_encoding"] = RTLIL::Const("auto");
122 struct FsmDetectPass
: public Pass
{
123 FsmDetectPass() : Pass("fsm_detect", "finding FSMs in design") { }
126 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
128 log(" fsm_detect [selection]\n");
130 log("This pass detects finite state machines by identifying the state signal.\n");
131 log("The state signal is then marked by setting the attribute 'fsm_encoding'\n");
132 log("on the state signal to \"auto\".\n");
134 log("Existing 'fsm_encoding' attributes are not changed by this pass.\n");
136 log("Signals can be protected from being detected by this pass by setting the\n");
137 log("'fsm_encoding' attribute to \"none\".\n");
140 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
142 log_header("Executing FSM_DETECT pass (finding FSMs in design).\n");
143 extra_args(args
, 1, design
);
146 ct
.setup_internals();
147 ct
.setup_internals_mem();
149 ct
.setup_stdcells_mem();
151 for (auto &mod_it
: design
->modules
)
153 if (!design
->selected(mod_it
.second
))
156 module
= mod_it
.second
;
157 assign_map
.set(module
);
162 for (auto &cell_it
: module
->cells
)
163 for (auto &conn_it
: cell_it
.second
->connections
) {
164 if (ct
.cell_output(cell_it
.second
->type
, conn_it
.first
) || !ct
.cell_known(cell_it
.second
->type
)) {
165 RTLIL::SigSpec sig
= conn_it
.second
;
166 assign_map
.apply(sig
);
167 sig2driver
.insert(sig
, sig2driver_entry_t(cell_it
.second
, conn_it
.first
));
169 if (!ct
.cell_known(cell_it
.second
->type
) || ct
.cell_input(cell_it
.second
->type
, conn_it
.first
)) {
170 RTLIL::SigSpec sig
= conn_it
.second
;
171 assign_map
.apply(sig
);
172 sig2user
.insert(sig
, sig2driver_entry_t(cell_it
.second
, conn_it
.first
));
176 for (auto &wire_it
: module
->wires
)
177 if (wire_it
.second
->port_id
!= 0)
178 sig_at_port
.add(assign_map(RTLIL::SigSpec(wire_it
.second
)));
180 for (auto &wire_it
: module
->wires
)
181 if (design
->selected(module
, wire_it
.second
))
182 detect_fsm(wire_it
.second
);
188 muxtree_cells
.clear();