Replaced RTLIL::Const::str with generic decoder method
[yosys.git] / passes / fsm / fsm_export.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2012 Martin Schmölzer <martin@schmoelzer.at>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/log.h"
22 #include "kernel/register.h"
23 #include "kernel/sigtools.h"
24 #include "kernel/consteval.h"
25 #include "kernel/celltypes.h"
26 #include "fsmdata.h"
27 #include <string>
28 #include <iostream>
29 #include <fstream>
30
31 /**
32 * Convert a signal into a KISS-compatible textual representation.
33 */
34 std::string kiss_convert_signal(const RTLIL::SigSpec &sig) {
35 if (!sig.is_fully_const()) {
36 throw 0;
37 }
38
39 return sig.as_const().as_string();
40 }
41
42 /**
43 * Create a KISS2 file from a cell.
44 *
45 * The destination file name is taken from the fsm_export attribute if present,
46 * e.g. (* fsm_export="filename.kiss2" *). If this attribute is not present,
47 * the file name will be assembled from the module and cell names.
48 *
49 * @param module pointer to module which contains the FSM cell.
50 * @param cell pointer to the FSM cell which should be exported.
51 */
52 void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::string filename, bool origenc) {
53 std::map<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
54 FsmData fsm_data;
55 FsmData::transition_t tr;
56 std::ofstream kiss_file;
57 std::string kiss_name;
58 size_t i;
59
60 attr_it = cell->attributes.find("\\fsm_export");
61 if (!filename.empty()) {
62 kiss_name.assign(filename);
63 } else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") {
64 kiss_name.assign(attr_it->second.decode_string());
65 }
66 else {
67 kiss_name.assign(module->name);
68 kiss_name.append('-' + cell->name + ".kiss2");
69 }
70
71 log("\n");
72 log("Exporting FSM `%s' from module `%s' to file `%s'.\n",
73 cell->name.c_str(),
74 module->name.c_str(),
75 kiss_name.c_str());
76
77 kiss_file.open(kiss_name, std::ios::out | std::ios::trunc);
78
79 if (!kiss_file.is_open()) {
80 log_error("Could not open file \"%s\" with write access.\n", kiss_name.c_str());
81 }
82
83 fsm_data.copy_from_cell(cell);
84
85 kiss_file << ".i " << std::dec << fsm_data.num_inputs << std::endl;
86 kiss_file << ".o " << std::dec << fsm_data.num_outputs << std::endl;
87 kiss_file << ".p " << std::dec << fsm_data.transition_table.size() << std::endl;
88 kiss_file << ".s " << std::dec << fsm_data.state_table.size() << std::endl;
89 if (origenc) {
90 kiss_file << ".r " << kiss_convert_signal(fsm_data.state_table[fsm_data.reset_state]) << std::endl;
91 } else {
92 kiss_file << ".r s" << std::dec << fsm_data.reset_state << std::endl;
93 }
94
95 for (i = 0; i < fsm_data.transition_table.size(); i++) {
96 tr = fsm_data.transition_table[i];
97
98 try {
99 kiss_file << kiss_convert_signal(tr.ctrl_in) << ' ';
100 if (origenc) {
101 kiss_file << kiss_convert_signal(fsm_data.state_table[tr.state_in]) << ' ';
102 kiss_file << kiss_convert_signal(fsm_data.state_table[tr.state_out]) << ' ';
103 } else {
104 kiss_file << 's' << tr.state_in << ' ';
105 kiss_file << 's' << tr.state_out << ' ';
106 }
107 kiss_file << kiss_convert_signal(tr.ctrl_out) << std::endl;
108 }
109 catch (int) {
110 kiss_file.close();
111 log_error("exporting an FSM input or output signal failed.\n");
112 }
113 }
114
115 kiss_file.close();
116 }
117
118 /**
119 * Exports Finite State Machines in the design to one file per FSM. Currently,
120 * only the KISS2 file format is supported.
121 */
122 struct FsmExportPass : public Pass {
123 FsmExportPass() : Pass("fsm_export", "exporting FSMs to KISS2 files") { }
124 virtual void help()
125 {
126 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
127 log("\n");
128 log(" fsm_export [-noauto] [-o filename] [-origenc] [selection]\n");
129 log("\n");
130 log("This pass creates a KISS2 file for every selected FSM. For FSMs with the\n");
131 log("'fsm_export' attribute set, the attribute value is used as filename, otherwise\n");
132 log("the module and cell name is used as filename. If the parameter '-o' is given,\n");
133 log("the first exported FSM is written to the specified filename. This overwrites\n");
134 log("the setting as specified with the 'fsm_export' attribute. All other FSMs are\n");
135 log("exported to the default name as mentioned above.\n");
136 log("\n");
137 log(" -noauto\n");
138 log(" only export FSMs that have the 'fsm_export' attribute set\n");
139 log("\n");
140 log(" -o filename\n");
141 log(" filename of the first exported FSM\n");
142 log("\n");
143 log(" -origenc\n");
144 log(" use binary state encoding as state names instead of s0, s1, ...\n");
145 log("\n");
146 }
147 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
148 {
149 std::map<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
150 std::string arg;
151 bool flag_noauto = false;
152 std::string filename;
153 bool flag_origenc = false;
154 size_t argidx;
155
156 log_header("Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n");
157
158 for (argidx = 1; argidx < args.size(); argidx++) {
159 arg = args[argidx];
160 if (arg == "-noauto") {
161 flag_noauto = true;
162 continue;
163 }
164 if (arg == "-o") {
165 argidx++;
166 filename = args[argidx];
167 continue;
168 }
169 if (arg == "-origenc") {
170 flag_origenc = true;
171 continue;
172 }
173 break;
174 }
175 extra_args(args, argidx, design);
176
177 for (auto &mod_it : design->modules)
178 if (design->selected(mod_it.second))
179 for (auto &cell_it : mod_it.second->cells)
180 if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
181 attr_it = cell_it.second->attributes.find("\\fsm_export");
182 if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) {
183 write_kiss2(mod_it.second, cell_it.second, filename, flag_origenc);
184 filename.clear();
185 }
186 }
187 }
188 } FsmExportPass;