Merge remote-tracking branch 'upstream/master'
[yosys.git] / passes / fsm / fsm_export.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2012 Martin Schmölzer <martin@schmoelzer.at>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/log.h"
22 #include "kernel/register.h"
23 #include "kernel/sigtools.h"
24 #include "kernel/consteval.h"
25 #include "kernel/celltypes.h"
26 #include "fsmdata.h"
27 #include <string>
28 #include <iostream>
29 #include <fstream>
30
31 /**
32 * Convert a signal into a KISS-compatible textual representation.
33 */
34 std::string kiss_convert_signal(const RTLIL::SigSpec &sig) {
35 if (!sig.is_fully_const()) {
36 throw 0;
37 }
38
39 return sig.as_const().as_string();
40 }
41
42 /**
43 * Create a KISS2 file from a cell.
44 *
45 * The destination file name is taken from the fsm_export attribute if present,
46 * e.g. (* fsm_export="filename.kiss2" *). If this attribute is not present,
47 * the file name will be assembled from the module and cell names.
48 *
49 * @param module pointer to module which contains the FSM cell.
50 * @param cell pointer to the FSM cell which should be exported.
51 */
52 void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell) {
53 std::map<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
54 FsmData fsm_data;
55 FsmData::transition_t tr;
56 std::ofstream kiss_file;
57 std::string kiss_name;
58 size_t i;
59
60 attr_it = cell->attributes.find("\\fsm_export");
61 if (attr_it != cell->attributes.end() && attr_it->second.str != "") {
62 kiss_name.assign(attr_it->second.str);
63 }
64 else {
65 kiss_name.assign(module->name);
66 kiss_name.append('-' + cell->name + ".kiss2");
67 }
68
69 log("\n");
70 log("Exporting FSM `%s' from module `%s' to file `%s'.\n",
71 cell->name.c_str(),
72 module->name.c_str(),
73 kiss_name.c_str());
74
75 kiss_file.open(kiss_name, std::ios::out | std::ios::trunc);
76
77 if (!kiss_file.is_open()) {
78 log_error("Could not open file \"%s\" with write access.\n", kiss_name.c_str());
79 }
80
81 fsm_data.copy_from_cell(cell);
82
83 kiss_file << ".start_kiss" << std::endl;
84 kiss_file << ".i " << std::dec << fsm_data.num_inputs << std::endl;
85 kiss_file << ".o " << std::dec << fsm_data.num_outputs << std::endl;
86 kiss_file << ".r s" << std::dec << fsm_data.reset_state << std::endl;
87
88 for (i = 0; i < fsm_data.transition_table.size(); i++) {
89 tr = fsm_data.transition_table[i];
90
91 try {
92 kiss_file << kiss_convert_signal(tr.ctrl_in) << ' ';
93 kiss_file << 's' << tr.state_in << ' ';
94 kiss_file << 's' << tr.state_out << ' ';
95 kiss_file << kiss_convert_signal(tr.ctrl_out) << std::endl;
96 }
97 catch (int) {
98 kiss_file.close();
99 log_error("exporting an FSM input or output signal failed.\n");
100 }
101 }
102
103 kiss_file << ".end_kiss" << std::endl << ".end" << std::endl;
104 kiss_file.close();
105 }
106
107 /**
108 * Exports Finite State Machines in the design to one file per FSM. Currently,
109 * only the KISS2 file format is supported.
110 */
111 struct FsmExportPass : public Pass {
112 FsmExportPass() : Pass("fsm_export") {
113 }
114
115 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
116 {
117 std::map<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
118 std::string arg;
119 bool flag_noauto = false;
120 size_t argidx;
121
122 log_header("Executing FSM_EXPORT pass (exporting FSMs in KISS2 file format).\n");
123
124 for (argidx = 1; argidx < args.size(); argidx++) {
125 arg = args[argidx];
126 if (arg == "-noauto") {
127 flag_noauto = true;
128 continue;
129 }
130 break;
131 }
132 extra_args(args, argidx, design);
133
134 for (auto &mod_it : design->modules)
135 for (auto &cell_it : mod_it.second->cells)
136 if (cell_it.second->type == "$fsm") {
137 attr_it = cell_it.second->attributes.find("\\fsm_export");
138 if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) {
139 write_kiss2(mod_it.second, cell_it.second);
140 }
141 }
142 }
143 } FsmExportPass;