passes/fsm/fsm_info.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/log.h"
  21 #include "kernel/register.h"
  22 #include "kernel/sigtools.h"
  23 #include "kernel/consteval.h"
  24 #include "kernel/celltypes.h"
  25 #include "fsmdata.h"
  26 #include <string.h>
  27
  28 USING_YOSYS_NAMESPACE
  29 PRIVATE_NAMESPACE_BEGIN
  30
  31 struct FsmInfoPass : public Pass {
  32         FsmInfoPass() : Pass("fsm_info", "print information on finite state machines") { }
  33         void help() YS_OVERRIDE
  34         {
  35                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  36                 log("\n");
  37                 log("    fsm_info [selection]\n");
  38                 log("\n");
  39                 log("This pass dumps all internal information on FSM cells. It can be useful for\n");
  40                 log("analyzing the synthesis process and is called automatically by the 'fsm'\n");
  41                 log("pass so that this information is included in the synthesis log file.\n");
  42                 log("\n");
  43         }
  44         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  45         {
  46                 log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
  47                 extra_args(args, 1, design);
  48
  49                 for (auto &mod_it : design->modules_)
  50                         if (design->selected(mod_it.second))
  51                                 for (auto &cell_it : mod_it.second->cells_)
  52                                         if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
  53                                                 log("\n");
  54                                                 log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str());
  55                                                 FsmData fsm_data;
  56                                                 fsm_data.copy_from_cell(cell_it.second);
  57                                                 fsm_data.log_info(cell_it.second);
  58                                         }
  59         }
  60 } FsmInfoPass;
  61
  62 PRIVATE_NAMESPACE_END