2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/log.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/consteval.h"
24 #include "kernel/celltypes.h"
29 PRIVATE_NAMESPACE_BEGIN
31 struct FsmInfoPass
: public Pass
{
32 FsmInfoPass() : Pass("fsm_info", "print information on finite state machines") { }
33 void help() YS_OVERRIDE
35 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
37 log(" fsm_info [selection]\n");
39 log("This pass dumps all internal information on FSM cells. It can be useful for\n");
40 log("analyzing the synthesis process and is called automatically by the 'fsm'\n");
41 log("pass so that this information is included in the synthesis log file.\n");
44 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
46 log_header(design
, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
47 extra_args(args
, 1, design
);
49 for (auto mod
: design
->selected_modules())
50 for (auto cell
: mod
->selected_cells())
51 if (cell
->type
== ID($fsm
)) {
53 log("FSM `%s' from module `%s':\n", log_id(cell
), log_id(mod
));
55 fsm_data
.copy_from_cell(cell
);
56 fsm_data
.log_info(cell
);