2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/log.h"
29 struct generate_port_decl_t
{
36 static void generate(RTLIL::Design
*design
, const std::vector
<std::string
> &celltypes
, const std::vector
<generate_port_decl_t
> &portdecls
)
38 std::set
<std::string
> found_celltypes
;
40 for (auto i1
: design
->modules
)
41 for (auto i2
: i1
.second
->cells_
)
43 RTLIL::Cell
*cell
= i2
.second
;
44 if (cell
->type
[0] == '$' || design
->modules
.count(cell
->type
) > 0)
46 for (auto &pattern
: celltypes
)
47 if (!fnmatch(pattern
.c_str(), RTLIL::unescape_id(cell
->type
).c_str(), FNM_NOESCAPE
))
48 found_celltypes
.insert(cell
->type
);
51 for (auto &celltype
: found_celltypes
)
53 std::set
<std::string
> portnames
;
54 std::set
<std::string
> parameters
;
55 std::map
<std::string
, int> portwidths
;
56 log("Generate module for cell type %s:\n", celltype
.c_str());
58 for (auto i1
: design
->modules
)
59 for (auto i2
: i1
.second
->cells_
)
60 if (i2
.second
->type
== celltype
) {
61 for (auto &conn
: i2
.second
->connections()) {
62 if (conn
.first
[0] != '$')
63 portnames
.insert(conn
.first
);
64 portwidths
[conn
.first
] = std::max(portwidths
[conn
.first
], conn
.second
.size());
66 for (auto ¶
: i2
.second
->parameters
)
67 parameters
.insert(para
.first
);
70 for (auto &decl
: portdecls
)
72 portnames
.insert(decl
.portname
);
74 std::set
<int> indices
;
75 for (int i
= 0; i
< int(portnames
.size()); i
++)
78 std::vector
<generate_port_decl_t
> ports(portnames
.size());
80 for (auto &decl
: portdecls
)
82 portwidths
[decl
.portname
] = std::max(portwidths
[decl
.portname
], 1);
83 portwidths
[decl
.portname
] = std::max(portwidths
[decl
.portname
], portwidths
[stringf("$%d", decl
.index
)]);
84 log(" port %d: %s [%d:0] %s\n", decl
.index
, decl
.input
? decl
.output
? "inout" : "input" : "output", portwidths
[decl
.portname
]-1, RTLIL::id2cstr(decl
.portname
));
85 if (indices
.count(decl
.index
) > ports
.size())
86 log_error("Port index (%d) exceeds number of found ports (%d).\n", decl
.index
, int(ports
.size()));
87 if (indices
.count(decl
.index
) == 0)
88 log_error("Conflict on port index %d.\n", decl
.index
);
89 indices
.erase(decl
.index
);
90 portnames
.erase(decl
.portname
);
91 ports
[decl
.index
-1] = decl
;
94 while (portnames
.size() > 0) {
95 std::string portname
= *portnames
.begin();
96 for (auto &decl
: portdecls
)
97 if (decl
.index
== 0 && !fnmatch(decl
.portname
.c_str(), RTLIL::unescape_id(portname
).c_str(), FNM_NOESCAPE
)) {
98 generate_port_decl_t d
= decl
;
99 d
.portname
= portname
;
100 d
.index
= *indices
.begin();
101 assert(!indices
.empty());
102 indices
.erase(d
.index
);
103 ports
[d
.index
-1] = d
;
104 portwidths
[d
.portname
] = std::max(portwidths
[d
.portname
], 1);
105 log(" port %d: %s [%d:0] %s\n", d
.index
, d
.input
? d
.output
? "inout" : "input" : "output", portwidths
[d
.portname
]-1, RTLIL::id2cstr(d
.portname
));
106 goto found_matching_decl
;
108 log_error("Can't match port %s.\n", RTLIL::id2cstr(portname
));
109 found_matching_decl
:;
110 portnames
.erase(portname
);
113 assert(indices
.empty());
115 RTLIL::Module
*mod
= new RTLIL::Module
;
116 mod
->name
= celltype
;
117 mod
->attributes
["\\blackbox"] = RTLIL::Const(1);
118 design
->modules
[mod
->name
] = mod
;
120 for (auto &decl
: ports
) {
121 RTLIL::Wire
*wire
= mod
->addWire(decl
.portname
, portwidths
.at(decl
.portname
));
122 wire
->port_id
= decl
.index
;
123 wire
->port_input
= decl
.input
;
124 wire
->port_output
= decl
.output
;
127 for (auto ¶
: parameters
)
128 log(" ignoring parameter %s.\n", RTLIL::id2cstr(para
));
130 log(" module %s created.\n", RTLIL::id2cstr(mod
->name
));
134 static bool expand_module(RTLIL::Design
*design
, RTLIL::Module
*module
, bool flag_check
, std::vector
<std::string
> &libdirs
)
136 bool did_something
= false;
137 std::map
<RTLIL::Cell
*, std::pair
<int, int>> array_cells
;
138 std::string filename
;
140 for (auto &cell_it
: module
->cells_
)
142 RTLIL::Cell
*cell
= cell_it
.second
;
144 if (cell
->type
.substr(0, 7) == "$array:") {
145 int pos_idx
= cell
->type
.find_first_of(':');
146 int pos_num
= cell
->type
.find_first_of(':', pos_idx
+ 1);
147 int pos_type
= cell
->type
.find_first_of(':', pos_num
+ 1);
148 int idx
= atoi(cell
->type
.substr(pos_idx
+ 1, pos_num
).c_str());
149 int num
= atoi(cell
->type
.substr(pos_num
+ 1, pos_type
).c_str());
150 array_cells
[cell
] = std::pair
<int, int>(idx
, num
);
151 cell
->type
= cell
->type
.substr(pos_type
+ 1);
154 if (design
->modules
.count(cell
->type
) == 0)
156 if (design
->modules
.count("$abstract" + cell
->type
))
158 cell
->type
= design
->modules
.at("$abstract" + cell
->type
)->derive(design
, cell
->parameters
);
159 cell
->parameters
.clear();
160 did_something
= true;
164 if (cell
->type
[0] == '$')
167 for (auto &dir
: libdirs
)
169 filename
= dir
+ "/" + RTLIL::unescape_id(cell
->type
) + ".v";
170 if (access(filename
.c_str(), F_OK
) == 0) {
171 std::vector
<std::string
> args
;
172 args
.push_back(filename
);
173 Frontend::frontend_call(design
, NULL
, filename
, "verilog");
177 filename
= dir
+ "/" + RTLIL::unescape_id(cell
->type
) + ".il";
178 if (access(filename
.c_str(), F_OK
) == 0) {
179 std::vector
<std::string
> args
;
180 args
.push_back(filename
);
181 Frontend::frontend_call(design
, NULL
, filename
, "ilang");
186 if (flag_check
&& cell
->type
[0] != '$')
187 log_error("Module `%s' referenced in module `%s' in cell `%s' is not part of the design.\n",
188 cell
->type
.c_str(), module
->name
.c_str(), cell
->name
.c_str());
192 if (design
->modules
.count(cell
->type
) == 0)
193 log_error("File `%s' from libdir does not declare module `%s'.\n", filename
.c_str(), cell
->type
.c_str());
194 did_something
= true;
197 if (cell
->parameters
.size() == 0)
200 if (design
->modules
.at(cell
->type
)->get_bool_attribute("\\blackbox"))
203 RTLIL::Module
*mod
= design
->modules
[cell
->type
];
204 cell
->type
= mod
->derive(design
, cell
->parameters
);
205 cell
->parameters
.clear();
206 did_something
= true;
209 for (auto &it
: array_cells
)
211 RTLIL::Cell
*cell
= it
.first
;
212 int idx
= it
.second
.first
, num
= it
.second
.second
;
214 if (design
->modules
.count(cell
->type
) == 0)
215 log_error("Array cell `%s.%s' of unkown type `%s'.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(cell
->type
));
217 RTLIL::Module
*mod
= design
->modules
[cell
->type
];
219 for (auto &conn
: cell
->connections_
) {
220 int conn_size
= conn
.second
.size();
221 std::string portname
= conn
.first
;
222 if (portname
.substr(0, 1) == "$") {
223 int port_id
= atoi(portname
.substr(1).c_str());
224 for (auto &wire_it
: mod
->wires_
)
225 if (wire_it
.second
->port_id
== port_id
) {
226 portname
= wire_it
.first
;
230 if (mod
->wires_
.count(portname
) == 0)
231 log_error("Array cell `%s.%s' connects to unkown port `%s'.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(conn
.first
));
232 int port_size
= mod
->wires_
.at(portname
)->width
;
233 if (conn_size
== port_size
)
235 if (conn_size
!= port_size
*num
)
236 log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(conn
.first
));
237 conn
.second
= conn
.second
.extract(port_size
*idx
, port_size
);
241 return did_something
;
244 static void hierarchy_worker(RTLIL::Design
*design
, std::set
<RTLIL::Module
*> &used
, RTLIL::Module
*mod
, int indent
)
246 if (used
.count(mod
) > 0)
250 log("Top module: %s\n", mod
->name
.c_str());
252 log("Used module: %*s%s\n", indent
, "", mod
->name
.c_str());
255 for (auto &it
: mod
->cells_
) {
256 if (design
->modules
.count(it
.second
->type
) > 0)
257 hierarchy_worker(design
, used
, design
->modules
[it
.second
->type
], indent
+4);
261 static void hierarchy(RTLIL::Design
*design
, RTLIL::Module
*top
, bool purge_lib
, bool first_pass
)
263 std::set
<RTLIL::Module
*> used
;
264 hierarchy_worker(design
, used
, top
, 0);
266 std::vector
<RTLIL::Module
*> del_modules
;
267 for (auto &it
: design
->modules
)
268 if (used
.count(it
.second
) == 0)
269 del_modules
.push_back(it
.second
);
271 for (auto mod
: del_modules
) {
272 if (first_pass
&& mod
->name
.substr(0, 9) == "$abstract")
274 if (!purge_lib
&& mod
->get_bool_attribute("\\blackbox"))
276 log("Removing unused module `%s'.\n", mod
->name
.c_str());
277 design
->modules
.erase(mod
->name
);
281 log("Removed %zd unused modules.\n", del_modules
.size());
284 struct HierarchyPass
: public Pass
{
285 HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
288 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
290 log(" hierarchy [-check] [-top <module>]\n");
291 log(" hierarchy -generate <cell-types> <port-decls>\n");
293 log("In parametric designs, a module might exists in serveral variations with\n");
294 log("different parameter values. This pass looks at all modules in the current\n");
295 log("design an re-runs the language frontends for the parametric modules as\n");
299 log(" also check the design hierarchy. this generates an error when\n");
300 log(" an unknown module is used as cell type.\n");
302 log(" -purge_lib\n");
303 log(" by default the hierarchy command will not remove library (blackbox)\n");
304 log(" module. use this options to also remove unused blackbox modules.\n");
306 log(" -libdir <directory>\n");
307 log(" search for files named <module_name>.v in the specified directory\n");
308 log(" for unkown modules and automatically run read_verilog for each\n");
309 log(" unknown module.\n");
311 log(" -keep_positionals\n");
312 log(" per default this pass also converts positional arguments in cells\n");
313 log(" to arguments using port names. this option disables this behavior.\n");
315 log(" -top <module>\n");
316 log(" use the specified top module to built a design hierarchy. modules\n");
317 log(" outside this tree (unused modules) are removed.\n");
319 log(" when the -top option is used, the 'top' attribute will be set on the\n");
320 log(" specified top module. otherwise a module with the 'top' attribute set\n");
321 log(" will implicitly be used as top module, if such a module exists.\n");
323 log("In -generate mode this pass generates blackbox modules for the given cell\n");
324 log("types (wildcards supported). For this the design is searched for cells that\n");
325 log("match the given types and then the given port declarations are used to\n");
326 log("determine the direction of the ports. The syntax for a port declaration is:\n");
328 log(" {i|o|io}[@<num>]:<portname>\n");
330 log("Input ports are specified with the 'i' prefix, output ports with the 'o'\n");
331 log("prefix and inout ports with the 'io' prefix. The optional <num> specifies\n");
332 log("the position of the port in the parameter list (needed when instanciated\n");
333 log("using positional arguments). When <num> is not specified, the <portname> can\n");
334 log("also contain wildcard characters.\n");
336 log("This pass ignores the current selection and always operates on all modules\n");
337 log("in the current design.\n");
340 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
342 log_header("Executing HIERARCHY pass (managing design hierarchy).\n");
344 bool flag_check
= false;
345 bool purge_lib
= false;
346 RTLIL::Module
*top_mod
= NULL
;
347 std::vector
<std::string
> libdirs
;
349 bool generate_mode
= false;
350 bool keep_positionals
= false;
351 std::vector
<std::string
> generate_cells
;
352 std::vector
<generate_port_decl_t
> generate_ports
;
355 for (argidx
= 1; argidx
< args
.size(); argidx
++)
357 if (args
[argidx
] == "-generate" && !flag_check
&& !top_mod
) {
358 generate_mode
= true;
359 log("Entering generate mode.\n");
360 while (++argidx
< args
.size()) {
361 const char *p
= args
[argidx
].c_str();
362 generate_port_decl_t decl
;
363 if (p
[0] == 'i' && p
[1] == 'o')
364 decl
.input
= true, decl
.output
= true, p
+= 2;
366 decl
.input
= true, decl
.output
= false, p
++;
368 decl
.input
= false, decl
.output
= true, p
++;
373 decl
.index
= strtol(++p
, &endptr
, 10);
384 log("Port declaration: %s", decl
.input
? decl
.output
? "inout" : "input" : "output");
386 log(" [at position %d]", decl
.index
);
387 log(" %s\n", decl
.portname
.c_str());
388 generate_ports
.push_back(decl
);
391 log("Celltype: %s\n", args
[argidx
].c_str());
392 generate_cells
.push_back(RTLIL::unescape_id(args
[argidx
]));
396 if (args
[argidx
] == "-check") {
400 if (args
[argidx
] == "-purge_lib") {
404 if (args
[argidx
] == "-keep_positionals") {
405 keep_positionals
= true;
408 if (args
[argidx
] == "-libdir" && argidx
+1 < args
.size()) {
409 libdirs
.push_back(args
[++argidx
]);
412 if (args
[argidx
] == "-top") {
413 if (++argidx
>= args
.size())
414 log_cmd_error("Option -top requires an additional argument!\n");
415 top_mod
= design
->modules
.count(RTLIL::escape_id(args
[argidx
])) ? design
->modules
.at(RTLIL::escape_id(args
[argidx
])) : NULL
;
416 if (top_mod
== NULL
&& design
->modules
.count("$abstract" + RTLIL::escape_id(args
[argidx
]))) {
417 std::map
<RTLIL::IdString
, RTLIL::Const
> empty_parameters
;
418 design
->modules
.at("$abstract" + RTLIL::escape_id(args
[argidx
]))->derive(design
, empty_parameters
);
419 top_mod
= design
->modules
.count(RTLIL::escape_id(args
[argidx
])) ? design
->modules
.at(RTLIL::escape_id(args
[argidx
])) : NULL
;
422 log_cmd_error("Module `%s' not found!\n", args
[argidx
].c_str());
427 extra_args(args
, argidx
, design
, false);
430 generate(design
, generate_cells
, generate_ports
);
437 for (auto &mod_it
: design
->modules
)
438 if (mod_it
.second
->get_bool_attribute("\\top"))
439 top_mod
= mod_it
.second
;
442 hierarchy(design
, top_mod
, purge_lib
, true);
444 bool did_something
= true;
445 bool did_something_once
= false;
446 while (did_something
) {
447 did_something
= false;
448 std::vector
<std::string
> modnames
;
449 modnames
.reserve(design
->modules
.size());
450 for (auto &mod_it
: design
->modules
)
451 modnames
.push_back(mod_it
.first
);
452 for (auto &modname
: modnames
) {
453 if (design
->modules
.count(modname
) == 0)
455 if (expand_module(design
, design
->modules
[modname
], flag_check
, libdirs
))
456 did_something
= true;
459 did_something_once
= true;
462 if (top_mod
!= NULL
&& did_something_once
) {
463 log_header("Re-running hierarchy analysis..\n");
464 hierarchy(design
, top_mod
, purge_lib
, false);
467 if (top_mod
!= NULL
) {
468 for (auto &mod_it
: design
->modules
)
469 if (mod_it
.second
== top_mod
)
470 mod_it
.second
->attributes
["\\top"] = RTLIL::Const(1);
472 mod_it
.second
->attributes
.erase("\\top");
475 if (!keep_positionals
)
477 std::set
<RTLIL::Module
*> pos_mods
;
478 std::map
<std::pair
<RTLIL::Module
*,int>, RTLIL::IdString
> pos_map
;
479 std::vector
<std::pair
<RTLIL::Module
*,RTLIL::Cell
*>> pos_work
;
481 for (auto &mod_it
: design
->modules
)
482 for (auto &cell_it
: mod_it
.second
->cells_
) {
483 RTLIL::Cell
*cell
= cell_it
.second
;
484 if (design
->modules
.count(cell
->type
) == 0)
486 for (auto &conn
: cell
->connections())
487 if (conn
.first
[0] == '$' && '0' <= conn
.first
[1] && conn
.first
[1] <= '9') {
488 pos_mods
.insert(design
->modules
.at(cell
->type
));
489 pos_work
.push_back(std::pair
<RTLIL::Module
*,RTLIL::Cell
*>(mod_it
.second
, cell
));
494 for (auto module
: pos_mods
)
495 for (auto &wire_it
: module
->wires_
) {
496 RTLIL::Wire
*wire
= wire_it
.second
;
497 if (wire
->port_id
> 0)
498 pos_map
[std::pair
<RTLIL::Module
*,int>(module
, wire
->port_id
)] = wire
->name
;
501 for (auto &work
: pos_work
) {
502 RTLIL::Module
*module
= work
.first
;
503 RTLIL::Cell
*cell
= work
.second
;
504 log("Mapping positional arguments of cell %s.%s (%s).\n",
505 RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(cell
->type
));
506 std::map
<RTLIL::IdString
, RTLIL::SigSpec
> new_connections
;
507 for (auto &conn
: cell
->connections())
508 if (conn
.first
[0] == '$' && '0' <= conn
.first
[1] && conn
.first
[1] <= '9') {
509 int id
= atoi(conn
.first
.c_str()+1);
510 std::pair
<RTLIL::Module
*,int> key(design
->modules
.at(cell
->type
), id
);
511 if (pos_map
.count(key
) == 0) {
512 log(" Failed to map positional argument %d of cell %s.%s (%s).\n",
513 id
, RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(cell
->type
));
514 new_connections
[conn
.first
] = conn
.second
;
516 new_connections
[pos_map
.at(key
)] = conn
.second
;
518 new_connections
[conn
.first
] = conn
.second
;
519 cell
->connections_
= new_connections
;