passes/hierarchy/hierarchy.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <set>
  24
  25 #ifndef _WIN32
  26 #  include <unistd.h>
  27 #endif
  28
  29
  30 USING_YOSYS_NAMESPACE
  31 PRIVATE_NAMESPACE_BEGIN
  32
  33 struct generate_port_decl_t {
  34         bool input, output;
  35         string portname;
  36         int index;
  37 };
  38
  39 void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, const std::vector<generate_port_decl_t> &portdecls)
  40 {
  41         std::set<RTLIL::IdString> found_celltypes;
  42
  43         for (auto i1 : design->modules_)
  44         for (auto i2 : i1.second->cells_)
  45         {
  46                 RTLIL::Cell *cell = i2.second;
  47                 if (design->has(cell->type))
  48                         continue;
  49                 if (cell->type.substr(0, 1) == "$" && cell->type.substr(0, 3) != "$__")
  50                         continue;
  51                 for (auto &pattern : celltypes)
  52                         if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str()))
  53                                 found_celltypes.insert(cell->type);
  54         }
  55
  56         for (auto &celltype : found_celltypes)
  57         {
  58                 std::set<RTLIL::IdString> portnames;
  59                 std::set<RTLIL::IdString> parameters;
  60                 std::map<RTLIL::IdString, int> portwidths;
  61                 log("Generate module for cell type %s:\n", celltype.c_str());
  62
  63                 for (auto i1 : design->modules_)
  64                 for (auto i2 : i1.second->cells_)
  65                         if (i2.second->type == celltype) {
  66                                 for (auto &conn : i2.second->connections()) {
  67                                         if (conn.first[0] != '$')
  68                                                 portnames.insert(conn.first);
  69                                         portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size());
  70                                 }
  71                                 for (auto &para : i2.second->parameters)
  72                                         parameters.insert(para.first);
  73                         }
  74
  75                 for (auto &decl : portdecls)
  76                         if (decl.index > 0)
  77                                 portnames.insert(decl.portname);
  78
  79                 std::set<int> indices;
  80                 for (int i = 0; i < int(portnames.size()); i++)
  81                         indices.insert(i+1);
  82
  83                 std::vector<generate_port_decl_t> ports(portnames.size());
  84
  85                 for (auto &decl : portdecls)
  86                         if (decl.index > 0) {
  87                                 portwidths[decl.portname] = std::max(portwidths[decl.portname], 1);
  88                                 portwidths[decl.portname] = std::max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]);
  89                                 log("  port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, RTLIL::id2cstr(decl.portname));
  90                                 if (indices.count(decl.index) > ports.size())
  91                                         log_error("Port index (%d) exceeds number of found ports (%d).\n", decl.index, int(ports.size()));
  92                                 if (indices.count(decl.index) == 0)
  93                                         log_error("Conflict on port index %d.\n", decl.index);
  94                                 indices.erase(decl.index);
  95                                 portnames.erase(decl.portname);
  96                                 ports[decl.index-1] = decl;
  97                         }
  98
  99                 while (portnames.size() > 0) {
 100                         RTLIL::IdString portname = *portnames.begin();
 101                         for (auto &decl : portdecls)
 102                                 if (decl.index == 0 && patmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str())) {
 103                                         generate_port_decl_t d = decl;
 104                                         d.portname = portname.str();
 105                                         d.index = *indices.begin();
 106                                         log_assert(!indices.empty());
 107                                         indices.erase(d.index);
 108                                         ports[d.index-1] = d;
 109                                         portwidths[d.portname] = std::max(portwidths[d.portname], 1);
 110                                         log("  port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::id2cstr(d.portname));
 111                                         goto found_matching_decl;
 112                                 }
 113                         log_error("Can't match port %s.\n", RTLIL::id2cstr(portname));
 114                 found_matching_decl:;
 115                         portnames.erase(portname);
 116                 }
 117
 118                 log_assert(indices.empty());
 119
 120                 RTLIL::Module *mod = new RTLIL::Module;
 121                 mod->name = celltype;
 122                 mod->attributes["\\blackbox"] = RTLIL::Const(1);
 123                 design->add(mod);
 124
 125                 for (auto &decl : ports) {
 126                         RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname));
 127                         wire->port_id = decl.index;
 128                         wire->port_input = decl.input;
 129                         wire->port_output = decl.output;
 130                 }
 131
 132                 mod->fixup_ports();
 133
 134                 for (auto &para : parameters)
 135                         log("  ignoring parameter %s.\n", RTLIL::id2cstr(para));
 136
 137                 log("  module %s created.\n", RTLIL::id2cstr(mod->name));
 138         }
 139 }
 140
 141 bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, std::vector<std::string> &libdirs)
 142 {
 143         bool did_something = false;
 144         std::map<RTLIL::Cell*, std::pair<int, int>> array_cells;
 145         std::string filename;
 146
 147         for (auto &cell_it : module->cells_)
 148         {
 149                 RTLIL::Cell *cell = cell_it.second;
 150
 151                 if (cell->type.substr(0, 7) == "$array:") {
 152                         int pos_idx = cell->type.str().find_first_of(':');
 153                         int pos_num = cell->type.str().find_first_of(':', pos_idx + 1);
 154                         int pos_type = cell->type.str().find_first_of(':', pos_num + 1);
 155                         int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str());
 156                         int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str());
 157                         array_cells[cell] = std::pair<int, int>(idx, num);
 158                         cell->type = cell->type.str().substr(pos_type + 1);
 159                 }
 160
 161                 if (design->modules_.count(cell->type) == 0)
 162                 {
 163                         if (design->modules_.count("$abstract" + cell->type.str()))
 164                         {
 165                                 cell->type = design->modules_.at("$abstract" + cell->type.str())->derive(design, cell->parameters);
 166                                 cell->parameters.clear();
 167                                 did_something = true;
 168                                 continue;
 169                         }
 170
 171                         if (cell->type[0] == '$')
 172                                 continue;
 173
 174                         for (auto &dir : libdirs)
 175                         {
 176                                 filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v";
 177                                 if (check_file_exists(filename)) {
 178                                         std::vector<std::string> args;
 179                                         args.push_back(filename);
 180                                         Frontend::frontend_call(design, NULL, filename, "verilog");
 181                                         goto loaded_module;
 182                                 }
 183
 184                                 filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il";
 185                                 if (check_file_exists(filename)) {
 186                                         std::vector<std::string> args;
 187                                         args.push_back(filename);
 188                                         Frontend::frontend_call(design, NULL, filename, "ilang");
 189                                         goto loaded_module;
 190                                 }
 191                         }
 192
 193                         if (flag_check && cell->type[0] != '$')
 194                                 log_error("Module `%s' referenced in module `%s' in cell `%s' is not part of the design.\n",
 195                                                 cell->type.c_str(), module->name.c_str(), cell->name.c_str());
 196                         continue;
 197
 198                 loaded_module:
 199                         if (design->modules_.count(cell->type) == 0)
 200                                 log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str());
 201                         did_something = true;
 202                 } else
 203                 if (flag_check)
 204                 {
 205                         RTLIL::Module *mod = design->module(cell->type);
 206                         for (auto &conn : cell->connections())
 207                                 if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
 208                                         int id = atoi(conn.first.c_str()+1);
 209                                         if (id <= 0 || id > GetSize(mod->ports))
 210                                                 log_error("Module `%s' referenced in module `%s' in cell `%s' has only %d ports, requested port %d.\n",
 211                                                                 log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->ports), id);
 212                                 } else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0)
 213                                         log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
 214                                                         log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));
 215                 }
 216
 217                 if (cell->parameters.size() == 0)
 218                         continue;
 219
 220                 if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox"))
 221                         continue;
 222
 223                 RTLIL::Module *mod = design->modules_[cell->type];
 224                 cell->type = mod->derive(design, cell->parameters);
 225                 cell->parameters.clear();
 226                 did_something = true;
 227         }
 228
 229         for (auto &it : array_cells)
 230         {
 231                 RTLIL::Cell *cell = it.first;
 232                 int idx = it.second.first, num = it.second.second;
 233
 234                 if (design->modules_.count(cell->type) == 0)
 235                         log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
 236
 237                 RTLIL::Module *mod = design->modules_[cell->type];
 238
 239                 for (auto &conn : cell->connections_) {
 240                         int conn_size = conn.second.size();
 241                         RTLIL::IdString portname = conn.first;
 242                         if (portname.substr(0, 1) == "$") {
 243                                 int port_id = atoi(portname.substr(1).c_str());
 244                                 for (auto &wire_it : mod->wires_)
 245                                         if (wire_it.second->port_id == port_id) {
 246                                                 portname = wire_it.first;
 247                                                 break;
 248                                         }
 249                         }
 250                         if (mod->wires_.count(portname) == 0)
 251                                 log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
 252                         int port_size = mod->wires_.at(portname)->width;
 253                         if (conn_size == port_size)
 254                                 continue;
 255                         if (conn_size != port_size*num)
 256                                 log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
 257                         conn.second = conn.second.extract(port_size*idx, port_size);
 258                 }
 259         }
 260
 261         return did_something;
 262 }
 263
 264 void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &used, RTLIL::Module *mod, int indent)
 265 {
 266         if (used.count(mod) > 0)
 267                 return;
 268
 269         if (indent == 0)
 270                 log("Top module:  %s\n", mod->name.c_str());
 271         else if (!mod->get_bool_attribute("\\blackbox"))
 272                 log("Used module: %*s%s\n", indent, "", mod->name.c_str());
 273         used.insert(mod);
 274
 275         for (auto cell : mod->cells()) {
 276                 std::string celltype = cell->type.str();
 277                 if (celltype.substr(0, 7) == "$array:") {
 278                         int pos_idx = celltype.find_first_of(':');
 279                         int pos_num = celltype.find_first_of(':', pos_idx + 1);
 280                         int pos_type = celltype.find_first_of(':', pos_num + 1);
 281                         celltype = celltype.substr(pos_type + 1);
 282                 }
 283                 if (design->module(celltype))
 284                         hierarchy_worker(design, used, design->module(celltype), indent+4);
 285         }
 286 }
 287
 288 void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
 289 {
 290         std::set<RTLIL::Module*> used;
 291         hierarchy_worker(design, used, top, 0);
 292
 293         std::vector<RTLIL::Module*> del_modules;
 294         for (auto &it : design->modules_)
 295                 if (used.count(it.second) == 0)
 296                         del_modules.push_back(it.second);
 297
 298         int del_counter = 0;
 299         for (auto mod : del_modules) {
 300                 if (mod->name.substr(0, 9) == "$abstract")
 301                         continue;
 302                 if (!purge_lib && mod->get_bool_attribute("\\blackbox"))
 303                         continue;
 304                 log("Removing unused module `%s'.\n", mod->name.c_str());
 305                 design->modules_.erase(mod->name);
 306                 del_counter++;
 307                 delete mod;
 308         }
 309
 310         log("Removed %d unused modules.\n", del_counter);
 311 }
 312
 313 bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
 314 {
 315         if (cache.count(mod) == 0)
 316                 for (auto c : mod->cells()) {
 317                         RTLIL::Module *m = mod->design->module(c->type);
 318                         if ((m != nullptr && set_keep_assert(cache, m)) || c->type == "$assert")
 319                                 return cache[mod] = true;
 320                 }
 321         return cache[mod];
 322 }
 323
 324 int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
 325 {
 326         if (db.count(module) == 0) {
 327                 db[module] = 0;
 328                 for (auto cell : module->cells())
 329                         if (design->module(cell->type))
 330                                 db[module] = std::max(db[module], find_top_mod_score(design, design->module(cell->type), db) + 1);
 331         }
 332         return db.at(module);
 333 }
 334
 335 struct HierarchyPass : public Pass {
 336         HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
 337         virtual void help()
 338         {
 339                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 340                 log("\n");
 341                 log("    hierarchy [-check] [-top <module>]\n");
 342                 log("    hierarchy -generate <cell-types> <port-decls>\n");
 343                 log("\n");
 344                 log("In parametric designs, a module might exists in several variations with\n");
 345                 log("different parameter values. This pass looks at all modules in the current\n");
 346                 log("design an re-runs the language frontends for the parametric modules as\n");
 347                 log("needed.\n");
 348                 log("\n");
 349                 log("    -check\n");
 350                 log("        also check the design hierarchy. this generates an error when\n");
 351                 log("        an unknown module is used as cell type.\n");
 352                 log("\n");
 353                 log("    -purge_lib\n");
 354                 log("        by default the hierarchy command will not remove library (blackbox)\n");
 355                 log("        modules. use this option to also remove unused blackbox modules.\n");
 356                 log("\n");
 357                 log("    -libdir <directory>\n");
 358                 log("        search for files named <module_name>.v in the specified directory\n");
 359                 log("        for unknown modules and automatically run read_verilog for each\n");
 360                 log("        unknown module.\n");
 361                 log("\n");
 362                 log("    -keep_positionals\n");
 363                 log("        per default this pass also converts positional arguments in cells\n");
 364                 log("        to arguments using port names. this option disables this behavior.\n");
 365                 log("\n");
 366                 log("    -nokeep_asserts\n");
 367                 log("        per default this pass sets the \"keep\" attribute on all modules\n");
 368                 log("        that directly or indirectly contain one or more $assert cells. this\n");
 369                 log("        option disables this behavior.\n");
 370                 log("\n");
 371                 log("    -top <module>\n");
 372                 log("        use the specified top module to built a design hierarchy. modules\n");
 373                 log("        outside this tree (unused modules) are removed.\n");
 374                 log("\n");
 375                 log("        when the -top option is used, the 'top' attribute will be set on the\n");
 376                 log("        specified top module. otherwise a module with the 'top' attribute set\n");
 377                 log("        will implicitly be used as top module, if such a module exists.\n");
 378                 log("\n");
 379                 log("    -auto-top\n");
 380                 log("        automatically determine the top of the design hierarchy and mark it.\n");
 381                 log("\n");
 382                 log("In -generate mode this pass generates blackbox modules for the given cell\n");
 383                 log("types (wildcards supported). For this the design is searched for cells that\n");
 384                 log("match the given types and then the given port declarations are used to\n");
 385                 log("determine the direction of the ports. The syntax for a port declaration is:\n");
 386                 log("\n");
 387                 log("    {i|o|io}[@<num>]:<portname>\n");
 388                 log("\n");
 389                 log("Input ports are specified with the 'i' prefix, output ports with the 'o'\n");
 390                 log("prefix and inout ports with the 'io' prefix. The optional <num> specifies\n");
 391                 log("the position of the port in the parameter list (needed when instanciated\n");
 392                 log("using positional arguments). When <num> is not specified, the <portname> can\n");
 393                 log("also contain wildcard characters.\n");
 394                 log("\n");
 395                 log("This pass ignores the current selection and always operates on all modules\n");
 396                 log("in the current design.\n");
 397                 log("\n");
 398         }
 399         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 400         {
 401                 log_header("Executing HIERARCHY pass (managing design hierarchy).\n");
 402
 403                 bool flag_check = false;
 404                 bool purge_lib = false;
 405                 RTLIL::Module *top_mod = NULL;
 406                 std::vector<std::string> libdirs;
 407
 408                 bool auto_top_mode = false;
 409                 bool generate_mode = false;
 410                 bool keep_positionals = false;
 411                 bool nokeep_asserts = false;
 412                 std::vector<std::string> generate_cells;
 413                 std::vector<generate_port_decl_t> generate_ports;
 414
 415                 size_t argidx;
 416                 for (argidx = 1; argidx < args.size(); argidx++)
 417                 {
 418                         if (args[argidx] == "-generate" && !flag_check && !top_mod) {
 419                                 generate_mode = true;
 420                                 log("Entering generate mode.\n");
 421                                 while (++argidx < args.size()) {
 422                                         const char *p = args[argidx].c_str();
 423                                         generate_port_decl_t decl;
 424                                         if (p[0] == 'i' && p[1] == 'o')
 425                                                 decl.input = true, decl.output = true, p += 2;
 426                                         else if (*p == 'i')
 427                                                 decl.input = true, decl.output = false, p++;
 428                                         else if (*p == 'o')
 429                                                 decl.input = false, decl.output = true, p++;
 430                                         else
 431                                                 goto is_celltype;
 432                                         if (*p == '@') {
 433                                                 char *endptr;
 434                                                 decl.index = strtol(++p, &endptr, 10);
 435                                                 if (decl.index < 1)
 436                                                         goto is_celltype;
 437                                                 p = endptr;
 438                                         } else
 439                                                 decl.index = 0;
 440                                         if (*(p++) != ':')
 441                                                 goto is_celltype;
 442                                         if (*p == 0)
 443                                                 goto is_celltype;
 444                                         decl.portname = p;
 445                                         log("Port declaration: %s", decl.input ? decl.output ? "inout" : "input" : "output");
 446                                         if (decl.index >= 1)
 447                                                 log(" [at position %d]", decl.index);
 448                                         log(" %s\n", decl.portname.c_str());
 449                                         generate_ports.push_back(decl);
 450                                         continue;
 451                                 is_celltype:
 452                                         log("Celltype: %s\n", args[argidx].c_str());
 453                                         generate_cells.push_back(RTLIL::unescape_id(args[argidx]));
 454                                 }
 455                                 continue;
 456                         }
 457                         if (args[argidx] == "-check") {
 458                                 flag_check = true;
 459                                 continue;
 460                         }
 461                         if (args[argidx] == "-purge_lib") {
 462                                 purge_lib = true;
 463                                 continue;
 464                         }
 465                         if (args[argidx] == "-keep_positionals") {
 466                                 keep_positionals = true;
 467                                 continue;
 468                         }
 469                         if (args[argidx] == "-nokeep_asserts") {
 470                                 nokeep_asserts = true;
 471                                 continue;
 472                         }
 473                         if (args[argidx] == "-libdir" && argidx+1 < args.size()) {
 474                                 libdirs.push_back(args[++argidx]);
 475                                 continue;
 476                         }
 477                         if (args[argidx] == "-top") {
 478                                 if (++argidx >= args.size())
 479                                         log_cmd_error("Option -top requires an additional argument!\n");
 480                                 top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
 481                                 if (top_mod == NULL && design->modules_.count("$abstract" + RTLIL::escape_id(args[argidx]))) {
 482                                         dict<RTLIL::IdString, RTLIL::Const> empty_parameters;
 483                                         design->modules_.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters);
 484                                         top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
 485                                 }
 486                                 if (top_mod == NULL)
 487                                         log_cmd_error("Module `%s' not found!\n", args[argidx].c_str());
 488                                 continue;
 489                         }
 490                         if (args[argidx] == "-auto-top") {
 491                                 auto_top_mode = true;
 492                                 continue;
 493                         }
 494                         break;
 495                 }
 496                 extra_args(args, argidx, design, false);
 497
 498                 if (generate_mode) {
 499                         generate(design, generate_cells, generate_ports);
 500                         return;
 501                 }
 502
 503                 log_push();
 504
 505                 if (top_mod == nullptr)
 506                         for (auto &mod_it : design->modules_)
 507                                 if (mod_it.second->get_bool_attribute("\\top"))
 508                                         top_mod = mod_it.second;
 509
 510                 if (top_mod == nullptr && auto_top_mode) {
 511                         log_header("Finding top of design hierarchy..\n");
 512                         dict<Module*, int> db;
 513                         for (Module *mod : design->selected_modules()) {
 514                                 int score = find_top_mod_score(design, mod, db);
 515                                 log("root of %3d design levels: %-20s\n", score, log_id(mod));
 516                                 if (!top_mod || score > db[top_mod])
 517                                         top_mod = mod;
 518                         }
 519                         if (top_mod != nullptr)
 520                                 log("Automatically selected %s as design top module.\n", log_id(top_mod));
 521                 }
 522
 523                 bool did_something = true;
 524                 while (did_something)
 525                 {
 526                         did_something = false;
 527
 528                         std::set<RTLIL::Module*> used_modules;
 529                         if (top_mod != NULL) {
 530                                 log_header("Analyzing design hierarchy..\n");
 531                                 hierarchy_worker(design, used_modules, top_mod, 0);
 532                         } else {
 533                                 for (auto mod : design->modules())
 534                                         used_modules.insert(mod);
 535                         }
 536
 537                         for (auto module : used_modules) {
 538                                 if (expand_module(design, module, flag_check, libdirs))
 539                                         did_something = true;
 540                         }
 541                 }
 542
 543                 if (top_mod != NULL) {
 544                         log_header("Analyzing design hierarchy..\n");
 545                         hierarchy_clean(design, top_mod, purge_lib);
 546                 }
 547
 548                 if (top_mod != NULL) {
 549                         for (auto &mod_it : design->modules_)
 550                                 if (mod_it.second == top_mod)
 551                                         mod_it.second->attributes["\\top"] = RTLIL::Const(1);
 552                                 else
 553                                         mod_it.second->attributes.erase("\\top");
 554                 }
 555
 556                 if (!nokeep_asserts) {
 557                         std::map<RTLIL::Module*, bool> cache;
 558                         for (auto mod : design->modules())
 559                                 if (set_keep_assert(cache, mod)) {
 560                                         log("Module %s directly or indirectly contains $assert cells -> setting \"keep\" attribute.\n", log_id(mod));
 561                                         mod->set_bool_attribute("\\keep");
 562                                 }
 563                 }
 564
 565                 if (!keep_positionals)
 566                 {
 567                         std::set<RTLIL::Module*> pos_mods;
 568                         std::map<std::pair<RTLIL::Module*,int>, RTLIL::IdString> pos_map;
 569                         std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work;
 570
 571                         for (auto &mod_it : design->modules_)
 572                         for (auto &cell_it : mod_it.second->cells_) {
 573                                 RTLIL::Cell *cell = cell_it.second;
 574                                 if (design->modules_.count(cell->type) == 0)
 575                                         continue;
 576                                 for (auto &conn : cell->connections())
 577                                         if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
 578                                                 pos_mods.insert(design->modules_.at(cell->type));
 579                                                 pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell));
 580                                                 break;
 581                                         }
 582                         }
 583
 584                         for (auto module : pos_mods)
 585                         for (auto &wire_it : module->wires_) {
 586                                 RTLIL::Wire *wire = wire_it.second;
 587                                 if (wire->port_id > 0)
 588                                         pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = wire->name;
 589                         }
 590
 591                         for (auto &work : pos_work) {
 592                                 RTLIL::Module *module = work.first;
 593                                 RTLIL::Cell *cell = work.second;
 594                                 log("Mapping positional arguments of cell %s.%s (%s).\n",
 595                                                 RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
 596                                 dict<RTLIL::IdString, RTLIL::SigSpec> new_connections;
 597                                 for (auto &conn : cell->connections())
 598                                         if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
 599                                                 int id = atoi(conn.first.c_str()+1);
 600                                                 std::pair<RTLIL::Module*,int> key(design->modules_.at(cell->type), id);
 601                                                 if (pos_map.count(key) == 0) {
 602                                                         log("  Failed to map positional argument %d of cell %s.%s (%s).\n",
 603                                                                         id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
 604                                                         new_connections[conn.first] = conn.second;
 605                                                 } else
 606                                                         new_connections[pos_map.at(key)] = conn.second;
 607                                         } else
 608                                                 new_connections[conn.first] = conn.second;
 609                                 cell->connections_ = new_connections;
 610                         }
 611                 }
 612
 613                 log_pop();
 614         }
 615 } HierarchyPass;
 616
 617 PRIVATE_NAMESPACE_END