2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
31 PRIVATE_NAMESPACE_BEGIN
33 struct generate_port_decl_t
{
39 void generate(RTLIL::Design
*design
, const std::vector
<std::string
> &celltypes
, const std::vector
<generate_port_decl_t
> &portdecls
)
41 std::set
<RTLIL::IdString
> found_celltypes
;
43 for (auto i1
: design
->modules_
)
44 for (auto i2
: i1
.second
->cells_
)
46 RTLIL::Cell
*cell
= i2
.second
;
47 if (design
->has(cell
->type
))
49 if (cell
->type
.substr(0, 1) == "$" && cell
->type
.substr(0, 3) != "$__")
51 for (auto &pattern
: celltypes
)
52 if (patmatch(pattern
.c_str(), RTLIL::unescape_id(cell
->type
).c_str()))
53 found_celltypes
.insert(cell
->type
);
56 for (auto &celltype
: found_celltypes
)
58 std::set
<RTLIL::IdString
> portnames
;
59 std::set
<RTLIL::IdString
> parameters
;
60 std::map
<RTLIL::IdString
, int> portwidths
;
61 log("Generate module for cell type %s:\n", celltype
.c_str());
63 for (auto i1
: design
->modules_
)
64 for (auto i2
: i1
.second
->cells_
)
65 if (i2
.second
->type
== celltype
) {
66 for (auto &conn
: i2
.second
->connections()) {
67 if (conn
.first
[0] != '$')
68 portnames
.insert(conn
.first
);
69 portwidths
[conn
.first
] = max(portwidths
[conn
.first
], conn
.second
.size());
71 for (auto ¶
: i2
.second
->parameters
)
72 parameters
.insert(para
.first
);
75 for (auto &decl
: portdecls
)
77 portnames
.insert(decl
.portname
);
79 std::set
<int> indices
;
80 for (int i
= 0; i
< int(portnames
.size()); i
++)
83 std::vector
<generate_port_decl_t
> ports(portnames
.size());
85 for (auto &decl
: portdecls
)
87 portwidths
[decl
.portname
] = max(portwidths
[decl
.portname
], 1);
88 portwidths
[decl
.portname
] = max(portwidths
[decl
.portname
], portwidths
[stringf("$%d", decl
.index
)]);
89 log(" port %d: %s [%d:0] %s\n", decl
.index
, decl
.input
? decl
.output
? "inout" : "input" : "output", portwidths
[decl
.portname
]-1, RTLIL::id2cstr(decl
.portname
));
90 if (indices
.count(decl
.index
) > ports
.size())
91 log_error("Port index (%d) exceeds number of found ports (%d).\n", decl
.index
, int(ports
.size()));
92 if (indices
.count(decl
.index
) == 0)
93 log_error("Conflict on port index %d.\n", decl
.index
);
94 indices
.erase(decl
.index
);
95 portnames
.erase(decl
.portname
);
96 ports
[decl
.index
-1] = decl
;
99 while (portnames
.size() > 0) {
100 RTLIL::IdString portname
= *portnames
.begin();
101 for (auto &decl
: portdecls
)
102 if (decl
.index
== 0 && patmatch(decl
.portname
.c_str(), RTLIL::unescape_id(portname
).c_str())) {
103 generate_port_decl_t d
= decl
;
104 d
.portname
= portname
.str();
105 d
.index
= *indices
.begin();
106 log_assert(!indices
.empty());
107 indices
.erase(d
.index
);
108 ports
[d
.index
-1] = d
;
109 portwidths
[d
.portname
] = max(portwidths
[d
.portname
], 1);
110 log(" port %d: %s [%d:0] %s\n", d
.index
, d
.input
? d
.output
? "inout" : "input" : "output", portwidths
[d
.portname
]-1, RTLIL::id2cstr(d
.portname
));
111 goto found_matching_decl
;
113 log_error("Can't match port %s.\n", RTLIL::id2cstr(portname
));
114 found_matching_decl
:;
115 portnames
.erase(portname
);
118 log_assert(indices
.empty());
120 RTLIL::Module
*mod
= new RTLIL::Module
;
121 mod
->name
= celltype
;
122 mod
->attributes
["\\blackbox"] = RTLIL::Const(1);
125 for (auto &decl
: ports
) {
126 RTLIL::Wire
*wire
= mod
->addWire(decl
.portname
, portwidths
.at(decl
.portname
));
127 wire
->port_id
= decl
.index
;
128 wire
->port_input
= decl
.input
;
129 wire
->port_output
= decl
.output
;
134 for (auto ¶
: parameters
)
135 log(" ignoring parameter %s.\n", RTLIL::id2cstr(para
));
137 log(" module %s created.\n", RTLIL::id2cstr(mod
->name
));
141 bool expand_module(RTLIL::Design
*design
, RTLIL::Module
*module
, bool flag_check
, std::vector
<std::string
> &libdirs
)
143 bool did_something
= false;
144 std::map
<RTLIL::Cell
*, std::pair
<int, int>> array_cells
;
145 std::string filename
;
147 for (auto &cell_it
: module
->cells_
)
149 RTLIL::Cell
*cell
= cell_it
.second
;
151 if (cell
->type
.substr(0, 7) == "$array:") {
152 int pos_idx
= cell
->type
.str().find_first_of(':');
153 int pos_num
= cell
->type
.str().find_first_of(':', pos_idx
+ 1);
154 int pos_type
= cell
->type
.str().find_first_of(':', pos_num
+ 1);
155 int idx
= atoi(cell
->type
.str().substr(pos_idx
+ 1, pos_num
).c_str());
156 int num
= atoi(cell
->type
.str().substr(pos_num
+ 1, pos_type
).c_str());
157 array_cells
[cell
] = std::pair
<int, int>(idx
, num
);
158 cell
->type
= cell
->type
.str().substr(pos_type
+ 1);
161 if (design
->modules_
.count(cell
->type
) == 0)
163 if (design
->modules_
.count("$abstract" + cell
->type
.str()))
165 cell
->type
= design
->modules_
.at("$abstract" + cell
->type
.str())->derive(design
, cell
->parameters
);
166 cell
->parameters
.clear();
167 did_something
= true;
171 if (cell
->type
[0] == '$')
174 for (auto &dir
: libdirs
)
176 filename
= dir
+ "/" + RTLIL::unescape_id(cell
->type
) + ".v";
177 if (check_file_exists(filename
)) {
178 Frontend::frontend_call(design
, NULL
, filename
, "verilog");
182 filename
= dir
+ "/" + RTLIL::unescape_id(cell
->type
) + ".il";
183 if (check_file_exists(filename
)) {
184 Frontend::frontend_call(design
, NULL
, filename
, "ilang");
189 if (flag_check
&& cell
->type
[0] != '$')
190 log_error("Module `%s' referenced in module `%s' in cell `%s' is not part of the design.\n",
191 cell
->type
.c_str(), module
->name
.c_str(), cell
->name
.c_str());
195 if (design
->modules_
.count(cell
->type
) == 0)
196 log_error("File `%s' from libdir does not declare module `%s'.\n", filename
.c_str(), cell
->type
.c_str());
197 did_something
= true;
201 RTLIL::Module
*mod
= design
->module(cell
->type
);
202 for (auto &conn
: cell
->connections())
203 if (conn
.first
[0] == '$' && '0' <= conn
.first
[1] && conn
.first
[1] <= '9') {
204 int id
= atoi(conn
.first
.c_str()+1);
205 if (id
<= 0 || id
> GetSize(mod
->ports
))
206 log_error("Module `%s' referenced in module `%s' in cell `%s' has only %d ports, requested port %d.\n",
207 log_id(cell
->type
), log_id(module
), log_id(cell
), GetSize(mod
->ports
), id
);
208 } else if (mod
->wire(conn
.first
) == nullptr || mod
->wire(conn
.first
)->port_id
== 0)
209 log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
210 log_id(cell
->type
), log_id(module
), log_id(cell
), log_id(conn
.first
));
211 for (auto ¶m
: cell
->parameters
)
212 if (mod
->avail_parameters
.count(param
.first
) == 0 && param
.first
[0] != '$' && strchr(param
.first
.c_str(), '.') == NULL
)
213 log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a parameter named '%s'.\n",
214 log_id(cell
->type
), log_id(module
), log_id(cell
), log_id(param
.first
));
217 if (cell
->parameters
.size() == 0)
220 if (design
->modules_
.at(cell
->type
)->get_bool_attribute("\\blackbox"))
223 RTLIL::Module
*mod
= design
->modules_
[cell
->type
];
224 cell
->type
= mod
->derive(design
, cell
->parameters
);
225 cell
->parameters
.clear();
226 did_something
= true;
229 for (auto &it
: array_cells
)
231 RTLIL::Cell
*cell
= it
.first
;
232 int idx
= it
.second
.first
, num
= it
.second
.second
;
234 if (design
->modules_
.count(cell
->type
) == 0)
235 log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(cell
->type
));
237 RTLIL::Module
*mod
= design
->modules_
[cell
->type
];
239 for (auto &conn
: cell
->connections_
) {
240 int conn_size
= conn
.second
.size();
241 RTLIL::IdString portname
= conn
.first
;
242 if (portname
.substr(0, 1) == "$") {
243 int port_id
= atoi(portname
.substr(1).c_str());
244 for (auto &wire_it
: mod
->wires_
)
245 if (wire_it
.second
->port_id
== port_id
) {
246 portname
= wire_it
.first
;
250 if (mod
->wires_
.count(portname
) == 0)
251 log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(conn
.first
));
252 int port_size
= mod
->wires_
.at(portname
)->width
;
253 if (conn_size
== port_size
)
255 if (conn_size
!= port_size
*num
)
256 log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(conn
.first
));
257 conn
.second
= conn
.second
.extract(port_size
*idx
, port_size
);
261 return did_something
;
264 void hierarchy_worker(RTLIL::Design
*design
, std::set
<RTLIL::Module
*, IdString::compare_ptr_by_name
<Module
>> &used
, RTLIL::Module
*mod
, int indent
)
266 if (used
.count(mod
) > 0)
270 log("Top module: %s\n", mod
->name
.c_str());
271 else if (!mod
->get_bool_attribute("\\blackbox"))
272 log("Used module: %*s%s\n", indent
, "", mod
->name
.c_str());
275 for (auto cell
: mod
->cells()) {
276 std::string celltype
= cell
->type
.str();
277 if (celltype
.substr(0, 7) == "$array:") {
278 int pos_idx
= celltype
.find_first_of(':');
279 int pos_num
= celltype
.find_first_of(':', pos_idx
+ 1);
280 int pos_type
= celltype
.find_first_of(':', pos_num
+ 1);
281 celltype
= celltype
.substr(pos_type
+ 1);
283 if (design
->module(celltype
))
284 hierarchy_worker(design
, used
, design
->module(celltype
), indent
+4);
288 void hierarchy_clean(RTLIL::Design
*design
, RTLIL::Module
*top
, bool purge_lib
)
290 std::set
<RTLIL::Module
*, IdString::compare_ptr_by_name
<Module
>> used
;
291 hierarchy_worker(design
, used
, top
, 0);
293 std::vector
<RTLIL::Module
*> del_modules
;
294 for (auto &it
: design
->modules_
)
295 if (used
.count(it
.second
) == 0)
296 del_modules
.push_back(it
.second
);
299 for (auto mod
: del_modules
) {
300 if (!purge_lib
&& mod
->get_bool_attribute("\\blackbox"))
302 log("Removing unused module `%s'.\n", mod
->name
.c_str());
303 design
->modules_
.erase(mod
->name
);
308 log("Removed %d unused modules.\n", del_counter
);
311 bool set_keep_assert(std::map
<RTLIL::Module
*, bool> &cache
, RTLIL::Module
*mod
)
313 if (cache
.count(mod
) == 0)
314 for (auto c
: mod
->cells()) {
315 RTLIL::Module
*m
= mod
->design
->module(c
->type
);
316 if ((m
!= nullptr && set_keep_assert(cache
, m
)) || c
->type
.in("$assert", "$assume", "$cover"))
317 return cache
[mod
] = true;
322 int find_top_mod_score(Design
*design
, Module
*module
, dict
<Module
*, int> &db
)
324 if (db
.count(module
) == 0) {
327 for (auto cell
: module
->cells())
328 if (design
->module(cell
->type
))
329 score
= max(score
, find_top_mod_score(design
, design
->module(cell
->type
), db
) + 1);
332 return db
.at(module
);
335 struct HierarchyPass
: public Pass
{
336 HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
339 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
341 log(" hierarchy [-check] [-top <module>]\n");
342 log(" hierarchy -generate <cell-types> <port-decls>\n");
344 log("In parametric designs, a module might exists in several variations with\n");
345 log("different parameter values. This pass looks at all modules in the current\n");
346 log("design an re-runs the language frontends for the parametric modules as\n");
350 log(" also check the design hierarchy. this generates an error when\n");
351 log(" an unknown module is used as cell type.\n");
353 log(" -purge_lib\n");
354 log(" by default the hierarchy command will not remove library (blackbox)\n");
355 log(" modules. use this option to also remove unused blackbox modules.\n");
357 log(" -libdir <directory>\n");
358 log(" search for files named <module_name>.v in the specified directory\n");
359 log(" for unknown modules and automatically run read_verilog for each\n");
360 log(" unknown module.\n");
362 log(" -keep_positionals\n");
363 log(" per default this pass also converts positional arguments in cells\n");
364 log(" to arguments using port names. this option disables this behavior.\n");
366 log(" -keep_portwidths\n");
367 log(" per default this pass adjusts the port width on cells that are\n");
368 log(" module instances when the width does not match the module port. this\n");
369 log(" option disables this behavior.\n");
371 log(" -nokeep_asserts\n");
372 log(" per default this pass sets the \"keep\" attribute on all modules\n");
373 log(" that directly or indirectly contain one or more $assert cells. this\n");
374 log(" option disables this behavior.\n");
376 log(" -top <module>\n");
377 log(" use the specified top module to built a design hierarchy. modules\n");
378 log(" outside this tree (unused modules) are removed.\n");
380 log(" when the -top option is used, the 'top' attribute will be set on the\n");
381 log(" specified top module. otherwise a module with the 'top' attribute set\n");
382 log(" will implicitly be used as top module, if such a module exists.\n");
385 log(" automatically determine the top of the design hierarchy and mark it.\n");
387 log("In -generate mode this pass generates blackbox modules for the given cell\n");
388 log("types (wildcards supported). For this the design is searched for cells that\n");
389 log("match the given types and then the given port declarations are used to\n");
390 log("determine the direction of the ports. The syntax for a port declaration is:\n");
392 log(" {i|o|io}[@<num>]:<portname>\n");
394 log("Input ports are specified with the 'i' prefix, output ports with the 'o'\n");
395 log("prefix and inout ports with the 'io' prefix. The optional <num> specifies\n");
396 log("the position of the port in the parameter list (needed when instantiated\n");
397 log("using positional arguments). When <num> is not specified, the <portname> can\n");
398 log("also contain wildcard characters.\n");
400 log("This pass ignores the current selection and always operates on all modules\n");
401 log("in the current design.\n");
404 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
406 log_header(design
, "Executing HIERARCHY pass (managing design hierarchy).\n");
408 bool flag_check
= false;
409 bool purge_lib
= false;
410 RTLIL::Module
*top_mod
= NULL
;
411 std::vector
<std::string
> libdirs
;
413 bool auto_top_mode
= false;
414 bool generate_mode
= false;
415 bool keep_positionals
= false;
416 bool keep_portwidths
= false;
417 bool nokeep_asserts
= false;
418 std::vector
<std::string
> generate_cells
;
419 std::vector
<generate_port_decl_t
> generate_ports
;
422 for (argidx
= 1; argidx
< args
.size(); argidx
++)
424 if (args
[argidx
] == "-generate" && !flag_check
&& !top_mod
) {
425 generate_mode
= true;
426 log("Entering generate mode.\n");
427 while (++argidx
< args
.size()) {
428 const char *p
= args
[argidx
].c_str();
429 generate_port_decl_t decl
;
430 if (p
[0] == 'i' && p
[1] == 'o')
431 decl
.input
= true, decl
.output
= true, p
+= 2;
433 decl
.input
= true, decl
.output
= false, p
++;
435 decl
.input
= false, decl
.output
= true, p
++;
440 decl
.index
= strtol(++p
, &endptr
, 10);
451 log("Port declaration: %s", decl
.input
? decl
.output
? "inout" : "input" : "output");
453 log(" [at position %d]", decl
.index
);
454 log(" %s\n", decl
.portname
.c_str());
455 generate_ports
.push_back(decl
);
458 log("Celltype: %s\n", args
[argidx
].c_str());
459 generate_cells
.push_back(RTLIL::unescape_id(args
[argidx
]));
463 if (args
[argidx
] == "-check") {
467 if (args
[argidx
] == "-purge_lib") {
471 if (args
[argidx
] == "-keep_positionals") {
472 keep_positionals
= true;
475 if (args
[argidx
] == "-keep_portwidths") {
476 keep_portwidths
= true;
479 if (args
[argidx
] == "-nokeep_asserts") {
480 nokeep_asserts
= true;
483 if (args
[argidx
] == "-libdir" && argidx
+1 < args
.size()) {
484 libdirs
.push_back(args
[++argidx
]);
487 if (args
[argidx
] == "-top") {
488 if (++argidx
>= args
.size())
489 log_cmd_error("Option -top requires an additional argument!\n");
490 top_mod
= design
->modules_
.count(RTLIL::escape_id(args
[argidx
])) ? design
->modules_
.at(RTLIL::escape_id(args
[argidx
])) : NULL
;
491 if (top_mod
== NULL
&& design
->modules_
.count("$abstract" + RTLIL::escape_id(args
[argidx
]))) {
492 dict
<RTLIL::IdString
, RTLIL::Const
> empty_parameters
;
493 design
->modules_
.at("$abstract" + RTLIL::escape_id(args
[argidx
]))->derive(design
, empty_parameters
);
494 top_mod
= design
->modules_
.count(RTLIL::escape_id(args
[argidx
])) ? design
->modules_
.at(RTLIL::escape_id(args
[argidx
])) : NULL
;
497 log_cmd_error("Module `%s' not found!\n", args
[argidx
].c_str());
500 if (args
[argidx
] == "-auto-top") {
501 auto_top_mode
= true;
506 extra_args(args
, argidx
, design
, false);
509 generate(design
, generate_cells
, generate_ports
);
515 if (top_mod
== nullptr)
516 for (auto &mod_it
: design
->modules_
)
517 if (mod_it
.second
->get_bool_attribute("\\top"))
518 top_mod
= mod_it
.second
;
520 if (top_mod
== nullptr && auto_top_mode
) {
521 log_header(design
, "Finding top of design hierarchy..\n");
522 dict
<Module
*, int> db
;
523 for (Module
*mod
: design
->selected_modules()) {
524 int score
= find_top_mod_score(design
, mod
, db
);
525 log("root of %3d design levels: %-20s\n", score
, log_id(mod
));
526 if (!top_mod
|| score
> db
[top_mod
])
529 if (top_mod
!= nullptr)
530 log("Automatically selected %s as design top module.\n", log_id(top_mod
));
533 bool did_something
= true;
534 while (did_something
)
536 did_something
= false;
538 std::set
<RTLIL::Module
*, IdString::compare_ptr_by_name
<Module
>> used_modules
;
539 if (top_mod
!= NULL
) {
540 log_header(design
, "Analyzing design hierarchy..\n");
541 hierarchy_worker(design
, used_modules
, top_mod
, 0);
543 for (auto mod
: design
->modules())
544 used_modules
.insert(mod
);
547 for (auto module
: used_modules
) {
548 if (expand_module(design
, module
, flag_check
, libdirs
))
549 did_something
= true;
553 if (top_mod
!= NULL
) {
554 log_header(design
, "Analyzing design hierarchy..\n");
555 hierarchy_clean(design
, top_mod
, purge_lib
);
558 if (top_mod
!= NULL
) {
559 for (auto &mod_it
: design
->modules_
)
560 if (mod_it
.second
== top_mod
)
561 mod_it
.second
->attributes
["\\top"] = RTLIL::Const(1);
563 mod_it
.second
->attributes
.erase("\\top");
566 if (!nokeep_asserts
) {
567 std::map
<RTLIL::Module
*, bool> cache
;
568 for (auto mod
: design
->modules())
569 if (set_keep_assert(cache
, mod
)) {
570 log("Module %s directly or indirectly contains $assert cells -> setting \"keep\" attribute.\n", log_id(mod
));
571 mod
->set_bool_attribute("\\keep");
575 if (!keep_positionals
)
577 std::set
<RTLIL::Module
*> pos_mods
;
578 std::map
<std::pair
<RTLIL::Module
*,int>, RTLIL::IdString
> pos_map
;
579 std::vector
<std::pair
<RTLIL::Module
*,RTLIL::Cell
*>> pos_work
;
581 for (auto &mod_it
: design
->modules_
)
582 for (auto &cell_it
: mod_it
.second
->cells_
) {
583 RTLIL::Cell
*cell
= cell_it
.second
;
584 if (design
->modules_
.count(cell
->type
) == 0)
586 for (auto &conn
: cell
->connections())
587 if (conn
.first
[0] == '$' && '0' <= conn
.first
[1] && conn
.first
[1] <= '9') {
588 pos_mods
.insert(design
->modules_
.at(cell
->type
));
589 pos_work
.push_back(std::pair
<RTLIL::Module
*,RTLIL::Cell
*>(mod_it
.second
, cell
));
594 for (auto module
: pos_mods
)
595 for (auto &wire_it
: module
->wires_
) {
596 RTLIL::Wire
*wire
= wire_it
.second
;
597 if (wire
->port_id
> 0)
598 pos_map
[std::pair
<RTLIL::Module
*,int>(module
, wire
->port_id
)] = wire
->name
;
601 for (auto &work
: pos_work
) {
602 RTLIL::Module
*module
= work
.first
;
603 RTLIL::Cell
*cell
= work
.second
;
604 log("Mapping positional arguments of cell %s.%s (%s).\n",
605 RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(cell
->type
));
606 dict
<RTLIL::IdString
, RTLIL::SigSpec
> new_connections
;
607 for (auto &conn
: cell
->connections())
608 if (conn
.first
[0] == '$' && '0' <= conn
.first
[1] && conn
.first
[1] <= '9') {
609 int id
= atoi(conn
.first
.c_str()+1);
610 std::pair
<RTLIL::Module
*,int> key(design
->modules_
.at(cell
->type
), id
);
611 if (pos_map
.count(key
) == 0) {
612 log(" Failed to map positional argument %d of cell %s.%s (%s).\n",
613 id
, RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(cell
->type
));
614 new_connections
[conn
.first
] = conn
.second
;
616 new_connections
[pos_map
.at(key
)] = conn
.second
;
618 new_connections
[conn
.first
] = conn
.second
;
619 cell
->connections_
= new_connections
;
623 if (!keep_portwidths
)
625 for (auto module
: design
->modules())
626 for (auto cell
: module
->cells())
628 Module
*m
= design
->module(cell
->type
);
633 for (auto &conn
: cell
->connections())
635 Wire
*w
= m
->wire(conn
.first
);
637 if (w
== nullptr || w
->port_id
== 0)
640 if (GetSize(w
) == GetSize(conn
.second
))
643 SigSpec sig
= conn
.second
;
645 if (GetSize(w
) < GetSize(conn
.second
))
647 int n
= GetSize(conn
.second
) - GetSize(w
);
648 if (!w
->port_input
&& w
->port_output
)
649 module
->connect(sig
.extract(GetSize(w
), n
), Const(0, n
));
650 sig
.remove(GetSize(w
), n
);
654 int n
= GetSize(w
) - GetSize(conn
.second
);
655 if (w
->port_input
&& !w
->port_output
)
656 sig
.append(Const(0, n
));
658 sig
.append(module
->addWire(NEW_ID
, n
));
661 if (!conn
.second
.is_fully_const() || !w
->port_input
|| w
->port_output
)
662 log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module
), log_id(cell
),
663 log_id(conn
.first
), GetSize(conn
.second
), GetSize(sig
));
664 cell
->setPort(conn
.first
, sig
);
673 PRIVATE_NAMESPACE_END