Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"
[yosys.git] / passes / hierarchy / uniquify.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21
22 USING_YOSYS_NAMESPACE
23 PRIVATE_NAMESPACE_BEGIN
24
25 struct UniquifyPass : public Pass {
26 UniquifyPass() : Pass("uniquify", "create unique copies of modules") { }
27 void help() YS_OVERRIDE
28 {
29 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
30 log("\n");
31 log(" uniquify [selection]\n");
32 log("\n");
33 log("By default, a module that is instantiated by several other modules is only\n");
34 log("kept once in the design. This preserves the original modularity of the design\n");
35 log("and reduces the overall size of the design in memory. But it prevents certain\n");
36 log("optimizations and other operations on the design. This pass creates unique\n");
37 log("modules for all selected cells. The created modules are marked with the\n");
38 log("'unique' attribute.\n");
39 log("\n");
40 log("This commands only operates on modules that by themself have the 'unique'\n");
41 log("attribute set (the 'top' module is unique implicitly).\n");
42 log("\n");
43 }
44 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
45 {
46 log_header(design, "Executing UNIQUIFY pass (creating unique copies of modules).\n");
47
48 size_t argidx;
49 for (argidx = 1; argidx < args.size(); argidx++)
50 {
51 // if (args[argidx] == "-check") {
52 // flag_check = true;
53 // continue;
54 // }
55 }
56 extra_args(args, argidx, design);
57
58 bool did_something = true;
59 int count = 0;
60
61 while (did_something)
62 {
63 did_something = false;
64
65 for (auto module : design->selected_modules())
66 {
67 if (!module->get_bool_attribute(ID::unique) && !module->get_bool_attribute(ID::top))
68 continue;
69
70 for (auto cell : module->selected_cells())
71 {
72 Module *tmod = design->module(cell->type);
73 IdString newname = module->name.str() + "." + log_id(cell->name);
74
75 if (tmod == nullptr)
76 continue;
77
78 if (tmod->get_blackbox_attribute())
79 continue;
80
81 if (tmod->get_bool_attribute(ID::unique) && newname == tmod->name)
82 continue;
83
84 log("Creating module %s from %s.\n", log_id(newname), log_id(tmod));
85
86 auto smod = tmod->clone();
87 smod->name = newname;
88 cell->type = newname;
89 smod->set_bool_attribute(ID::unique);
90 if (smod->attributes.count(ID::hdlname) == 0)
91 smod->attributes[ID::hdlname] = string(log_id(tmod->name));
92 design->add(smod);
93
94 did_something = true;
95 count++;
96 }
97 }
98 }
99
100 log("Created %d unique modules.\n", count);
101 }
102 } UniquifyPass;
103
104 PRIVATE_NAMESPACE_END