Merge pull request #3310 from robinsonb5-PRs/master
[yosys.git] / passes / memory / memory_collect.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/mem.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 struct MemoryCollectPass : public Pass {
27 MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { }
28 void help() override
29 {
30 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
31 log("\n");
32 log(" memory_collect [selection]\n");
33 log("\n");
34 log("This pass collects memories and memory ports and creates generic multiport\n");
35 log("memory cells.\n");
36 log("\n");
37 }
38 void execute(std::vector<std::string> args, RTLIL::Design *design) override {
39 log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
40 extra_args(args, 1, design);
41 for (auto module : design->selected_modules()) {
42 for (auto &mem : Mem::get_selected_memories(module)) {
43 if (!mem.packed) {
44 mem.packed = true;
45 mem.emit();
46 }
47 }
48 }
49 }
50 } MemoryCollectPass;
51
52 PRIVATE_NAMESPACE_END