2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/mem.h"
24 PRIVATE_NAMESPACE_BEGIN
26 struct MemoryCollectPass
: public Pass
{
27 MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { }
30 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
32 log(" memory_collect [selection]\n");
34 log("This pass collects memories and memory ports and creates generic multiport\n");
35 log("memory cells.\n");
38 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) override
{
39 log_header(design
, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
40 extra_args(args
, 1, design
);
41 for (auto module
: design
->selected_modules()) {
42 for (auto &mem
: Mem::get_selected_memories(module
)) {