passes/memory/memory_narrow.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2020  Marcelina Kościelnicka <mwk@0x04.net>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/sigtools.h"
  22 #include "kernel/mem.h"
  23
  24 USING_YOSYS_NAMESPACE
  25 PRIVATE_NAMESPACE_BEGIN
  26
  27 struct MemoryNarrowPass : public Pass {
  28         MemoryNarrowPass() : Pass("memory_narrow", "split up wide memory ports") { }
  29         void help() override
  30         {
  31                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  32                 log("\n");
  33                 log("    memory_narrow [options] [selection]\n");
  34                 log("\n");
  35                 log("This pass splits up wide memory ports into several narrow ports.\n");
  36                 log("\n");
  37         }
  38         void execute(std::vector<std::string> args, RTLIL::Design *design) override
  39         {
  40                 log_header(design, "Executing MEMORY_NARROW pass (splitting up wide memory ports).\n");
  41
  42                 size_t argidx;
  43                 for (argidx = 1; argidx < args.size(); argidx++) {
  44                         break;
  45                 }
  46                 extra_args(args, argidx, design);
  47
  48                 for (auto module : design->selected_modules()) {
  49                         for (auto &mem : Mem::get_selected_memories(module))
  50                         {
  51                                 bool wide = false;
  52                                 for (auto &port : mem.rd_ports)
  53                                         if (port.wide_log2)
  54                                                 wide = true;
  55                                 for (auto &port : mem.wr_ports)
  56                                         if (port.wide_log2)
  57                                                 wide = true;
  58                                 if (wide) {
  59                                         mem.narrow();
  60                                         mem.emit();
  61                                 }
  62                         }
  63                 }
  64         }
  65 } MemoryNarrowPass;
  66
  67 PRIVATE_NAMESPACE_END