2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
24 PRIVATE_NAMESPACE_BEGIN
26 struct MemoryNordffPass
: public Pass
{
27 MemoryNordffPass() : Pass("memory_nordff", "extract read port FFs from memories") { }
28 void help() YS_OVERRIDE
30 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
32 log(" memory_nordff [options] [selection]\n");
34 log("This pass extracts FFs from memory read ports. This results in a netlist\n");
35 log("similar to what one would get from calling memory_dff with -nordff.\n");
38 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
40 log_header(design
, "Executing MEMORY_NORDFF pass (extracting $dff cells from $mem).\n");
43 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
44 // if (args[argidx] == "-nordff" || args[argidx] == "-wr_only") {
45 // flag_wr_only = true;
50 extra_args(args
, argidx
, design
);
52 for (auto module
: design
->selected_modules())
53 for (auto cell
: vector
<Cell
*>(module
->selected_cells()))
55 if (cell
->type
!= "$mem")
58 int rd_ports
= cell
->getParam("\\RD_PORTS").as_int();
59 int abits
= cell
->getParam("\\ABITS").as_int();
60 int width
= cell
->getParam("\\WIDTH").as_int();
62 SigSpec rd_addr
= cell
->getPort("\\RD_ADDR");
63 SigSpec rd_data
= cell
->getPort("\\RD_DATA");
64 SigSpec rd_clk
= cell
->getPort("\\RD_CLK");
65 SigSpec rd_en
= cell
->getPort("\\RD_EN");
66 Const rd_clk_enable
= cell
->getParam("\\RD_CLK_ENABLE");
67 Const rd_clk_polarity
= cell
->getParam("\\RD_CLK_POLARITY");
69 for (int i
= 0; i
< rd_ports
; i
++)
71 bool clk_enable
= rd_clk_enable
[i
] == State::S1
;
75 bool clk_polarity
= cell
->getParam("\\RD_CLK_POLARITY")[i
] == State::S1
;
76 bool transparent
= cell
->getParam("\\RD_TRANSPARENT")[i
] == State::S1
;
78 SigSpec clk
= cell
->getPort("\\RD_CLK")[i
] ;
79 SigSpec en
= cell
->getPort("\\RD_EN")[i
];
84 SigSpec sig_q
= module
->addWire(NEW_ID
, abits
);
85 SigSpec sig_d
= rd_addr
.extract(abits
* i
, abits
);
86 rd_addr
.replace(abits
* i
, sig_q
);
88 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, en
);
89 c
= module
->addDff(NEW_ID
, clk
, sig_d
, sig_q
, clk_polarity
);
93 SigSpec sig_d
= module
->addWire(NEW_ID
, width
);
94 SigSpec sig_q
= rd_data
.extract(width
* i
, width
);
95 rd_data
.replace(width
*i
, sig_d
);
97 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, en
);
98 c
= module
->addDff(NEW_ID
, clk
, sig_d
, sig_q
, clk_polarity
);
101 log("Extracted %s FF from read port %d of %s.%s: %s\n", transparent
? "addr" : "data",
102 i
, log_id(module
), log_id(cell
), log_id(c
));
105 rd_en
[i
] = State::S1
;
106 rd_clk
[i
] = State::S0
;
107 rd_clk_enable
[i
] = State::S0
;
108 rd_clk_polarity
[i
] = State::S1
;
111 cell
->setPort("\\RD_ADDR", rd_addr
);
112 cell
->setPort("\\RD_DATA", rd_data
);
113 cell
->setPort("\\RD_CLK", rd_clk
);
114 cell
->setPort("\\RD_EN", rd_en
);
115 cell
->setParam("\\RD_CLK_ENABLE", rd_clk_enable
);
116 cell
->setParam("\\RD_CLK_POLARITY", rd_clk_polarity
);
121 PRIVATE_NAMESPACE_END