passes/opt/opt_clean.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "opt_status.h"
  21 #include "kernel/register.h"
  22 #include "kernel/sigtools.h"
  23 #include "kernel/log.h"
  24 #include "kernel/celltypes.h"
  25 #include <stdlib.h>
  26 #include <assert.h>
  27 #include <stdio.h>
  28 #include <set>
  29
  30 using RTLIL::id2cstr;
  31
  32 static CellTypes ct, ct_reg;
  33 static int count_rm_cells, count_rm_wires;
  34
  35 static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
  36 {
  37         SigMap assign_map(module);
  38         std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused;
  39
  40         SigSet<RTLIL::Cell*> wire2driver;
  41         for (auto &it : module->cells) {
  42                 RTLIL::Cell *cell = it.second;
  43                 for (auto &it2 : cell->connections) {
  44                         if (!ct.cell_input(cell->type, it2.first)) {
  45                                 RTLIL::SigSpec sig = it2.second;
  46                                 assign_map.apply(sig);
  47                                 wire2driver.insert(sig, cell);
  48                         }
  49                 }
  50                 if (cell->type == "$memwr" || cell->attributes.count("\\keep"))
  51                         queue.insert(cell);
  52                 unused.insert(cell);
  53         }
  54
  55         for (auto &it : module->wires) {
  56                 RTLIL::Wire *wire = it.second;
  57                 if (wire->port_output) {
  58                         std::set<RTLIL::Cell*> cell_list;
  59                         RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
  60                         assign_map.apply(sig);
  61                         wire2driver.find(sig, cell_list);
  62                         for (auto cell : cell_list)
  63                                 queue.insert(cell);
  64                 }
  65         }
  66
  67         while (queue.size() > 0)
  68         {
  69                 std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> new_queue;
  70                 for (auto cell : queue)
  71                         unused.erase(cell);
  72                 for (auto cell : queue) {
  73                         for (auto &it : cell->connections) {
  74                                 if (!ct.cell_output(cell->type, it.first)) {
  75                                         std::set<RTLIL::Cell*> cell_list;
  76                                         RTLIL::SigSpec sig = it.second;
  77                                         assign_map.apply(sig);
  78                                         wire2driver.find(sig, cell_list);
  79                                         for (auto cell : cell_list) {
  80                                                 if (unused.count(cell) > 0)
  81                                                         new_queue.insert(cell);
  82                                         }
  83                                 }
  84                         }
  85                 }
  86                 queue.swap(new_queue);
  87         }
  88
  89         for (auto cell : unused) {
  90                 if (verbose)
  91                         log("  removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
  92                 OPT_DID_SOMETHING = true;
  93                 module->cells.erase(cell->name);
  94                 count_rm_cells++;
  95                 delete cell;
  96         }
  97 }
  98
  99 static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2, SigPool &regs, SigPool &conns)
 100 {
 101         assert(s1.width == 1);
 102         assert(s2.width == 1);
 103         assert(s1.chunks.size() == 1);
 104         assert(s2.chunks.size() == 1);
 105
 106         RTLIL::Wire *w1 = s1.chunks[0].wire;
 107         RTLIL::Wire *w2 = s2.chunks[0].wire;
 108
 109         if (w1 == NULL || w2 == NULL)
 110                 return w2 == NULL;
 111
 112         if (w1->port_input != w2->port_input)
 113                 return w2->port_input;
 114
 115         if (w1->name[0] == '\\' && w2->name[0] == '\\') {
 116                 if (regs.check_any(s1) != regs.check_any(s2))
 117                         return regs.check_any(s2);
 118                 if (conns.check_any(s1) != conns.check_any(s2))
 119                         return conns.check_any(s2);
 120         }
 121
 122         if (w1->port_output != w2->port_output)
 123                 return w2->port_output;
 124
 125         if (w1->name[0] != w2->name[0])
 126                 return w2->name[0] == '\\';
 127
 128         if (w1->attributes.size() != w2->attributes.size())
 129                 return w2->attributes.size() > w1->attributes.size();
 130
 131         return w2->name < w1->name;
 132 }
 133
 134 static bool check_public_name(RTLIL::IdString id)
 135 {
 136         if (id[0] == '$')
 137                 return false;
 138         if (id.substr(0, 2) == "\\_" && (id[id.size()-1] == '_' || id.find("_[") != std::string::npos))
 139                 return false;
 140         if (id.find(".$") != std::string::npos)
 141                 return false;
 142         return true;
 143 }
 144
 145 static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose)
 146 {
 147         SigPool register_signals;
 148         SigPool connected_signals;
 149
 150         if (!purge_mode)
 151                 for (auto &it : module->cells) {
 152                         RTLIL::Cell *cell = it.second;
 153                         if (ct_reg.cell_known(cell->type))
 154                                 for (auto &it2 : cell->connections)
 155                                         if (ct_reg.cell_output(cell->type, it2.first))
 156                                                 register_signals.add(it2.second);
 157                         for (auto &it2 : cell->connections)
 158                                 connected_signals.add(it2.second);
 159                 }
 160
 161         SigMap assign_map(module);
 162         for (auto &it : module->wires) {
 163                 RTLIL::Wire *wire = it.second;
 164                 for (int i = 0; i < wire->width; i++) {
 165                         RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, 1, i), s2 = assign_map(s1);
 166                         if (!compare_signals(s1, s2, register_signals, connected_signals))
 167                                 assign_map.add(s1);
 168                 }
 169         }
 170
 171         module->connections.clear();
 172
 173         SigPool used_signals;
 174         SigPool used_signals_nodrivers;
 175         for (auto &it : module->cells) {
 176                 RTLIL::Cell *cell = it.second;
 177                 for (auto &it2 : cell->connections) {
 178                         assign_map.apply(it2.second);
 179                         used_signals.add(it2.second);
 180                         if (!ct.cell_output(cell->type, it2.first))
 181                                 used_signals_nodrivers.add(it2.second);
 182                 }
 183         }
 184         for (auto &it : module->wires) {
 185                 RTLIL::Wire *wire = it.second;
 186                 if (wire->port_id > 0) {
 187                         RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
 188                         assign_map.apply(sig);
 189                         used_signals.add(sig);
 190                         if (!wire->port_input)
 191                                 used_signals_nodrivers.add(sig);
 192                 }
 193         }
 194
 195         std::vector<RTLIL::Wire*> del_wires;
 196         for (auto &it : module->wires) {
 197                 RTLIL::Wire *wire = it.second;
 198                 if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0) {
 199                         RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1;
 200                         assign_map.apply(s2);
 201                         if (!used_signals.check_any(s2) && wire->port_id == 0) {
 202                                 del_wires.push_back(wire);
 203                         } else {
 204                                 s1.expand();
 205                                 s2.expand();
 206                                 assert(s1.chunks.size() == s2.chunks.size());
 207                                 RTLIL::SigSig new_conn;
 208                                 for (size_t i = 0; i < s1.chunks.size(); i++)
 209                                         if (s1.chunks[i] != s2.chunks[i]) {
 210                                                 new_conn.first.append(s1.chunks[i]);
 211                                                 new_conn.second.append(s2.chunks[i]);
 212                                         }
 213                                 if (new_conn.first.width > 0) {
 214                                         new_conn.first.optimize();
 215                                         new_conn.second.optimize();
 216                                         used_signals.add(new_conn.first);
 217                                         used_signals.add(new_conn.second);
 218                                         module->connections.push_back(new_conn);
 219                                 }
 220                         }
 221                 } else {
 222                         if (!used_signals.check_any(RTLIL::SigSpec(wire)))
 223                                 del_wires.push_back(wire);
 224                 }
 225                 RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire));
 226                 if (!used_signals_nodrivers.check_any(sig)) {
 227                         std::string unused_bits;
 228                         sig.expand();
 229                         for (size_t i = 0; i < sig.chunks.size(); i++) {
 230                                 if (sig.chunks[i].wire == NULL)
 231                                         continue;
 232                                 if (!used_signals_nodrivers.check_any(sig)) {
 233                                         if (!unused_bits.empty())
 234                                                 unused_bits += " ";
 235                                         unused_bits += stringf("%zd", i);
 236                                 }
 237                         }
 238                         if (unused_bits.empty() || wire->port_id != 0)
 239                                 wire->attributes.erase("\\unused_bits");
 240                         else
 241                                 wire->attributes["\\unused_bits"] = RTLIL::Const(unused_bits);
 242                 } else {
 243                         wire->attributes.erase("\\unused_bits");
 244                 }
 245         }
 246
 247         int del_wires_count = 0;
 248         for (auto wire : del_wires)
 249                 if (!used_signals.check_any(RTLIL::SigSpec(wire))) {
 250                         if (check_public_name(wire->name) && verbose) {
 251                                 log("  removing unused non-port wire %s.\n", wire->name.c_str());
 252                                 del_wires_count++;
 253                         }
 254                         module->wires.erase(wire->name);
 255                         count_rm_wires++;
 256                         delete wire;
 257                 }
 258
 259         if (del_wires_count > 0)
 260                 log("  removed %d unused temporary wires.\n", del_wires_count);
 261 }
 262
 263 static void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose)
 264 {
 265         if (verbose)
 266                 log("Finding unused cells or wires in module %s..\n", module->name.c_str());
 267
 268         rmunused_module_cells(module, verbose);
 269         rmunused_module_signals(module, purge_mode, verbose);
 270 }
 271
 272 struct OptCleanPass : public Pass {
 273         OptCleanPass() : Pass("opt_clean", "remove unused cells and wires") { }
 274         virtual void help()
 275         {
 276                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 277                 log("\n");
 278                 log("    opt_clean [options] [selection]\n");
 279                 log("\n");
 280                 log("This pass identifies wires and cells that are unused and removes them. Other\n");
 281                 log("passes often remove cells but leave the wires in the design or reconnect the\n");
 282                 log("wires but leave the old cells in the design. This pass can be used to clean up\n");
 283                 log("after the passes that do the actual work.\n");
 284                 log("\n");
 285                 log("This pass only operates on completely selected modules without processes.\n");
 286                 log("\n");
 287                 log("    -purge\n");
 288                 log("        also remove internal nets if they have a public name\n");
 289                 log("\n");
 290         }
 291         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 292         {
 293                 bool purge_mode = false;
 294
 295                 log_header("Executing OPT_CLEAN pass (remove unused cells and wires).\n");
 296                 log_push();
 297
 298                 size_t argidx;
 299                 for (argidx = 1; argidx < args.size(); argidx++) {
 300                         if (args[argidx] == "-purge") {
 301                                 purge_mode = true;
 302                                 continue;
 303                         }
 304                         break;
 305                 }
 306                 extra_args(args, argidx, design);
 307
 308                 ct.setup_internals();
 309                 ct.setup_internals_mem();
 310                 ct.setup_stdcells();
 311                 ct.setup_stdcells_mem();
 312
 313                 ct_reg.setup_internals_mem();
 314                 ct_reg.setup_stdcells_mem();
 315
 316                 for (auto &mod_it : design->modules) {
 317                         if (!design->selected_whole_module(mod_it.first)) {
 318                                 if (design->selected(mod_it.second))
 319                                         log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name));
 320                                 continue;
 321                         }
 322                         if (mod_it.second->processes.size() > 0) {
 323                                 log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
 324                         } else {
 325                                 rmunused_module(mod_it.second, purge_mode, true);
 326                         }
 327                 }
 328
 329                 ct.clear();
 330                 ct_reg.clear();
 331                 log_pop();
 332         }
 333 } OptCleanPass;
 334
 335 struct CleanPass : public Pass {
 336         CleanPass() : Pass("clean", "remove unused cells and wires") { }
 337         virtual void help()
 338         {
 339                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 340                 log("\n");
 341                 log("    clean [options] [selection]\n");
 342                 log("\n");
 343                 log("This is identical to 'opt_clean', but less verbose.\n");
 344                 log("\n");
 345                 log("When commands are seperated using the ';;' token, this command will be executed\n");
 346                 log("between the commands.\n");
 347                 log("\n");
 348                 log("When commands are seperated using the ';;;' token, this command will be executed\n");
 349                 log("in -purge mode between the commands.\n");
 350                 log("\n");
 351         }
 352         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 353         {
 354                 bool purge_mode = false;
 355
 356                 size_t argidx;
 357                 for (argidx = 1; argidx < args.size(); argidx++) {
 358                         if (args[argidx] == "-purge") {
 359                                 purge_mode = true;
 360                                 continue;
 361                         }
 362                         break;
 363                 }
 364                 if (argidx < args.size())
 365                         extra_args(args, argidx, design);
 366
 367                 ct.setup_internals();
 368                 ct.setup_internals_mem();
 369                 ct.setup_stdcells();
 370                 ct.setup_stdcells_mem();
 371
 372                 ct_reg.setup_internals_mem();
 373                 ct_reg.setup_stdcells_mem();
 374
 375                 count_rm_cells = 0;
 376                 count_rm_wires = 0;
 377
 378                 for (auto &mod_it : design->modules) {
 379                         if (design->selected_whole_module(mod_it.first) && mod_it.second->processes.size() == 0)
 380                                 do {
 381                                         OPT_DID_SOMETHING = false;
 382                                         rmunused_module(mod_it.second, purge_mode, false);
 383                                 } while (OPT_DID_SOMETHING);
 384                 }
 385
 386                 if (count_rm_cells > 0 || count_rm_wires > 0)
 387                         log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 388
 389                 ct.clear();
 390                 ct_reg.clear();
 391         }
 392 } CleanPass;
 393