2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/log.h"
23 #include "kernel/celltypes.h"
29 PRIVATE_NAMESPACE_BEGIN
36 dict
<Module
*, bool> cache
;
38 void reset(Design
*design
= nullptr)
40 this->design
= design
;
44 bool query(Module
*module
)
46 log_assert(design
!= nullptr);
48 if (module
== nullptr)
51 if (cache
.count(module
))
52 return cache
.at(module
);
55 if (!module
->get_bool_attribute("\\keep")) {
56 bool found_keep
= false;
57 for (auto cell
: module
->cells())
58 if (query(cell
)) found_keep
= true;
59 cache
[module
] = found_keep
;
65 bool query(Cell
*cell
)
67 if (cell
->type
.in("$memwr", "$meminit", "$assert", "$assume", "$live", "$fair", "$cover", "$specify2", "$specify3", "$specrule"))
70 if (cell
->has_keep_attr())
73 if (cell
->module
&& cell
->module
->design
)
74 return query(cell
->module
->design
->module(cell
->type
));
80 keep_cache_t keep_cache
;
81 CellTypes ct_reg
, ct_all
;
82 int count_rm_cells
, count_rm_wires
;
84 void rmunused_module_cells(Module
*module
, bool verbose
)
86 SigMap
sigmap(module
);
87 pool
<Cell
*> queue
, unused
;
88 pool
<SigBit
> used_raw_bits
;
89 dict
<SigBit
, pool
<Cell
*>> wire2driver
;
90 dict
<SigBit
, vector
<string
>> driver_driver_logs
;
93 for (auto &it
: module
->connections_
) {
94 for (int i
= 0; i
< GetSize(it
.second
); i
++) {
95 if (it
.second
[i
].wire
!= nullptr)
96 raw_sigmap
.add(it
.first
[i
], it
.second
[i
]);
100 for (auto &it
: module
->cells_
) {
101 Cell
*cell
= it
.second
;
102 for (auto &it2
: cell
->connections()) {
103 if (ct_all
.cell_known(cell
->type
) && !ct_all
.cell_output(cell
->type
, it2
.first
))
105 for (auto raw_bit
: it2
.second
) {
106 if (raw_bit
.wire
== nullptr)
108 auto bit
= sigmap(raw_bit
);
109 if (bit
.wire
== nullptr)
110 driver_driver_logs
[raw_sigmap(raw_bit
)].push_back(stringf("Driver-driver conflict "
111 "for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
112 log_signal(raw_bit
), log_id(cell
), log_id(it2
.first
), log_signal(bit
), log_id(module
)));
113 if (bit
.wire
!= nullptr)
114 wire2driver
[bit
].insert(cell
);
117 if (keep_cache
.query(cell
))
123 for (auto &it
: module
->wires_
) {
124 Wire
*wire
= it
.second
;
125 if (wire
->port_output
|| wire
->get_bool_attribute("\\keep")) {
126 for (auto bit
: sigmap(wire
))
127 for (auto c
: wire2driver
[bit
])
128 queue
.insert(c
), unused
.erase(c
);
129 for (auto raw_bit
: SigSpec(wire
))
130 used_raw_bits
.insert(raw_sigmap(raw_bit
));
134 while (!queue
.empty())
137 for (auto cell
: queue
)
138 for (auto &it
: cell
->connections())
139 if (!ct_all
.cell_known(cell
->type
) || ct_all
.cell_input(cell
->type
, it
.first
))
140 for (auto bit
: sigmap(it
.second
))
144 for (auto bit
: bits
)
145 for (auto c
: wire2driver
[bit
])
147 queue
.insert(c
), unused
.erase(c
);
150 unused
.sort(RTLIL::sort_by_name_id
<RTLIL::Cell
>());
152 for (auto cell
: unused
) {
154 log_debug(" removing unused `%s' cell `%s'.\n", cell
->type
.c_str(), cell
->name
.c_str());
155 module
->design
->scratchpad_set_bool("opt.did_something", true);
156 module
->remove(cell
);
160 for (auto &it
: module
->cells_
) {
161 Cell
*cell
= it
.second
;
162 for (auto &it2
: cell
->connections()) {
163 if (ct_all
.cell_known(cell
->type
) && !ct_all
.cell_input(cell
->type
, it2
.first
))
165 for (auto raw_bit
: raw_sigmap(it2
.second
))
166 used_raw_bits
.insert(raw_bit
);
170 for (auto it
: driver_driver_logs
) {
171 if (used_raw_bits
.count(it
.first
))
172 for (auto msg
: it
.second
)
173 log_warning("%s\n", msg
.c_str());
177 int count_nontrivial_wire_attrs(RTLIL::Wire
*w
)
179 int count
= w
->attributes
.size();
180 count
-= w
->attributes
.count("\\src");
181 count
-= w
->attributes
.count("\\unused_bits");
185 bool compare_signals(RTLIL::SigBit
&s1
, RTLIL::SigBit
&s2
, SigPool
®s
, SigPool
&conns
, pool
<RTLIL::Wire
*> &direct_wires
)
187 RTLIL::Wire
*w1
= s1
.wire
;
188 RTLIL::Wire
*w2
= s2
.wire
;
190 if (w1
== NULL
|| w2
== NULL
)
193 if (w1
->port_input
!= w2
->port_input
)
194 return w2
->port_input
;
196 if ((w1
->port_input
&& w1
->port_output
) != (w2
->port_input
&& w2
->port_output
))
197 return !(w2
->port_input
&& w2
->port_output
);
199 if (w1
->name
[0] == '\\' && w2
->name
[0] == '\\') {
200 if (regs
.check_any(s1
) != regs
.check_any(s2
))
201 return regs
.check_any(s2
);
202 if (direct_wires
.count(w1
) != direct_wires
.count(w2
))
203 return direct_wires
.count(w2
) != 0;
204 if (conns
.check_any(s1
) != conns
.check_any(s2
))
205 return conns
.check_any(s2
);
208 if (w1
->port_output
!= w2
->port_output
)
209 return w2
->port_output
;
211 if (w1
->name
[0] != w2
->name
[0])
212 return w2
->name
[0] == '\\';
214 int attrs1
= count_nontrivial_wire_attrs(w1
);
215 int attrs2
= count_nontrivial_wire_attrs(w2
);
217 if (attrs1
!= attrs2
)
218 return attrs2
> attrs1
;
220 return strcmp(w2
->name
.c_str(), w1
->name
.c_str()) < 0;
223 bool check_public_name(RTLIL::IdString id
)
225 const std::string
&id_str
= id
.str();
226 if (id_str
[0] == '$')
228 if (id_str
.substr(0, 2) == "\\_" && (id_str
[id_str
.size()-1] == '_' || id_str
.find("_[") != std::string::npos
))
230 if (id_str
.find(".$") != std::string::npos
)
235 void rmunused_module_signals(RTLIL::Module
*module
, bool purge_mode
, bool verbose
)
237 SigPool register_signals
;
238 SigPool connected_signals
;
241 for (auto &it
: module
->cells_
) {
242 RTLIL::Cell
*cell
= it
.second
;
243 if (ct_reg
.cell_known(cell
->type
))
244 for (auto &it2
: cell
->connections())
245 if (ct_reg
.cell_output(cell
->type
, it2
.first
))
246 register_signals
.add(it2
.second
);
247 for (auto &it2
: cell
->connections())
248 connected_signals
.add(it2
.second
);
251 SigMap
assign_map(module
);
252 pool
<RTLIL::SigSpec
> direct_sigs
;
253 pool
<RTLIL::Wire
*> direct_wires
;
254 for (auto &it
: module
->cells_
) {
255 RTLIL::Cell
*cell
= it
.second
;
256 if (ct_all
.cell_known(cell
->type
))
257 for (auto &it2
: cell
->connections())
258 if (ct_all
.cell_output(cell
->type
, it2
.first
))
259 direct_sigs
.insert(assign_map(it2
.second
));
261 for (auto &it
: module
->wires_
) {
262 if (direct_sigs
.count(assign_map(it
.second
)) || it
.second
->port_input
)
263 direct_wires
.insert(it
.second
);
266 for (auto &it
: module
->wires_
) {
267 RTLIL::Wire
*wire
= it
.second
;
268 for (int i
= 0; i
< wire
->width
; i
++) {
269 RTLIL::SigBit s1
= RTLIL::SigBit(wire
, i
), s2
= assign_map(s1
);
270 if (!compare_signals(s1
, s2
, register_signals
, connected_signals
, direct_wires
))
275 SigPool raw_used_signals_noaliases
;
276 for (auto &it
: module
->connections_
)
277 raw_used_signals_noaliases
.add(it
.second
);
279 module
->connections_
.clear();
281 SigPool used_signals
;
282 SigPool used_signals_nodrivers
;
283 for (auto &it
: module
->cells_
) {
284 RTLIL::Cell
*cell
= it
.second
;
285 for (auto &it2
: cell
->connections_
) {
286 assign_map
.apply(it2
.second
);
287 used_signals
.add(it2
.second
);
288 raw_used_signals_noaliases
.add(it2
.second
);
289 if (!ct_all
.cell_output(cell
->type
, it2
.first
))
290 used_signals_nodrivers
.add(it2
.second
);
293 for (auto &it
: module
->wires_
) {
294 RTLIL::Wire
*wire
= it
.second
;
295 if (wire
->port_id
> 0) {
296 RTLIL::SigSpec sig
= RTLIL::SigSpec(wire
);
297 assign_map
.apply(sig
);
298 used_signals
.add(sig
);
299 if (!wire
->port_input
)
300 used_signals_nodrivers
.add(sig
);
302 if (wire
->get_bool_attribute("\\keep")) {
303 RTLIL::SigSpec sig
= RTLIL::SigSpec(wire
);
304 assign_map
.apply(sig
);
305 used_signals
.add(sig
);
309 pool
<RTLIL::Wire
*> del_wires_queue
;
310 for (auto wire
: module
->wires())
312 SigSpec s1
= SigSpec(wire
), s2
= assign_map(s1
);
313 log_assert(GetSize(s1
) == GetSize(s2
));
316 if (wire
->attributes
.count("\\init"))
317 initval
= wire
->attributes
.at("\\init");
318 if (GetSize(initval
) != GetSize(wire
))
319 initval
.bits
.resize(GetSize(wire
), State::Sx
);
320 if (initval
.is_fully_undef())
321 wire
->attributes
.erase("\\init");
323 if (GetSize(wire
) == 0) {
324 // delete zero-width wires
325 goto delete_this_wire
;
327 if (wire
->port_id
!= 0 || wire
->get_bool_attribute("\\keep") || !initval
.is_fully_undef()) {
328 // do not delete anything with "keep" or module ports or initialized wires
330 if (!purge_mode
&& check_public_name(wire
->name
)) {
331 // do not get rid of public names unless in purge mode
333 if (!raw_used_signals_noaliases
.check_any(s1
)) {
334 // delete wires that aren't used by anything directly
335 goto delete_this_wire
;
337 if (!used_signals_nodrivers
.check_any(s2
)) {
338 // delete wires that aren't used by anything indirectly, even though other wires may alias it
339 goto delete_this_wire
;
345 del_wires_queue
.insert(wire
);
349 RTLIL::SigSig new_conn
;
350 for (int i
= 0; i
< GetSize(s1
); i
++)
351 if (s1
[i
] != s2
[i
]) {
352 if (s2
[i
] == State::Sx
&& (initval
[i
] == State::S0
|| initval
[i
] == State::S1
)) {
354 initval
[i
] = State::Sx
;
356 new_conn
.first
.append_bit(s1
[i
]);
357 new_conn
.second
.append_bit(s2
[i
]);
359 if (new_conn
.first
.size() > 0) {
360 if (initval
.is_fully_undef())
361 wire
->attributes
.erase("\\init");
363 wire
->attributes
.at("\\init") = initval
;
364 used_signals
.add(new_conn
.first
);
365 used_signals
.add(new_conn
.second
);
366 module
->connect(new_conn
);
369 if (!used_signals_nodrivers
.check_all(s2
)) {
370 std::string unused_bits
;
371 for (int i
= 0; i
< GetSize(s2
); i
++) {
372 if (s2
[i
].wire
== NULL
)
374 if (!used_signals_nodrivers
.check(s2
[i
])) {
375 if (!unused_bits
.empty())
377 unused_bits
+= stringf("%d", i
);
380 if (unused_bits
.empty() || wire
->port_id
!= 0)
381 wire
->attributes
.erase("\\unused_bits");
383 wire
->attributes
["\\unused_bits"] = RTLIL::Const(unused_bits
);
385 wire
->attributes
.erase("\\unused_bits");
390 int del_temp_wires_count
= 0;
391 for (auto wire
: del_wires_queue
) {
392 if (ys_debug() || (check_public_name(wire
->name
) && verbose
))
393 log_debug(" removing unused non-port wire %s.\n", wire
->name
.c_str());
395 del_temp_wires_count
++;
398 module
->remove(del_wires_queue
);
399 count_rm_wires
+= GetSize(del_wires_queue
);
401 if (verbose
&& del_temp_wires_count
)
402 log_debug(" removed %d unused temporary wires.\n", del_temp_wires_count
);
405 bool rmunused_module_init(RTLIL::Module
*module
, bool purge_mode
, bool verbose
)
407 bool did_something
= false;
409 fftypes
.setup_internals_mem();
411 SigMap
sigmap(module
);
412 dict
<SigBit
, State
> qbits
;
414 for (auto cell
: module
->cells())
415 if (fftypes
.cell_known(cell
->type
) && cell
->hasPort("\\Q"))
417 SigSpec sig
= cell
->getPort("\\Q");
419 for (int i
= 0; i
< GetSize(sig
); i
++)
423 if (bit
.wire
== nullptr || bit
.wire
->attributes
.count("\\init") == 0)
426 Const init
= bit
.wire
->attributes
.at("\\init");
428 if (i
>= GetSize(init
) || init
[i
] == State::Sx
|| init
[i
] == State::Sz
)
432 qbits
[bit
] = init
[i
];
436 for (auto wire
: module
->wires())
438 if (!purge_mode
&& wire
->name
[0] == '\\')
441 if (wire
->attributes
.count("\\init") == 0)
444 Const init
= wire
->attributes
.at("\\init");
446 for (int i
= 0; i
< GetSize(wire
) && i
< GetSize(init
); i
++)
448 if (init
[i
] == State::Sx
|| init
[i
] == State::Sz
)
451 SigBit wire_bit
= SigBit(wire
, i
);
452 SigBit mapped_wire_bit
= sigmap(wire_bit
);
454 if (wire_bit
== mapped_wire_bit
)
457 if (qbits
.count(sigmap(SigBit(wire
, i
))) == 0)
460 if (qbits
.at(sigmap(SigBit(wire
, i
))) != init
[i
])
465 log_debug(" removing redundant init attribute on %s.\n", log_id(wire
));
467 wire
->attributes
.erase("\\init");
468 did_something
= true;
472 return did_something
;
475 void rmunused_module(RTLIL::Module
*module
, bool purge_mode
, bool verbose
, bool rminit
)
478 log("Finding unused cells or wires in module %s..\n", module
->name
.c_str());
480 std::vector
<RTLIL::Cell
*> delcells
;
481 for (auto cell
: module
->cells())
482 if (cell
->type
.in("$pos", "$_BUF_")) {
483 bool is_signed
= cell
->type
== "$pos" && cell
->getParam("\\A_SIGNED").as_bool();
484 RTLIL::SigSpec a
= cell
->getPort("\\A");
485 RTLIL::SigSpec y
= cell
->getPort("\\Y");
486 a
.extend_u0(GetSize(y
), is_signed
);
487 module
->connect(y
, a
);
488 delcells
.push_back(cell
);
490 for (auto cell
: delcells
) {
492 log_debug(" removing buffer cell `%s': %s = %s\n", cell
->name
.c_str(),
493 log_signal(cell
->getPort("\\Y")), log_signal(cell
->getPort("\\A")));
494 module
->remove(cell
);
496 if (!delcells
.empty())
497 module
->design
->scratchpad_set_bool("opt.did_something", true);
499 rmunused_module_cells(module
, verbose
);
500 rmunused_module_signals(module
, purge_mode
, verbose
);
502 if (rminit
&& rmunused_module_init(module
, purge_mode
, verbose
))
503 rmunused_module_signals(module
, purge_mode
, verbose
);
506 struct OptCleanPass
: public Pass
{
507 OptCleanPass() : Pass("opt_clean", "remove unused cells and wires") { }
508 void help() YS_OVERRIDE
510 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
512 log(" opt_clean [options] [selection]\n");
514 log("This pass identifies wires and cells that are unused and removes them. Other\n");
515 log("passes often remove cells but leave the wires in the design or reconnect the\n");
516 log("wires but leave the old cells in the design. This pass can be used to clean up\n");
517 log("after the passes that do the actual work.\n");
519 log("This pass only operates on completely selected modules without processes.\n");
522 log(" also remove internal nets if they have a public name\n");
525 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
527 bool purge_mode
= false;
529 log_header(design
, "Executing OPT_CLEAN pass (remove unused cells and wires).\n");
533 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
534 if (args
[argidx
] == "-purge") {
540 extra_args(args
, argidx
, design
);
542 keep_cache
.reset(design
);
544 ct_reg
.setup_internals_mem();
545 ct_reg
.setup_stdcells_mem();
547 ct_all
.setup(design
);
552 for (auto module
: design
->selected_whole_modules_warn()) {
553 if (module
->has_processes_warn())
555 rmunused_module(module
, purge_mode
, true, true);
558 if (count_rm_cells
> 0 || count_rm_wires
> 0)
559 log("Removed %d unused cells and %d unused wires.\n", count_rm_cells
, count_rm_wires
);
572 struct CleanPass
: public Pass
{
573 CleanPass() : Pass("clean", "remove unused cells and wires") { }
574 void help() YS_OVERRIDE
576 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
578 log(" clean [options] [selection]\n");
580 log("This is identical to 'opt_clean', but less verbose.\n");
582 log("When commands are separated using the ';;' token, this command will be executed\n");
583 log("between the commands.\n");
585 log("When commands are separated using the ';;;' token, this command will be executed\n");
586 log("in -purge mode between the commands.\n");
589 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
591 bool purge_mode
= false;
594 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
595 if (args
[argidx
] == "-purge") {
601 if (argidx
< args
.size())
602 extra_args(args
, argidx
, design
);
604 keep_cache
.reset(design
);
606 ct_reg
.setup_internals_mem();
607 ct_reg
.setup_stdcells_mem();
609 ct_all
.setup(design
);
614 for (auto module
: design
->selected_whole_modules()) {
615 if (module
->has_processes())
617 rmunused_module(module
, purge_mode
, ys_debug(), false);
621 if (count_rm_cells
> 0 || count_rm_wires
> 0)
622 log("Removed %d unused cells and %d unused wires.\n", count_rm_cells
, count_rm_wires
);
634 PRIVATE_NAMESPACE_END